JPS59187224U - Variable limit length circuit - Google Patents
Variable limit length circuitInfo
- Publication number
- JPS59187224U JPS59187224U JP8115783U JP8115783U JPS59187224U JP S59187224 U JPS59187224 U JP S59187224U JP 8115783 U JP8115783 U JP 8115783U JP 8115783 U JP8115783 U JP 8115783U JP S59187224 U JPS59187224 U JP S59187224U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- variable limit
- limit length
- length circuit
- differential amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のリミッタ回路の具体的な構成図、−第２
図は本考案の一実施例を示すリミッタ回路の具体的な構
成図である。
７．８・・・増幅器、９． １４． １５・・・抵抗、
１０゜１１・・・ダイオード、１２．１３・・・差動増
幅器、１６・・・可変抵抗。Figure 1 is a specific configuration diagram of a conventional limiter circuit.
The figure is a specific configuration diagram of a limiter circuit showing an embodiment of the present invention. 7.8...Amplifier, 9. 14. 15...Resistance,
10゜11...Diode, 12.13...Differential amplifier, 16...Variable resistor.
Claims (1)
ードと直列接続の差動増幅器と、該差動増幅器の入力電
圧を設定する可変抵抗とよりなり、入力信号の中心電圧
に対して対称な２つのバイアス電圧を発生するための電
圧発生回路を設け、該バイアス電圧を前記２つのダイオ
ードに各々印加し、該電圧より大きい（または小さい）
電圧の信号が印加された場合は出力電圧値をそれ以上太
きく （または小さく）シないように構成したことを特
徴とする可変リミツテング回路。It consists of a diode connected antiparallel to the input signal, a differential amplifier connected in series with the diode, and a variable resistor that sets the input voltage of the differential amplifier. A voltage generation circuit for generating two bias voltages is provided, and the bias voltage is applied to each of the two diodes, and the bias voltage is larger (or smaller than the voltage).
A variable limit circuit characterized in that the output voltage value does not increase (or decrease) further when a voltage signal is applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8115783U JPS59187224U (en) | 1983-05-31 | 1983-05-31 | Variable limit length circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8115783U JPS59187224U (en) | 1983-05-31 | 1983-05-31 | Variable limit length circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59187224U true JPS59187224U (en) | 1984-12-12 |
Family
ID=30211127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8115783U Pending JPS59187224U (en) | 1983-05-31 | 1983-05-31 | Variable limit length circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59187224U (en) |
-
1983
- 1983-05-31 JP JP8115783U patent/JPS59187224U/en active Pending
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