JPS59186445A - Bus receiver with equalizing function - Google Patents
Bus receiver with equalizing functionInfo
- Publication number
- JPS59186445A JPS59186445A JP6141183A JP6141183A JPS59186445A JP S59186445 A JPS59186445 A JP S59186445A JP 6141183 A JP6141183 A JP 6141183A JP 6141183 A JP6141183 A JP 6141183A JP S59186445 A JPS59186445 A JP S59186445A
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- equalization
- station
- transmission
- receiver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
- Amplifiers (AREA)
- Dc Digital Transmission (AREA)
- Small-Scale Networks (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はデータウェイのパスレシーバに関し、更に詳し
くはその内部に等化機能をもたせて通信ラインの高速化
、長距離化を図ることができるようにしたパスレシーバ
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data way path receiver, and more particularly to a path receiver that is provided with an equalization function to increase the speed and distance of a communication line.
伝送線路(同軸ケーブルが多い)1本を複数の機器で共
有する所謂データウェイは広く普及しており、第1図に
その構成例を示す。図はリニア形のデータウェイを示し
ている。図において、81〜5n(nは整数、以下同じ
)はステーション、T1〜Tnはトランシーバ、A1〜
Anは結合器、DBは伝送線路で必る0各ステ一ジ日ン
81〜S11!:伝送線路DBとはパス結合器A1〜A
nによって行われ、トランシーバT1〜Tnによって論
理レベルに変換される。このような構成のデータウェイ
では、伝送長やステーション数に対する制限は、減衰、
帯域及び反射によって決定される。即ち、負荷(ステー
ション)数が増すと挿入による減衰増加と反射増加が生
じる。1だ、ケーブル長が増すと減衰と帯域制限が増加
する。A so-called data way, in which a single transmission line (often a coaxial cable) is shared by multiple devices, is widely used, and an example of its configuration is shown in FIG. The figure shows a linear dataway. In the figure, 81 to 5n (n is an integer, the same applies hereinafter) are stations, T1 to Tn are transceivers, and A1 to
An is a coupler, DB is a transmission line, and each stage is 81 to S11! : Transmission line DB is path coupler A1-A
n and converted to logic levels by transceivers T1-Tn. In dataways configured in this way, limitations on transmission length and number of stations are limited by attenuation,
Determined by band and reflection. That is, as the number of loads (stations) increases, attenuation increases and reflections increase due to insertion. 1. As cable length increases, attenuation and bandwidth limiting increase.
第2図は信号の伝播特性を示す図でめる。図において、
(a)はステーションS1の、(b)はステージ曽ンS
2の、(C)はステーションSnのそれぞれ受信信号波
形を示している。ステージ□ンSにおいては、受信信号
が減衰しかつ波形がな1っていることがわかる。
゛ 、
へまだ、ケーブル長が増すと減衰と帯域制限が増かしな
がら、データウェイの場合、伝送経路が通信ごとに変わ
るため等化を行わないのが一般的であった。このため、
1対1伝送の場合に比べ第1図のリニア形データウェイ
の場合、伝送長が大幅に制限されていた1、
本発明はこのような点に鑑みてなされたものでアって、
各ステーションごとのパスレシーハニ適当な波形等化機
能をもたせて通信ラインの高速化、長距離化を図ること
ができるパスレシーバを実現したものである。FIG. 2 is a diagram showing the signal propagation characteristics. In the figure,
(a) of station S1, (b) of stage S
2, (C) shows the respective received signal waveforms of station Sn. It can be seen that at stage S, the received signal is attenuated and its waveform becomes flat.
However, as the length of the cable increases, attenuation and bandwidth limitations increase, and in the case of dataways, the transmission path changes for each communication, so equalization is not generally performed. For this reason,
Compared to the case of one-to-one transmission, the transmission length of the linear dataway shown in Fig. 1 is significantly limited1.The present invention has been made in view of these points.
The present invention realizes a path receiver that is equipped with an appropriate waveform equalization function for each station, thereby increasing the speed and distance of communication lines.
以下、図面を参照して本発明の詳細な説明する。Hereinafter, the present invention will be described in detail with reference to the drawings.
第3図は、トランシーバの構成を示す図である。FIG. 3 is a diagram showing the configuration of the transceiver.
図において、1は伝送線路DBに取付けられた結合器、
2は送信用ドライバ、6は受信用アンプ、4は該アンプ
の出力を受りる識別器である。アンプ3と識別器4とで
パスレシーバを構成し、アンプ3に等化機能を設けてい
る。第4図は信号の伝達特性を示す図である。横軸は周
波数、縦軸はゲインである。f はステーションS2
(第1図参照)1
の、fB2はステーションSnの特性を示し、それぞれ
において1は等化なしの場合を、2は等化適性の場合を
、5は等化不適の場合をそれぞれ示している。第5図は
伝送波形を示す図であシ、(a)はステーションSの、
(b)はステージ□ンS2の伝送波形を示している。図
中の番号1〜5は第4図のそれと同じである。1は等化
がない場合であり、近くのステーションでは適であるが
、遠くのステーションでは不適となる。5はステージ菖
ンSで完全な波形が得られるように等化を行った場合で
ろるが、このようにするとステージ苔ンS2で等化が大
きくなりすぎる。これに対し、2ではステーションSn
では等化不足でらるが、その代わシステーシ四ンS2で
もそれほど波形の劣化が生じていない。In the figure, 1 is a coupler attached to the transmission line DB;
2 is a transmitting driver, 6 is a receiving amplifier, and 4 is a discriminator that receives the output of the amplifier. The amplifier 3 and the discriminator 4 constitute a path receiver, and the amplifier 3 is provided with an equalization function. FIG. 4 is a diagram showing signal transfer characteristics. The horizontal axis is frequency and the vertical axis is gain. f is station S2
(See Figure 1) 1 and fB2 indicate the characteristics of station Sn, where 1 indicates no equalization, 2 indicates appropriate equalization, and 5 indicates unsuitable equalization. . FIG. 5 is a diagram showing transmission waveforms, (a) of station S;
(b) shows the transmission waveform of stage S2. Numbers 1 to 5 in the figure are the same as those in FIG. 1 is the case without equalization, which is appropriate for nearby stations but inappropriate for distant stations. 5 is possible if equalization is performed so that a complete waveform can be obtained at stage S, but if this is done, the equalization will be too large at stage S2. On the other hand, in 2, station Sn
In this case, the equalization is insufficient, but on the other hand, the waveform does not deteriorate much even in the system S2.
このことから、ステーションSにおける等化不足量とス
テーションS2における等化オーバー量が等しくなるよ
うに等化量を設定した等化機能をアンプ3(第5図)に
持たせれば、信号の減衰しないデータウェイを実現する
ことができることになる。From this, if the amplifier 3 (Fig. 5) is equipped with an equalization function that sets the equalization amount so that the underequalization amount at station S and the overequalization amount at station S2 are equal, the signal will not be attenuated. This will make it possible to realize a data way.
第6図は、等化機能をもった受信用アンプの一構成を示
す電気回路図でおる。図に示すアンプは、トランジスタ
Q□、Q2を用いた差動増幅器により構成されており、
トランジスタQ工、Q2のエミッタ間に接続されたRC
直列回路10が等化回路をなしている。コレクタ抵抗値
をRL、 エミッタ抵抗値をREとすれば、このアンプ
のゲインGは次式で与えられる。FIG. 6 is an electrical circuit diagram showing one configuration of a receiving amplifier having an equalization function. The amplifier shown in the figure is composed of a differential amplifier using transistors Q□ and Q2.
RC connected between the emitter of transistor Q and Q2
The series circuit 10 constitutes an equalization circuit. If the collector resistance value is RL and the emitter resistance value is RE, then the gain G of this amplifier is given by the following equation.
ω:角周波数
TloR+ 2RE
T2″′CR
今、ステーションS1がらステージ曹ンsnへの伝達特
性をG、ステーションs2への伝達特性を02とすると
、これらはそれぞれ次式で与えられる。ω: Angular frequency TloR+ 2RE T2'''CR Now, assuming that the transfer characteristic from station S1 to stage sn sn is G and the transfer characteristic to station s2 is 02, these are given by the following equations.
n 1+jωTi
(2)G2”1(3)
KL、 T9.:定数
Gn”2を式(1)に等化すると、次のようになる。n 1+jωTi
(2) G2''1 (3) KL, T9.: When the constant Gn''2 is equalized to equation (1), it becomes as follows.
1+%T1(5)
G21=G2°G′″Ko 1+j(支)T2ここで、
Ti=T□となるように選ぶと、GnはQnlに等化さ
れる(下式参照)。1+%T1(5) G21=G2°G′″Ko 1+j (support) T2 where,
When selecting Ti=T□, Gn is equalized to Qnl (see the formula below).
G1=に9.に□(6)
01+JωT2
G2!=Ko刊茫 (7)ここで、第7
図(、)、 (b)に示すようにステーションS2にお
ける波形の偏差Δと、ステーシロンSにおn
ける波形偏差Δを等しくすることを考える。G1=9. ni□(6) 01+JωT2 G2! =Ko Kansu (7) Here, the 7th
Consider making the waveform deviation Δ at station S2 equal to the waveform deviation Δ at station S, as shown in FIGS.
両者が等しい条件はT9.= 2T2do)このとき、
(6)式は次式で与えられる。The condition that both are equal is T9. = 2T2do) At this time,
Equation (6) is given by the following equation.
a l=に1!、−に−トr(n)
n01+jω丁
αη式より、(2)式で表わされる帯域の2倍の帯域が
得られる。即ち、椿めて簡単な構成で伝送距離をのばす
ことができ、或いは伝送速度を2倍にすることができる
。第7図(、)はステーシロンS2・Snの無等化時の
受信波形を、(b)は等化後の受信波形を示す図である
。何れも1はS2の2はSnのそれぞれ波形を示してい
る。a l = 1! , −to−tr(n) n01+jωdαη From the equation, a band twice as large as the band expressed by equation (2) can be obtained. That is, the transmission distance can be extended or the transmission speed can be doubled with an extremely simple configuration. FIG. 7(,) shows the received waveform of the stacylons S2 and Sn when they are not equalized, and FIG. 7(b) shows the received waveform after equalization. In each case, 1 indicates the waveform of S2, and 2 indicates the waveform of Sn.
以上、詳細に説明したように、本発明によれば各ステー
シロンごとのパスレシーバに適当な波形等化機能をもた
せて通信ラインの高速化、長距離化を図ることができる
パスレシーバを実現することができる。As described in detail above, according to the present invention, it is possible to realize a path receiver that can increase the speed and distance of a communication line by providing a suitable waveform equalization function to the path receiver of each station. I can do it.
第1図はデータウェイの構成を示す図、第2図は信号の
伝播特性を示す図、第5図はトランシーバの構成を示す
図、第4図は信号の伝達特性を示す図、第5図は伝送波
形を示す図、第6図は受信中
用アンプの具体的構成の例を示す電気回路図、第7図は
波形偏差を示す図である。
S1〜Sn・・・ステーション、T1〜Tn・・・トラ
ンシーバ、A1〜An・・結合器、DB・・・伝送線路
、1・・・結合器、2ドライバ、3・・・アンプ、4・
・・識別器、10・・・等化回路、Ql、G2・・・ト
ランジスタ。
第1図
第2図
第3図
第4図
(J
第5図
第6 図
CC
第7図Fig. 1 shows the configuration of the dataway, Fig. 2 shows the signal propagation characteristics, Fig. 5 shows the transceiver configuration, Fig. 4 shows the signal transfer characteristics, Fig. 5 6 is a diagram showing a transmission waveform, FIG. 6 is an electric circuit diagram showing an example of a specific configuration of an amplifier for receiving, and FIG. 7 is a diagram showing waveform deviation. S1-Sn...Station, T1-Tn...Transceiver, A1-An...Coupler, DB...Transmission line, 1...Coupler, 2 Driver, 3...Amplifier, 4...
... Discriminator, 10... Equalization circuit, Ql, G2... Transistor. Figure 1 Figure 2 Figure 3 Figure 4 (J Figure 5 Figure 6 Figure CC Figure 7
Claims (2)
ンステムにおいて各ステージ四ン入ロ部に取付けられた
パスレシーバであって、複数個のステージg/が接続さ
れた場合におけるゲインの高周波領域における減衰特性
を補償するための等化特性を具備したアンプをその内部
に設けたことを特徴とする等化機能付パスレシーバ。(1) A pass receiver installed in the four-input part of each stage in a data unit system to which multiple stations are connected, and attenuation in the high frequency region of the gain when multiple stages g/ are connected. A path receiver with an equalization function, characterized in that an amplifier having an equalization characteristic for compensating the characteristics is provided inside the receiver.
化特性をもたせたことを特徴とする特許請求の範囲第1
項記載の等化機能付パスレシーバ。(2) When the transmission characteristic G of the communication line is expressed by G = x: i n 1 + j ω T ω: angular wave number KL, TL: constant, it is characterized by having an equalization characteristic expressed as the equalization characteristic G. Claim 1:
Pass receiver with equalization function as described in section.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6141183A JPS59186445A (en) | 1983-04-07 | 1983-04-07 | Bus receiver with equalizing function |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6141183A JPS59186445A (en) | 1983-04-07 | 1983-04-07 | Bus receiver with equalizing function |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59186445A true JPS59186445A (en) | 1984-10-23 |
JPH0544211B2 JPH0544211B2 (en) | 1993-07-05 |
Family
ID=13170349
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6141183A Granted JPS59186445A (en) | 1983-04-07 | 1983-04-07 | Bus receiver with equalizing function |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59186445A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5223241A (en) * | 1975-08-15 | 1977-02-22 | Fujitsu Ltd | Frequency compensation system |
JPS52116156A (en) * | 1976-03-26 | 1977-09-29 | Iwatsu Electric Co Ltd | Wide-band amplifier circuit |
JPS5379306A (en) * | 1976-12-24 | 1978-07-13 | Hitachi Ltd | Dp sugnal transmission system |
JPS54115010A (en) * | 1978-02-28 | 1979-09-07 | Fujitsu Ltd | Communication system |
-
1983
- 1983-04-07 JP JP6141183A patent/JPS59186445A/en active Granted
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5223241A (en) * | 1975-08-15 | 1977-02-22 | Fujitsu Ltd | Frequency compensation system |
JPS52116156A (en) * | 1976-03-26 | 1977-09-29 | Iwatsu Electric Co Ltd | Wide-band amplifier circuit |
JPS5379306A (en) * | 1976-12-24 | 1978-07-13 | Hitachi Ltd | Dp sugnal transmission system |
JPS54115010A (en) * | 1978-02-28 | 1979-09-07 | Fujitsu Ltd | Communication system |
Also Published As
Publication number | Publication date |
---|---|
JPH0544211B2 (en) | 1993-07-05 |
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