JPS59181882A - Video display device - Google Patents
Video display deviceInfo
- Publication number
- JPS59181882A JPS59181882A JP5563983A JP5563983A JPS59181882A JP S59181882 A JPS59181882 A JP S59181882A JP 5563983 A JP5563983 A JP 5563983A JP 5563983 A JP5563983 A JP 5563983A JP S59181882 A JPS59181882 A JP S59181882A
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- data
- signal
- memory
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/66—Transforming electric information into light information
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Transforming Electric Information Into Light Information (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は多数個配列された発光素子を、映像信号と［７
てのデイノタル化された階日周データに７１応じて点灯
させる映像表示装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention uses a large number of arranged light emitting elements to communicate video signals and [7]
The present invention relates to a video display device that lights up in accordance with 71 diurnal data of the floor.
この種の従来の装置は第１図に示すように、アンテナｊ
１で受信された映像信号が、増幅および）′べ局等を行
う受信部１２を介して映像イ計吋発生装置］３に加えら
れる。この映像信号発生装置〕３はアナログ信号全デイ
ノタル信号に変換するとともに、この映像信号が映像画
面を構成する発光素子の発光階調の何れに属するかを判
定してデイノタル化された階調データを発生する。一方
、受信部１２には同期信号検出回路１４が接続さね、で
おり、この同期信号検出回路１４の出力に基いてタイミ
ング信号発生部１５が鳶き込み、読出し信号Ｒ／Ｗ、行
選択用のアドレス信号ＲＡＤＤ、列選択用のアドレス信
号ＣＤＤおよびラッチ信号ＲＡＴ’ｉ出力し、さらに、
同期信号検出回路１４の出力信号に基いてカウンタ１６
が映像の略１ノーンに対応する時間を経過する毎にクリ
ヤされ、且つ、この時間内に順次階調数に応じた値まで
ノベルが１づつ増える階調レベル信号ＵＩ”Ｄ全出力し
ている。This type of conventional device has an antenna j as shown in FIG.
The video signal received at 1 is applied to a video signal generator 3 via a receiving section 12 which performs amplification, broadcasting, etc. This video signal generator] 3 converts the analog signal into an all-day notar signal, determines which of the light emission gradations of the light emitting elements constituting the video screen this video signal belongs to, and generates the de-notalized gradation data. Occur. On the other hand, a synchronization signal detection circuit 14 is connected to the reception section 12, and a timing signal generation section 15 generates a read signal R/W and a row selection signal based on the output of this synchronization signal detection circuit 14. address signal RADD, address signal CDD for column selection, and latch signal RAT'i, and further,
Based on the output signal of the synchronization signal detection circuit 14, the counter 16
is cleared every time a time corresponding to approximately one tone of the video elapses, and the gradation level signal UI"D is fully outputted, and the novel value increases by 1 one by one up to a value corresponding to the number of gradations within this time. .
ここで、映像信号発生装置１３の出力端には、タイミン
グ信号発生部１５の貫き込み、読出し信号Ｗ／Ｒおよび
アドレス信号ＲＡＤＤ 、 ＯＡ、ＤＤ によって一
画面分の階調データを記憶する表示メモリ１７が設けら
れており、ちょうど一画面分の階調データの書き込みを
終了した時点で、この階調データが読み出されて表示制
御回路２０に加えられる。Here, at the output end of the video signal generator 13, there is a display memory 17 that stores one screen worth of gradation data according to the penetration of the timing signal generator 15, the readout signal W/R, and the address signals RADD, OA, and DD. is provided, and just when writing of the gradation data for one screen is completed, this gradation data is read out and applied to the display control circuit 20.
この表示制御回路加はアドレス信号ＲＡＤＤによって作
動する行選択デコーダ、アドレス信号ＣＡＤＤおよびラ
ッチ信号ＲＡＴによって作動する列選択デコーダ２２、
発光素子のそれぞれに対応してマトリクス状に配置され
るラッチｎおよびコン・ぐレータＵ等をそなえており、
前記表示メモリ丘から読み出された発光素子毎の階調デ
ータがラッチ乙に記憶されるとともに、ラッチ乙の階調
データの数値が階調レベ信号ＩＪＰＤの値より大きくな
っている期間、表示信号Ｓｏｏ −Ｓｍｎを出力する。This display control circuit includes a row selection decoder 22 operated by an address signal RADD, a column selection decoder 22 operated by an address signal CADD and a latch signal RAT;
It is equipped with latches N and condurators U arranged in a matrix corresponding to each of the light emitting elements.
The gradation data for each light emitting element read from the display memory hill is stored in the latch O, and during the period when the numerical value of the gradation data in the latch B is larger than the value of the gradation level signal IJPD, the display signal is Output Soo-Smn.
また、表示信号Ｂｏｏ〜Ｓｍｎ”：ｔ、トランゾスタ等
のスイッチング素子をそなえる表示駆動回路（９）に加
えられ、この表示駆動制御回路３０が表示器４０の映像
画面を形成する発光素子４１を点灯させることになる。In addition, the display signal Boo~Smn":t is added to the display drive circuit (9) that includes switching elements such as transistors, and this display drive control circuit 30 lights up the light emitting element 41 that forms the video screen of the display 40. It turns out.
かくして、発光素子４１は階調データの値に応じた時間
だけ点灯され、結局、映像信号に対応する画像が表示器
４０に映出される。In this way, the light emitting element 41 is turned on for a period of time corresponding to the value of the gradation data, and eventually an image corresponding to the video signal is displayed on the display 40.
なυ、表示メモリ１７のｌＹｉ調データが表示制御回路
加のラッチおに記憶されている間、表示メモリ１７には
次の７−ンに対応する゛一画面分の階調データが禽き込
まれ、以下、上述した操作が順次繰返される。While the Yi tone data in the display memory 17 is stored in the latch of the display control circuit, the display memory 17 is filled with tone data for one screen corresponding to the next 7-tone. Then, the above-described operations are sequentially repeated.
ところで、表示器４０を構成する発光素子４１としては
電球、発光ダイオード、陰極線管（ＣＲＴ）等が用いら
れるが、縦横に多数（１５１配列される発光素子には、
一定の入力に対して略等しい発光特性を持つものが要求
される。By the way, light bulbs, light emitting diodes, cathode ray tubes (CRTs), etc. are used as the light emitting elements 41 constituting the display 40.
It is required that the light emitting characteristics be approximately the same for a given input.
このため、従来は発光特性が類似した発光素子を選別し
たり、あるいは、発光素子毎に光量調整回路を設けたり
していたが、１つの表示器に数万個の発光素子を用いる
ものにあっては、発光特性の類似する素子金揃えること
が極めて難１．＜、結局、光量調整回路を設置しなけれ
ば、発光素子間の光ｉｔのバラツキを補正することがで
きないものとされていた。For this reason, conventional methods have been to select light-emitting elements with similar light-emitting characteristics, or to provide a light intensity adjustment circuit for each light-emitting element, but this has been difficult since tens of thousands of light-emitting elements are used in one display. 1. It is extremely difficult to align elements with similar light emitting characteristics. <In the end, it was considered that it was not possible to correct variations in light IT between light emitting elements unless a light amount adjustment circuit was installed.
しかしながら、数万個に及ぶ発光素子の人々に光量調整
回路を設けることは現実的には雉しく、第１図に示す従
来の映［象表示装置はかかる尤π調り多回路を持たず、
階調データに対応した画像を忠実に映出すことかでへな
竜、八という欠点があった。However, it is practically difficult to provide a light amount adjustment circuit for tens of thousands of light emitting elements, and the conventional image display device shown in FIG. 1 does not have such a multi-circuit.
The drawback was that it was difficult to faithfully display images that corresponded to gradation data.
本発明はト記従来のものの欠点全除去する。′こめにな
されたもので、光量調整回路を用いるＣとなく、値の等
し７い階調データにχ・ｔ（７て映欧両面を構成する多
数の発光素：ｒ−の光量全均一化１．得、これによって
階、１）’、１７−タに７ｉ応した忠実な画像全映出し
得る映像表示装置の提供を目的と−とる。The present invention eliminates all the drawbacks of the prior art. It was made specifically for χ・t (7), which uses a light intensity adjustment circuit to apply 7 gradation data of equal values to the large number of light emitting elements that make up both sides of the screen: the light intensity of r- is completely uniform. The object of the present invention is to provide a video display device capable of faithfully displaying the entire image in accordance with the 7i standard.
この目的を達成するために本発明の映像表示装置は、多
数の発光素子を配列して映像画面全形成した表示器と、
映像信号としてディノタル化された階調データを出力す
る信号発生手段と、Ｍｉ前記表示器の少なくとも一画面
に対応する階Ａ７″−夕を記憶させる第１のメモリと、
Ａｉｌ記映１＃画面を検数に分けたブロック毎に設けら
れ、このブロック内の前記発光素子を順次点灯させる定
電圧全供給するとともに、この発光素イ、り電流を検出
する電流検出部と、この電流検出部の出力信号に基づき
、ブロック内のｉ１ｓ記発光素子の平均電流に対する各
発光素子の電流偏差分を階調データの階差に換算して出
力する信号処理手段と、この信号処理手段のデータ全記
憶させる第２のメモリと、曲記第１のメモリの階調デー
タ’ｃ Ｍ記第２のメモリのデータによって補正して出
力する演算回路と、この演算回路より出力される階調デ
ータに対応する時間だけ前記発光素子を点灯させる表示
制御回路とを具備したことを特徴とするものである。In order to achieve this object, the video display device of the present invention includes a display device in which a large number of light emitting elements are arranged to form the entire video screen;
a signal generating means for outputting dinotalized gradation data as a video signal; a first memory for storing floor A7''-Y corresponding to at least one screen of the display device;
A current detection section is provided for each block in which the Ail recording 1# screen is divided into numbers, and supplies a constant voltage to sequentially light up the light emitting elements in this block, and detects the current of the light emitting elements. , a signal processing means for converting the current deviation of each light emitting element with respect to the average current of the i1s light emitting elements in the block into a difference in gradation data based on the output signal of the current detection section, and outputting the converted signal; a second memory for storing all the data of the means; an arithmetic circuit that corrects and outputs the gradation data of the first memory; The present invention is characterized by comprising a display control circuit that lights up the light emitting element for a time corresponding to tone data.
以下、添付図面を参照して本発明の一実施例について説
明する。Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.
第２図は本発明に係る映像表示装置の構成例を示すブロ
ック図で、第１図と同一の符号を付したものはそれぞれ
同一の要素を示している。そして、映像画面（！７複数
に分けたブロック毎に設けられ、このグロック内の発光
素子を順次点灯させる定電圧を供給するととも（で、こ
れらの発光素子の電流をそれぞれ検出する電流検出部（
資）と、この電流検出部間の出力信号全処理し７易いよ
うに例えば増幅するための入力部５Ｑａと、この入力部
５０ ａ ｆ介して得られる信号に基づきブロック内の
全発光素子の平均電流に対する各発光素子の電流偏差分
を階調データの階差に換算して出力する信号処理手段と
しての操作部６１およびデータ処理部６２と、データ処
理部６２の出力データを記憶させる光計補正メモリ６３
と、操作部６１の操作信号により切替操作され、書き込
み読み出し信号Ｒ／Ｗ、アドレス信号ＲＡＤＤ 、 Ｃ
ＡＤＤ全表示メモリ１７に与える代わりに光量補正メモ
リ６３に加える切替スイッチ６４と、表示メモリ１７お
よび光量補正メモリ６３から読み出されデータを加え合
わせて表示制御回路かに加える累算器６５とが新たに付
加されている。FIG. 2 is a block diagram showing an example of the configuration of a video display device according to the present invention, and the same reference numerals as in FIG. 1 indicate the same elements. The video screen (!7) is provided for each block divided into multiple blocks, and supplies a constant voltage that sequentially lights up the light emitting elements in this Glock (and a current detection unit that detects the current of each of these light emitting elements).
input section 5Qa for amplification to facilitate processing of all the output signals between this current detection section, and an average of all light emitting elements in the block based on the signal obtained through this input section 50a. An operation unit 61 and a data processing unit 62 as signal processing means that convert the current deviation of each light emitting element with respect to the current into a difference in gradation data and output it, and a photometer correction that stores the output data of the data processing unit 62. memory 63
, the write/read signal R/W, address signals RADD, C are switched by operation signals from the operation unit 61.
A changeover switch 64 that adds data to the light amount correction memory 63 instead of the ADD full display memory 17, and an accumulator 65 that adds data read from the display memory 17 and the light amount correction memory 63 and adds it to the display control circuit are new. is added to.
第３図は電流検出部５０の要部の詳細な構成を示し、■
ブロックに属する発光素子４１の一端が共通接続される
とともに電流検出回路５１を介して一方の電源端子５３
に接続され、さらに、発光素子４１のそれぞれの他端に
はトランゾスタ５２のコレクタが接続されており、これ
らのトランジスタ５２のエミッタは他方の電源端子５４
に共通接続され、１だ、これらのトランジスタ５２のベ
ースはそれぞれ個別に制御信号Ｓ１を加えるための端子
５５に接続されている。FIG. 3 shows the detailed configuration of the main parts of the current detection section 50, and
One end of the light emitting elements 41 belonging to the block is connected in common, and one end of the light emitting element 41 belonging to the block is connected to one power terminal 53 via the current detection circuit 51.
Furthermore, the collectors of transistors 52 are connected to the other ends of the light emitting elements 41, and the emitters of these transistors 52 are connected to the other power terminal 54.
The bases of these transistors 52 are each individually connected to a terminal 55 for applying a control signal S1.
また、第４図は累算器６５の詳細な構成を示し、表示メ
モ＋１１７および光量補正メモリ６３からそれぞれ読み
出さ′Ｉ′１だ階調データＤＩおよび光量補正データＤ
２を加減算する加減算回路６５１、この加減算回路６５
１の出力および桁上がり信号Ｃの論理和を求めるＯＲ回
路６５２、および、加減算回路６５２の桁下りイ菖号Ｂ
を反転させた値とＯＲ回路６５２の出力の論理積を求め
るＡＮＤ回路６５３とで構成されている。FIG. 4 shows a detailed configuration of the accumulator 65, in which gradation data DI and light amount correction data D are read out from the display memo +117 and the light amount correction memory 63, respectively.
Addition and subtraction circuit 651 that adds and subtracts 2, this addition and subtraction circuit 65
The OR circuit 652 calculates the logical sum of the output of 1 and the carry signal C, and the carry signal B of the addition/subtraction circuit 652
The AND circuit 653 calculates the logical product of the inverted value and the output of the OR circuit 652.
上記の如く構成された映像表示装置の作用を、第１図に
比べて新たに付加した要素を中心にして以下に説明する
。The operation of the video display device configured as described above will be explained below, focusing on newly added elements compared to FIG. 1.
先ず、操作部６１を操作したとき、切替スイッチ６４が
破線で示した側に切替えられ、また、図示しない系統を
介して、アンテナ１１の代わりに例えば掃引発振器が受
信部１２に接続されるように講じられており、タイミン
グ信号発生部１５より出力される書き込み読み出し信号
Ｒ／Ｗ、アドレス信号ＲＡＤＤ 、 ＣＡＤＤが光量補
正メモリ６３に加えられる。First, when the operating section 61 is operated, the changeover switch 64 is switched to the side shown by the broken line, and a sweep oscillator, for example, is connected to the receiving section 12 instead of the antenna 11 via a system not shown. The write/read signal R/W, address signals RADD, and CADD output from the timing signal generator 15 are added to the light amount correction memory 63.
々お、このとき表示制御回路側が切離されて、表示器４
０の発光素子４１には電流検出部５０ヲ介して電力が供
給されるようになっている。At this time, the display control circuit side is disconnected and the display 4
Electric power is supplied to the light emitting element 41 of No. 0 through the current detection section 50.
ここで、電流検出部間の電源端子５３ 、５４間に一定
電圧を供給する一方、点灯制御用の端子５５より順次ト
ランゾスタ５２のベース電流を供給すると、発光素子４
１が順次点灯して電流検出回路５１から電流検出信号Ｓ
２が選出される。Here, when a constant voltage is supplied between the power supply terminals 53 and 54 between the current detection parts, and the base current of the transistor 52 is sequentially supplied from the lighting control terminal 55, the light emitting element 4
1 lights up sequentially and the current detection signal S is output from the current detection circuit 51.
2 is selected.
このようにして発光素子４１に流れる電流は必ずしも光
量と比例するとは限らないが光量の目安とすることがで
きる。Although the current flowing through the light emitting element 41 in this manner is not necessarily proportional to the amount of light, it can be used as a guide for the amount of light.
次に、電流検出信号Ｓ２が入力部５０ａ’ｉ介してデー
タ処理部６２に加えられると、データ処理部６２は電流
値の平均値を求める一方、この平均値と各発光素子４１
の電流値との偏差分を階調データの階差に換算して出力
する。Next, when the current detection signal S2 is applied to the data processing section 62 via the input section 50a'i, the data processing section 62 calculates the average value of the current value, and also combines this average value with each light emitting element 41.
The deviation from the current value is converted into a difference in gradation data and output.
このとき、光量補正メモリ６３には上述した如く、書き
込み読出し信号Ｒ／’Ｗとアドレス信号、ＲＡＤＤ 。At this time, the light amount correction memory 63 receives the write/read signal R/'W and the address signal RADD as described above.
Ｃ！ＡＤＤが加えられているため、階調データの階差で
表わされた値が指定された番地に書き適寸れる。C! Since ADD is added, the value expressed by the difference in the gradation data is written to the specified address and can be sized appropriately.
なお、発光電流の平均値に対してより大きな電流値全示
したときに負値として、反対に平均値に対してより小さ
な電流値を示したとき正値として書き込まれる。Note that when all current values larger than the average value of the light emitting current are shown, a negative value is written, and conversely, when a current value smaller than the average value is shown, a positive value is written.
続いて操作部６１ｆＫ：？７１期状態にリセットすると
、切替スイッチ６４は実線で示した側に切替えられ、同
時に図示しない掃引発振器の切離し、ならびに、表示制
御回路側の接続が行なわれる。これによって、第１図を
用いて説明したと同様に、アンテナ１１で受信された映
像信号の一画面分の階調データが表示メモリ１７に書き
込まれる。Next, the operation section 61fK:? When resetting to the 71st state, the selector switch 64 is switched to the side shown by the solid line, and at the same time, the sweep oscillator (not shown) is disconnected and the display control circuit side is connected. As a result, gradation data for one screen of the video signal received by the antenna 11 is written into the display memory 17, as explained using FIG.
この状態で表示メモリ１７および光量補正メモリ６３の
データ読み出しを行うと、両データが累算器６５によっ
て加減算されて表示制御回路かに加えられる。When data is read from the display memory 17 and the light amount correction memory 63 in this state, both data are added and subtracted by the accumulator 65 and added to the display control circuit.
ここで、階調データＤ１が表示メモリ１７から階調デー
タが読み出されると、これに同期して光量補正メモリ５
１から光鼠補正データＤ２が読み出される。加減算回路
５２１は光量補正データＤ２が負値のときは１）１−Ｄ
２の演算をイテい、Ｄ２が正値のときはＤｉ−１−Ｄ２
の演算を行う。またこれらの演算の結果、桁上がりが生
じたとき、すなわち、ＤＩ＋Ｄ２ の演算のとき桁−ｈ
ｂ信信号音Ｏ１１回路５２２に加え、出力の全ピッ）ｋ
ゝゝ１“にする。反対に桁下りが生じたとき、すなわち
、Ｄｌ−Ｄ２のとき桁下り信号Ｂをインヒビット信号と
してＡＮＤ回路５２３に加え、出力の全ビットをゝゝ０
”にするようにする。Here, when the gradation data D1 is read out from the display memory 17, the light amount correction memory 55 synchronizes with this.
Optical mouse correction data D2 is read from 1. The addition/subtraction circuit 521 performs 1) 1-D when the light amount correction data D2 is a negative value.
Iterate the operation of 2, and if D2 is a positive value, Di-1-D2
Perform the calculation. Also, when a carry occurs as a result of these operations, that is, when calculating DI+D2, the digit -h
In addition to the signal tone O11 circuit 522, all the output pitches) k
On the other hand, when a downshift occurs, that is, when Dl-D2, the downshift signal B is applied as an inhibit signal to the AND circuit 523, and all bits of the output are set to "0".
”
かくして、同一の電力に対して暗すぎる発光素子はより
長く点灯されて明るくなり、同一の電力に対して明るす
ぎる発光素子は点灯時間が制限されて暗くなることから
、一定の階調データに対して光量を均一化することがで
きる。In this way, a light-emitting element that is too dark for the same power will be lit for a longer time and become brighter, and a light-emitting element that is too bright for the same power will have a limited lighting time and become darker, so that The amount of light can be made uniform.
なお、上記実施例ではテレビジヨン）反送用の電波を受
信する表示装置について説明したが、映像の受信源はＶ
ＴＲでもよく、要は映像信号としてデイノタル化さね、
た階調データを出力する信号発生手段を具えるものに全
て不発明（ｉｌ−適用することができる。In the above embodiment, a display device that receives radio waves for retransmission (television) has been described, but the video reception source is V.
It could be TR, but the point is to convert it into a digital signal as a video signal.
The present invention can be applied to any device equipped with a signal generating means for outputting gray scale data.
以上の説明によって明らかな如く、本発明の映像表示装
置によれば、ｙＣＣ副調整回路設けることなく、値の等
しい階調データに対して映像画面を構成する多数の発光
素子の光量全均一化（７得、これによつ−Ｃ階Ａｆ−夕
に対応した忠実な画像を映出することができる。As is clear from the above description, according to the video display device of the present invention, the total light intensity of a large number of light emitting elements constituting a video screen can be made uniform for gradation data of equal value without providing a yCC sub-adjustment circuit 7. As a result, a faithful image corresponding to the -C floor Af-evening can be projected.
剪だ、表示器全構成する発光素子の新しいうちは規定の
電力を供給しなくとも必要な光量が得られることが多い
。この点、これら新しい発光素子（一部でも全体でもよ
い）に対して光量補正メモリの補正値を大きく（または
小さく）シて、発光素子に供給される電力を低く押さえ
るようにすればその寿命を大幅に延ばし得る等の優れた
効果が得られる。However, when the light-emitting elements that make up the entire display are new, it is often possible to obtain the necessary amount of light without having to supply the specified power. In this regard, if you increase (or decrease) the correction value of the light intensity correction memory for these new light emitting elements (part or all) to keep the power supplied to the light emitting elements low, you can extend their lifespan. Excellent effects such as being able to extend the period considerably can be obtained.
第１図は従来の映像表示装置の構成を示すブロック図、
第２図は本発明に係る映像表示装置の一実ＪＪ出例の構
成を示すブロック図、第３図および第４図は同実施例の
主要な要素の詳細な構成を示す回路図である。
１３・映像（Ｍ号発生装置、１７・・・表示メモリ、２
０・・表示１Ｄｌｌ ｊＴｌ ｌｐｌ ｉｆ、、３１Ｊ
−％ ａＪ ｌｉ’ｆｉ 路、４０− ｉｉ＜ 示＜
３．４１・発光素子、５０・）し、流検出ｔ′１１≦、
６２′１″−タ処ｊル部、６３・光−歇袖正メモリ、６
５・累Ｎ器。
出願人代理人 猪 股 清
手続補正書
昭和閏年５月１１日
特許庁長官 若 杉 和 夫 殿
１、事件の表示
昭和関年特許願第５５６３９号
２、発明の名称
映像表示装置
３、補正をする者
事件との関係特許出願人
（３７５）東芝電材株式会社
７、補正の対象
□ 明細書および図面
８、補正の内容
明細書および図面の浄書（Ｖ３容に変更なし）４９６−FIG. 1 is a block diagram showing the configuration of a conventional video display device.
FIG. 2 is a block diagram showing the configuration of an example of a video display device according to the present invention, and FIGS. 3 and 4 are circuit diagrams showing the detailed configuration of the main elements of the same embodiment. 13・Video (M number generator, 17...display memory, 2
0...Display 1Dll jTl lpl if,, 31J
-% aJ li'fi path, 40-ii<show<
3.41・Light emitting element, 50・) and current detection t′11≦,
62'1''-Data processing section, 63.Light - Intermittent sleeve main memory, 6
5. Cumulative N equipment. Applicant's agent Inomata Kiyoshi Procedural amendment May 11, Showa leap year Director of the Japan Patent Office Kazuo Wakasugi 1. Indication of the case Showa 1999 Patent Application No. 55639 2. Name of the invention Video display device 3. Make amendments. Patent applicant (375) Toshiba Electric Materials Corporation 7, Subject of amendment □ Specification and drawings 8, Contents of amendment Description and engraving of drawings (no change in V3 content) 496-
Claims (1)
、映像信号としてディノタル化された階調データを出力
する信号発生手段と、１１ｆ記表示器の少なくとも一画
面に対応する階調データを記憶させる第１のメモリと、
前記映像画面を複数に分けたブロック毎に設けられ、こ
のブロック内の１１ｓ記発光素子を順次点灯させる定電
圧を供給するとともに、この発光素子の電流を検出する
電流検出部と、この電流検出部の出力信号に基づき、ブ
ロック内の前記発光素子の平均電流に対する各発光素子
の電流偏差分を階調データの階差に換算して出力する信
号処理手段と、この信号処理手段のデータを記憶させる
第２のメモリと、前記第１のメーモリの階調データを前
記第２のメモリのデータによって補正して出力する演算
回路と、この演算回路より出力される階調データに対応
する時間だけ前記発光素子を点灯させる表示制御回路と
を具備したことを特徴とする映像表示装置ｒ１：。A display device having a video screen formed by arranging a large number of light emitting elements, a signal generating means for outputting gradation data dinotated as a video signal, and gradation data corresponding to at least one screen of the display device 11f. a first memory for storing;
a current detection unit provided in each block in which the video screen is divided into a plurality of blocks, which supplies a constant voltage to sequentially light up the 11s light emitting elements in this block and detects the current of the light emitting elements; a signal processing means for converting the current deviation of each light emitting element with respect to the average current of the light emitting elements in the block into a difference in gradation data based on the output signal of the block, and storing the data of the signal processing means. a second memory; an arithmetic circuit that corrects the gradation data of the first memory using the data of the second memory and outputs the corrected data; Video display device r1: characterized by comprising a display control circuit that lights up elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5563983A JPS59181882A (en) | 1983-03-31 | 1983-03-31 | Video display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5563983A JPS59181882A (en) | 1983-03-31 | 1983-03-31 | Video display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59181882A true JPS59181882A (en) | 1984-10-16 |
Family
ID=13004368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5563983A Pending JPS59181882A (en) | 1983-03-31 | 1983-03-31 | Video display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59181882A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63142392A (en) * | 1986-12-05 | 1988-06-14 | 三菱電機株式会社 | Light emitting diode array head |
| JPH10254410A (en) * | 1997-03-12 | 1998-09-25 | Pioneer Electron Corp | Organic electroluminescent display device, and driving method therefor |
| JP2002304156A (en) * | 2001-01-29 | 2002-10-18 | Semiconductor Energy Lab Co Ltd | Light-emitting device |
| JP2003122305A (en) * | 2001-10-10 | 2003-04-25 | Sony Corp | Organic el display device and its control method |
| JP2003202837A (en) * | 2001-12-28 | 2003-07-18 | Pioneer Electronic Corp | Device and method for driving display panel |
| JP2003202836A (en) * | 2001-12-28 | 2003-07-18 | Pioneer Electronic Corp | Device and method for driving display panel |
| JP2004004673A (en) * | 2002-03-29 | 2004-01-08 | Seiko Epson Corp | Electronic device, driving method for the same, electro-optical device, and electronic apparatus |
| JP2004038210A (en) * | 1997-03-12 | 2004-02-05 | Seiko Epson Corp | Display device and electronic equipment |
| JP2004038209A (en) * | 1997-03-12 | 2004-02-05 | Seiko Epson Corp | Display device and electronic equipment |
| US6806497B2 (en) | 2002-03-29 | 2004-10-19 | Seiko Epson Corporation | Electronic device, method for driving the electronic device, electro-optical device, and electronic equipment |
| JP2006309133A (en) * | 2005-04-28 | 2006-11-09 | Samsung Sdi Co Ltd | Organic light emitting display and method of driving the same |
| JP2006309134A (en) * | 2005-04-28 | 2006-11-09 | Samsung Sdi Co Ltd | Organic light emitting display device and driving method thereof |
| JP3887826B2 (en) * | 1997-03-12 | 2007-02-28 | セイコーエプソン株式会社 | Display device and electronic device |
-
1983
- 1983-03-31 JP JP5563983A patent/JPS59181882A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63142392A (en) * | 1986-12-05 | 1988-06-14 | 三菱電機株式会社 | Light emitting diode array head |
| JP3887826B2 (en) * | 1997-03-12 | 2007-02-28 | セイコーエプソン株式会社 | Display device and electronic device |
| JPH10254410A (en) * | 1997-03-12 | 1998-09-25 | Pioneer Electron Corp | Organic electroluminescent display device, and driving method therefor |
| US7362322B2 (en) | 1997-03-12 | 2008-04-22 | Seiko Epson Corporation | Pixel circuit, display apparatus and electronic apparatus equipped with current driving type light-emitting device |
| JP2004038209A (en) * | 1997-03-12 | 2004-02-05 | Seiko Epson Corp | Display device and electronic equipment |
| JP2004038210A (en) * | 1997-03-12 | 2004-02-05 | Seiko Epson Corp | Display device and electronic equipment |
| JP2002304156A (en) * | 2001-01-29 | 2002-10-18 | Semiconductor Energy Lab Co Ltd | Light-emitting device |
| JP2003122305A (en) * | 2001-10-10 | 2003-04-25 | Sony Corp | Organic el display device and its control method |
| JP2003202837A (en) * | 2001-12-28 | 2003-07-18 | Pioneer Electronic Corp | Device and method for driving display panel |
| JP2003202836A (en) * | 2001-12-28 | 2003-07-18 | Pioneer Electronic Corp | Device and method for driving display panel |
| US6806497B2 (en) | 2002-03-29 | 2004-10-19 | Seiko Epson Corporation | Electronic device, method for driving the electronic device, electro-optical device, and electronic equipment |
| JP2004004673A (en) * | 2002-03-29 | 2004-01-08 | Seiko Epson Corp | Electronic device, driving method for the same, electro-optical device, and electronic apparatus |
| JP2006309134A (en) * | 2005-04-28 | 2006-11-09 | Samsung Sdi Co Ltd | Organic light emitting display device and driving method thereof |
| JP2006309133A (en) * | 2005-04-28 | 2006-11-09 | Samsung Sdi Co Ltd | Organic light emitting display and method of driving the same |
| US7768486B2 (en) | 2005-04-28 | 2010-08-03 | Samsung Mobile Display Co., Ltd. | Organic light emitting display and method of driving the same |
| US8040363B2 (en) | 2005-04-28 | 2011-10-18 | Samsung Mobile Display Co., Ltd. | Organic light emitting display with user brightness control and method of driving the same |
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