JPS5917620U - power booster circuit - Google Patents
power booster circuitInfo
- Publication number
- JPS5917620U JPS5917620U JP11207182U JP11207182U JPS5917620U JP S5917620 U JPS5917620 U JP S5917620U JP 11207182 U JP11207182 U JP 11207182U JP 11207182 U JP11207182 U JP 11207182U JP S5917620 U JPS5917620 U JP S5917620U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- amplification circuit
- output
- power booster
- amplifies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のパワーブースタ回路の一例を示す回路図
、第2図はこの考案によるパワーブースタ回路の一実施
例を示す回路図、第3図は第2図の等価回路図である。
3′・・・バッファ増幅回廊、4・・・電力増幅回路、
5・・・フィードバック回路、R1’ * R2’ H
R4−R10・・・抵抗、C・・・コンデンサ、Tr1
〜Tr4・・・トランジスタ、C・・・コンデンサ。FIG. 1 is a circuit diagram showing an example of a conventional power booster circuit, FIG. 2 is a circuit diagram showing an embodiment of the power booster circuit according to this invention, and FIG. 3 is an equivalent circuit diagram of FIG. 2. 3'...Buffer amplification corridor, 4...Power amplification circuit,
5...Feedback circuit, R1'*R2'H
R4-R10...Resistor, C...Capacitor, Tr1
~Tr4...transistor, C...capacitor.
Claims (1)
増幅回路の出力を電圧増幅することにより入出力の位相
が互いに逆の出力を発生する電圧増幅回路と、この電圧
増幅回路の出力を前記バッファ増幅回路に帰還するフィ
ードバック回路とを備えたパワーブースタ回路に於いて
、前記バッファ増幅回路に複数入力信号を加算する加算
機能を附加したことを特徴とするパワーブースタ回路。a buffer amplification circuit that amplifies an input signal; a voltage amplification circuit that amplifies the output of this buffer amplification circuit to generate an output whose input and output phases are opposite to each other; and a voltage amplification circuit that amplifies the output of this voltage amplification circuit; 1. A power booster circuit comprising a feedback circuit that feeds back signals to the buffer amplifier circuit, wherein an addition function for adding a plurality of input signals is added to the buffer amplifier circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11207182U JPS5917620U (en) | 1982-07-22 | 1982-07-22 | power booster circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11207182U JPS5917620U (en) | 1982-07-22 | 1982-07-22 | power booster circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5917620U true JPS5917620U (en) | 1984-02-02 |
Family
ID=30259942
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11207182U Pending JPS5917620U (en) | 1982-07-22 | 1982-07-22 | power booster circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5917620U (en) |
-
1982
- 1982-07-22 JP JP11207182U patent/JPS5917620U/en active Pending
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