JPS59174058A - Dc voltage control circuit - Google Patents

Dc voltage control circuit

Info

Publication number
JPS59174058A
JPS59174058A JP58048249A JP4824983A JPS59174058A JP S59174058 A JPS59174058 A JP S59174058A JP 58048249 A JP58048249 A JP 58048249A JP 4824983 A JP4824983 A JP 4824983A JP S59174058 A JPS59174058 A JP S59174058A
Authority
JP
Japan
Prior art keywords
circuit
signal
error
control signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58048249A
Other languages
Japanese (ja)
Other versions
JPH0262983B2 (en
Inventor
Yasutsune Yoshida
泰玄 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58048249A priority Critical patent/JPS59174058A/en
Priority to US06/591,752 priority patent/US4544894A/en
Priority to CA000450157A priority patent/CA1208708A/en
Priority to DE8484103181T priority patent/DE3468800D1/en
Priority to AU25994/84A priority patent/AU557008B2/en
Priority to EP84103181A priority patent/EP0120474B1/en
Publication of JPS59174058A publication Critical patent/JPS59174058A/en
Publication of JPH0262983B2 publication Critical patent/JPH0262983B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/02Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H04L27/06Demodulator circuits; Receiver circuits
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/067Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing soft decisions, i.e. decisions together with an estimate of reliability

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Manipulation Of Pulses (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To prevent a reproduction error due to the abnormal pull-in by giving the control information in a single direction to the error information given from each error regions having the same positive or negative value compared with the central identification value, and producing a control signal. CONSTITUTION:This DC voltage control circuits is provided with a subtractor 3, an A/D converter 4 and a control signal generator 9. The generator 9 contains an AND circuit 6 which obtains an AND of outputs X1-X3 of the converter 4, an NOR circuit 7 which obtains an NOR of X1-X3, an FF8 which uses the output S1 of the circuit 6 as a set input and the output R1 of the circuit 7 as a reset input respectively, and a control signal generating circuit 5. Then the binary signals Q2 of ''1'' and ''0'' are produced to the output of the FF8 in relation to the outputs S1 and R1 of circuits 6 and 7 and each error region. These binary signals are processed by the circuit 5, and a DC output 101 is generated. In such a way, the correct control is secured, so that no abnormal pull-in phenomenon occurs.

Description

【発明の詳細な説明】 本発明は直流電圧制御回路、特に直交振幅変調波の復調
装置等で位相検波後の復調信号を識別再生する回路に用
いられ、ドリフト4によるinn酸成分変動を補償する
直流電圧制御p回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention is used in a DC voltage control circuit, particularly in a circuit that identifies and reproduces a demodulated signal after phase detection in a demodulating device for quadrature amplitude modulated waves, etc., and compensates for fluctuations in inn acid components due to drift 4. This invention relates to a DC voltage control p-circuit.

近年、マイクロ波などの搬送波を用いてディジタル信号
を伝送する場合、161直直交振幅変調方式(16値Q
AMと略記する)なとの多値直交振幅変調方式が、周波
数帯域を有効に使用できる高能率変調方式として注目さ
れその開発が行われている。このような高能率伝送方式
を実現するりf−で、各装置の回路各部で発生する不完
全性は極力除去する必要があシ、復調装置の識別再生回
路入力に含まれる直流ドリフトもその1つである。
In recent years, when transmitting digital signals using carrier waves such as microwaves, the 161 orthogonal amplitude modulation method (16-value Q
The multilevel orthogonal amplitude modulation method (abbreviated as AM) has been attracting attention as a highly efficient modulation method that can effectively use the frequency band, and is being developed. In order to realize such a high-efficiency transmission system, it is necessary to eliminate imperfections that occur in each part of the circuit of each device as much as possible, and DC drift included in the input of the identification and regeneration circuit of the demodulator is one of them. It is one.

上述の直流ドリフト成分を補償する効果的で量産にも適
した回路が、特願昭56−200047号明細書に提案
されている。この回路は、位相検波された多値復調信号
の識別再生を行うアナログ・ディジタル変換器(A/D
変換器と略記)の誤差出力で、入力側に重畳される直流
電圧を制御するものであって、連続運用時には良好に動
作するが、後述するように一度入力信号が切れた後、再
び入力が回復した場合、初期状態によっては異常引込み
を起こして誤った直流値に制御される恐れがあり、正常
動作に復帰しないという欠点がある。
A circuit that is effective and suitable for mass production for compensating the above-mentioned DC drift component is proposed in Japanese Patent Application No. 56-200047. This circuit consists of an analog-to-digital converter (A/D
The DC voltage superimposed on the input side is controlled by the error output of the converter (abbreviated as converter), and it works well during continuous operation, but as will be explained later, once the input signal is cut off, the input signal may be turned off again. When it recovers, depending on the initial state, there is a risk that abnormal draw-in may occur and the DC value will be controlled to an incorrect value, and there is a drawback that normal operation will not be restored.

本発明の目的は、上述の欠点を除去し、いかなる初期状
態でも異常引込みを起こさない旧派電圧制御回路を提供
することである。
SUMMARY OF THE INVENTION The object of the present invention is to eliminate the above-mentioned drawbacks and to provide an old-fashioned voltage control circuit that does not cause abnormal pull-in in any initial state.

本発明の1自流電圧制御回路は、入力信号に重畳される
直流電圧が制御信号により制御できる直流分制御器と、
信号を複数の信号領域に区分する中央識別値を含む奇数
個の信号識別値と前記各信号領域をそれづ−れ2つの誤
差領域に分割する偶数個の誤差識別IL’−で前記直流
分制御器の出力を多値識別して再生出力信号と誤差信号
とを出力するA/D変換器と、このA/D変換器の出力
から前記制御信号を発生する制御信号発生器とを備えた
直流電圧制御回路において、前記制御信号発生器が、少
なくとも前記中央識別値に接する正側および負側の2つ
を除く前記各誤差領域から得られる誤差情報のみを使用
し、前記中央識別値より正または負の同一側にある前記
各誤差領域からの誤差情報はそれぞれ同=方向の制御情
報を与えるようにして前記制御信号を発生する制御信号
発生手段を含むことによって構成される。
1. A direct current voltage control circuit of the present invention includes a DC component controller in which a DC voltage superimposed on an input signal can be controlled by a control signal;
The DC component control is performed using an odd number of signal discrimination values including a central discrimination value that divides the signal into a plurality of signal regions and an even number of error discrimination IL'- that divides each of the signal regions into two error regions. A direct current converter comprising an A/D converter that performs multi-value discrimination on the output of the device and outputs a reproduced output signal and an error signal, and a control signal generator that generates the control signal from the output of the A/D converter. In the voltage control circuit, the control signal generator uses only error information obtained from each of the error areas excluding at least two on the positive side and the negative side that are in contact with the central discrimination value, and The error information from each of the error areas on the same negative side is configured to include control signal generating means for generating the control signal so as to provide control information in the same direction.

次に図面を参照して本発明の詳細な説明する。Next, the present invention will be described in detail with reference to the drawings.

第1図は特願昭56−200’、047号明細書記載の
復調装置のブロック図であり、自動利イη制御機能を有
する中間周波増幅器1と、その出力の16値QAM波を
復調し2列の4値ディジタル信号100を出力する復調
器2と、その出力にそれぞれ直流電圧を重畳する減算器
3と、減算器3の出力を8値識別して2ビツトの再生出
力信号X、、X2及び1ビツトの誤差信号X3 を出力
す;5 A / D変換器4と、誤差信号X3 から低
域フィルタにより高周波成分を抑圧して制御用の直流電
圧101を発生する制御信号発生回路5とから成ってい
る。
FIG. 1 is a block diagram of a demodulator described in the specification of Japanese Patent Application No. 56-200', No. 047, which includes an intermediate frequency amplifier 1 having an automatic gain η control function, and a demodulator that demodulates the 16-level QAM wave output from the intermediate frequency amplifier 1. A demodulator 2 outputs two columns of 4-value digital signals 100, a subtracter 3 superimposes a DC voltage on each output, and the output of the subtracter 3 is identified in 8 values to produce a 2-bit reproduced output signal X, . 5 A/D converter 4 which outputs X2 and a 1-bit error signal X3; and a control signal generation circuit 5 which suppresses high frequency components from the error signal X3 using a low-pass filter to generate a control DC voltage 101. It consists of

このブロック図において、減算器3、A/D変換器4及
び制御信号発生回路3は、A/l)変換器4が最適動作
条件で信号識別が行えるよう復調信号に含寸れる直流分
を制御する市原電圧制御回路を構成している。第2図は
上述の面流′亀圧制御回路の動作を説明するためのA/
D変換器4の識別領域図であり、A/D変換器40入力
電圧は3つの信号識別値V、=Q 、 ■=±2dによ
って4つの信号領域I〜■に分割され、更に各信号領域
はV−±d、v=±3dの誤差識別値によりそれぞれ2
つの誤差領域■ とI  、n  とir、+n  と
■、■と■−に分割されている。A/D変換器4はその
入力信号102が第2図のどの領域にあるかにより、図
に示されている2値化号X1.X2.X3を送出するよ
う構1.+tされている。第1図のA/l)変換器4が
最適動作状態にあるときは、入力信号10204つの信
号レベルは各信号領域の甲心すなわち各誤差識別値と一
致しA1−A4で示される。人力の信号レベルが直流ド
リフトによってこの値から(−1−)方向にΔV変化し
てA 、/〜A4′  となると、誤差信号X3 はど
の信号レベルに対1てもすべて1″となって制御信号発
生回路5の1酊流出力101が増加する。従って、入力
(i号100に直流電圧が重畳された減算器3の出力1
02の直流分は(−)方向に変化して、A 、/〜N4
′は矢印α方向に移動し  −最適動作状態に戻される
。逆に人力(8号レベルが直流ドリフトのため破線で示
すように(→方向に変化すると、誤差信号X3 はすべ
て“0″となって制御信号発生回路5の直流出力101
が減少し、減算器3の出力信号102に含まれる]白流
分は(−1−1方向に制御される。すなわち、復調器や
ベース・くンド増幅器の旧派ドリフト等により入力信号
100の直流分が変動しても、A/D変換器4の入力1
02は常に最適の動作状態A1〜A4  となるように
制御される。
In this block diagram, a subtracter 3, an A/D converter 4, and a control signal generation circuit 3 control the DC component included in the demodulated signal so that the A/L converter 4 can perform signal identification under optimal operating conditions. It constitutes an Ichihara voltage control circuit. FIG.
It is a discrimination area diagram of the D converter 4, and the input voltage of the A/D converter 40 is divided into four signal areas I to ■ by three signal discrimination values V, =Q, ■=±2d, and each signal area is further divided into four signal areas I to ■. are 2 depending on the error identification values of V-±d and v=±3d, respectively.
The error areas are divided into three error areas: ■ and I, n and ir, +n and ■, and ■ and ■-. The A/D converter 4 converts the binary signals X1 to X1, . X2. Structure to send X3 1. +t has been applied. When the A/l) converter 4 of FIG. 1 is in optimal operating conditions, the signal levels of the input signals 10204 coincide with the core of each signal region, or each error discrimination value, and are indicated by A1-A4. When the human input signal level changes by ΔV from this value in the (-1-) direction due to DC drift and becomes A,/~A4', the error signal X3 becomes 1'' for any signal level and is controlled. The 1 intoxication output 101 of the signal generation circuit 5 increases. Therefore, the output 1 of the subtracter 3 in which the DC voltage is superimposed on the input (i 100)
The DC component of 02 changes in the (-) direction and becomes A,/~N4
' is moved in the direction of arrow α and returned to the optimum operating state. On the other hand, when the human input (No. 8 level changes in the direction of → as shown by the broken line due to DC drift), the error signal X3 becomes all “0” and the DC output 101 of the control signal generation circuit 5
is reduced and included in the output signal 102 of the subtractor 3] The white current component is controlled in the -1-1 direction.In other words, the DC of the input signal 100 is Even if the minute changes, the input 1 of the A/D converter 4
02 is always controlled to be in the optimum operating state A1 to A4.

しかしながら、上述の従来の方法では、人力信号が一度
断となって再び印加された場合、初期状態の直流分偏移
ΔV′が大きく第21ン」Bよ〜B4のごとく識別値間
隔dを越えてΔV’)dとなると、13□に対する誤差
信号X3 は“1”となるが、B2〜B4  に対する
誤差信号X3 はすべて“0″となって、10′出力の
方が多くなるので減算器3の出力102の直流分は(→
方向に制御され、B0〜B4は矢印γで示す正常な制御
方向と反対の矢印βの方向に移動しB2→A1.B3→
A2.B、→A3となる異常引込み現象が発生する。逆
に直流分偏移−ΔV′が負側に太きくずれ−dを越えB
 、/〜B4′となった場合には、誤差信号X3 は“
1′出力が多くなりB1′〜B 、/  を正常な制御
方向(矢印γ′)と反対の矢印β′υ・方向に制御して
異常引込み現象を起こし、信号が正しく再生されず誤り
を生ずることとなる。
However, in the conventional method described above, when the human input signal is once interrupted and then applied again, the DC component deviation ΔV' in the initial state is large and exceeds the discrimination value interval d, as shown in the 21st B~B4. ΔV')d, the error signal X3 for 13□ becomes "1", but the error signals X3 for B2 to B4 all become "0", and since the 10' output is larger, The DC component of the output 102 is (→
B0 to B4 move in the direction of arrow β, which is opposite to the normal control direction shown by arrow γ, and B2→A1. B3→
A2. An abnormal pull-in phenomenon occurs in which B, → A3. On the other hand, when the DC component deviation -ΔV' becomes larger on the negative side and exceeds -d, B
, /~B4', the error signal X3 becomes "
1' output increases and B1' to B, / are controlled in the arrow β'υ direction opposite to the normal control direction (arrow γ'), causing an abnormal pull-in phenomenon, causing the signal to not be reproduced correctly and causing an error. It happens.

上述の異常引込みを防止する第1の方法は、第2図で矢
印β、β′で示される誤った方向への制御情報を発生す
る恐れのある誤差領域1−、II“。
A first method for preventing the above-mentioned abnormal pull-in is to avoid error areas 1-, II'' that may generate control information in the wrong direction, as indicated by arrows β and β' in FIG.

n  、III  、ill  、IV  からの誤差
情報を使用せず、矢印γ、γ で示される正しい方向へ
の制御情報を出力する誤差領域■ 及び■−からの出力
のみで制御信号を発生させることである。第3図はこの
方法による本発明の第1の実施例のフ゛ロック図であり
、第1図と同じ減算器3、A/D変換器4と宙制御信号
発生器9とから構成されている。制御信号発生器9はA
/D変換器4の出力x、、x2.X3 の論理積を求め
るAND回路6と、X11 X2 + Xs の否定論
理和を求めるNOR回路7と、AND回路60出力S1
  をセット入力、NOR回路7の出力比、をリセット
入力とするクリップフロップ8と第1図と同じ制御信号
発生回路5とから構成され。
By not using error information from n, III, ill, and IV, and generating control signals only from the outputs from error regions ■ and ■-, which output control information in the correct direction indicated by arrows γ and γ. be. FIG. 3 is a block diagram of a first embodiment of the present invention according to this method, which is composed of the same subtracter 3, A/D converter 4, and space control signal generator 9 as in FIG. The control signal generator 9 is A
/D converter 4 output x, , x2 . An AND circuit 6 for calculating the logical product of X3, a NOR circuit 7 for calculating the negative logical sum of X11 X2 + Xs, and an AND circuit 60 output S1
It consists of a clip-flop 8 which has a set input, the output ratio of the NOR circuit 7, and a reset input, and the same control signal generation circuit 5 as shown in FIG.

でいる。AND回路6及びNOR回路7の出力S1及び
R8と第2図の各誤差領域との関係は第1表とナリ、■
十 心いベハらf>弯 他力“17ヒ■−外戚からのR
1出力“1”とを用いてフリツフ′フロップ8の出力に
“1”、“0″の2値化号Q1 を発生し、これを制御
信号発生回路5で第1図と同様に処理して直流出力10
1を発生している。この構成によれば第2図のB1〜B
4及びB 、/〜B4′の場合でもr及びγ′で示す正
しい制御が行われて異常引込みを起こす恐れがない。
I'm here. The relationship between the outputs S1 and R8 of the AND circuit 6 and NOR circuit 7 and each error region in FIG. 2 is as shown in Table 1.
10 Heart Behara f>弯 Tāriki “17 Hi■ – R from maternal relatives
1 output "1" is used to generate a binary signal Q1 of "1" and "0" at the output of the flip-flop 8, and this is processed by the control signal generation circuit 5 in the same manner as shown in FIG. DC output 10
1 is occurring. According to this configuration, B1 to B in FIG.
Even in the case of 4 and B, / to B4', the correct control shown by r and γ' is performed and there is no risk of abnormal pull-in.

第4図は本発明の第2の実施例のブロック図で減算器3
、A/D変換器4及び制御信号発生器9aから構成され
、制御信号発生器9aはOR回路10゜AND回路11
と12.NAND回路13.NOT回路14.クリップ
フロップ8及び制御信号発生回路5で構成されている。
FIG. 4 is a block diagram of a second embodiment of the present invention.
, an A/D converter 4, and a control signal generator 9a, and the control signal generator 9a includes an OR circuit 10 and an AND circuit 11.
and 12. NAND circuit 13. NOT circuit 14. It is composed of a clip-flop 8 and a control signal generation circuit 5.

この第2の実施例の回路は第2図の誤差領域のうち■ 
と■ とからの誤差情報を使用せず、残りの6つの誤差
領域からの誤差情報のみによって制御信号を発生するよ
う構成した回路であって、フリソゾフロノ78のセット
人力S2 及びリセット人力R2と各誤差領域との関係
は第2表となり、 第2表 S2 の“1”出力と1(2の“1”出力とから制御信
号を発生する。A/D変換器40入力信号102が最適
状態からずれて縞2図のA 、/〜A、/又はB1〜B
4 のいずれの状態になった場合でも、4値の各信号レ
ベルの発生確率は等しく且つその発生の順序は無作為と
考えられるので、S2 が“1″となる確率とR2が“
1′となる確率は2:1となる。
The circuit of this second embodiment is
This circuit is configured to generate a control signal only using error information from the remaining six error areas without using the error information from The relationship with the area is shown in Table 2, and a control signal is generated from the "1" output of S2 in Table 2 and the "1" output of 1 (2). A, /~A,/or B1~B in the stripe diagram 2
4, the probability of occurrence of each of the four signal levels is equal and the order of occurrence is considered to be random, so the probability that S2 becomes "1" and the probability that R2 becomes "
The probability of becoming 1' is 2:1.

従って、フリップフロップ8の出力Q2 が“1″とな
、る時間が“0″となる時間よシ多くなり、入力信号1
02は矢印α、γで示す方向に副側lすれる。人力信号
102が逆にB1′〜B 4/  となった場合も同様
にして矢印γ′で示す正常な方向に制御され、常に最適
動作状態に収れんして異常引込み現象は発生しない。
Therefore, the time when the output Q2 of the flip-flop 8 is "1" is longer than the time when it is "0", and the input signal 1
02 is subsided in the direction indicated by arrows α and γ. Conversely, when the human power signal 102 becomes B1' to B4/, it is similarly controlled in the normal direction indicated by the arrow γ', and the optimum operating state is always converged and no abnormal pull-in phenomenon occurs.

第5図は本発明の第3の実施例のブロック図で減算器3
 、A/D変換器4及び制御信号発生器9bから成り、
制御信号発生器9bはAND回路15゜NAND回路1
6.クリップフロップ8及び制御信号発生回路5とを備
え、第2図の誤差領域I。
FIG. 5 is a block diagram of a third embodiment of the present invention.
, an A/D converter 4 and a control signal generator 9b,
The control signal generator 9b is an AND circuit 15°NAND circuit 1
6. The error region I in FIG. 2 includes a clip-flop 8 and a control signal generation circuit 5.

■ 、■ 及び■−の誤差情報を用いて制御信号を発生
するよう構成されている。フリップ70ソゲ8のセット
人力S3 及びリセット入力R3と各誤差領域との関係
は第3表の通りであって、s3 のL”  h赴ゲfi
+ 、 // t nバカy、R3の■−ち・よぴ■〜
の“1”出力とから制御信号を発生する。
It is configured to generate a control signal using the error information of ■, ■, and ■-. The relationship between the set manual input S3 and reset input R3 of the flip 70 and the reset input R3 and each error area is as shown in Table 3.
+ , // t n baka y, R3's■-Chiyopi■~
A control signal is generated from the “1” output of

この回路では人力信号102が第2図のB□〜B4及び
B1′〜B 4/  の場合、s3 が“1”となる確
率2几3が“1″となる確率が等しくζ【り有効な制御
信号を発生しなくなるが、その他の場合にはすべて最適
動作状態に向かう方向の制御信号を発生するので、異常
引込み現象を起こすことはなく、多少時間はη弓弓っが
最適動作状態に収れんす・、。
In this circuit, when the human input signal 102 is B□ to B4 and B1' to B 4/ in FIG. Although the control signal is no longer generated, in all other cases, control signals are generated in the direction toward the optimal operating state, so no abnormal pull-in phenomenon occurs, and it takes some time for the η bow to converge to the optimal operating state. vinegar·,.

第61スは本発明の卯4のT施しリのブロック図てあり
、減算器3.A/L)変換器4及び制御1δ号発生器9
cから成り、制御i11信号発生器9cは制御信号発生
回路50人力を切替回路17によって、第1図の従来例
と同じ誤差出力x3  と第3図の実施例と同一のフリ
ップフロップ出力Q1  とに切替えるよう構成されて
いる。切替制御回路18はQlの正常および反転出力を
比較識別して、Ql が連続して“1″又は“0″のと
きは切替回路17が91人力を選択し、“1”および“
O”が交互に発生するとぎは切替回路17がX3 人力
を選択するよ、う構成されている。従って、入力信号1
02が最適値から大きくすれているときは第3図の実施
例と同様に動作して異常引込みを起こすことなくほぼ最
適値附近に制御し、その後はX3  を用いて第1図と
同様すべての誤差領域からの誤差情報を用いて梢度のよ
い制御が行われる。
The 61st stage is a block diagram of the T function of U4 of the present invention, and the subtractor 3. A/L) converter 4 and control 1 δ generator 9
The control i11 signal generator 9c converts the control signal generation circuit 50 into the error output x3, which is the same as the conventional example shown in FIG. 1, and the flip-flop output Q1, which is the same as the embodiment shown in FIG. configured to switch. The switching control circuit 18 compares and identifies the normal and inverted outputs of Ql, and when Ql is continuously "1" or "0", the switching circuit 17 selects 91 manual power and outputs "1" and "0".
The switching circuit 17 is configured to select X3 manual power when "O" occurs alternately. Therefore, the input signal 1
When 02 is far from the optimum value, it operates in the same way as the embodiment shown in Fig. 3, and controls it almost to the optimum value without causing any abnormal pull-in. Accurate control is performed using error information from the error area.

上述の第3図、第4図の実施例ではフリップフロッグ8
のセット及びリセット入力はA/I)変換器4の出力X
□、X2.X3  を論理処理して求めるよう構成され
ているが、これらはA/D変換器4を構成している各識
別器の出力から直接取り出すようにすることもできる。
In the embodiments shown in FIGS. 3 and 4 described above, the flip frog 8
The set and reset input of A/I) is the output of converter 4
□, X2. Although the configuration is such that X3 is obtained through logical processing, it is also possible to directly extract these from the output of each discriminator constituting the A/D converter 4.

又、第3図〜第5図の実施例ではセット入力の“1”情
報とリセット入力の“1”情報を7リツプフロソプで2
値化号に変換して制御電圧101を発生するように構成
されているが、フリップフロッグを用いずにセットリセ
ット入力を正、負の電圧に対応きせてそのま丑積分して
制御電圧を発生させることもでさる。
In addition, in the embodiments shown in FIGS. 3 to 5, the "1" information of the set input and the "1" information of the reset input are processed by 7 lip flops.
Although it is configured to generate a control voltage 101 by converting it into a value signal, the control voltage is generated by integrating the set-reset input corresponding to positive and negative voltages without using a flip-flop. It is also possible to let it happen.

又、第6図の実施例は第1図の従来例と第3図の実施例
とを切替え使用するよう構成したものであるが、第3図
の実施例の代りに第4図廿たは第5図の実施例を使用し
てもよい。更に第3図と第4図の方法を併用する等の方
法も可能である。
The embodiment shown in FIG. 6 is configured to switch between the conventional example shown in FIG. 1 and the embodiment shown in FIG. 3, but the embodiment shown in FIG. The embodiment of FIG. 5 may also be used. Furthermore, it is also possible to use a combination of the methods shown in FIGS. 3 and 4.

上述の説明では入力信号レベルが士d、±3dと正負対
称の4値(3号の場合について述べであるが、正負対称
でなくてもよく、4値以外の多値イハ号についても同様
の構成が可能である。又、入力信号に直流電圧を重畳す
るために減算器を用いているが、減算器の代りに加算器
を用いてもよく、制御信号により直流分が制御できる回
路であれは差支えない。
The above explanation describes the case where the input signal level is 2d, ±3d and 4-value (No. 3) with positive and negative symmetry, but it does not have to be symmetrical, and the same applies to multi-value No. 3 other than 4-value. In addition, although a subtracter is used to superimpose the DC voltage on the input signal, an adder may be used instead of the subtracter, and any circuit that can control the DC component by a control signal may be used. There is no problem.

以上詳細に説明したように、本発明の直流電圧制御回路
によれば、多値信号を識別再生する識別回路において、
信号断が生じても回復時の初期条件にかかわらす異常引
込みを起こすことなく正常動作に復帰することができ、
異常引込みによる再生誤りを防止できる効果がある。
As explained in detail above, according to the DC voltage control circuit of the present invention, in the identification circuit for identifying and reproducing multi-level signals,
Even if a signal disconnection occurs, normal operation can be restored without causing abnormality regardless of the initial conditions at the time of recovery.
This has the effect of preventing playback errors due to abnormal pull-in.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の復調装置のブロック図、第2図はA/D
変換器の識別領域図、第3図は本発明の第1の実施例の
ブロック図、第4図は本発明の第2の実施例のブロック
図、第5図は本発明の第3の実施例のブロック図、第6
図1は本発明の第4の実施例のブロン゛り図である。 1・・・・・・中間周波増幅器、2・・・・・・復調器
、3・・・・・減算器、4・・・・・・A/D変換器、
5・・・・・・制御信号発生回路、6,11,12.1
5・・・・・・AND回路、7・・・・・・NOR回路
、8・・・・・・フリップフロッグ、9゜9a l 9
b ! 9C・・・・・・制御信号発生器、10・・・
・・・0a回路、13.16・・・・・・NAND回路
、14・・・・・・NOT回路、17・・・・・・切替
回路、18・・・・・・切替制御回路。 代理人 弁理士  内 原   音 巣 3 已 鷺・4−ゾ 茅 左 1 を / 回 318
Figure 1 is a block diagram of a conventional demodulator, Figure 2 is an A/D
3 is a block diagram of the first embodiment of the present invention, FIG. 4 is a block diagram of the second embodiment of the present invention, and FIG. 5 is a diagram of the third embodiment of the present invention. Example block diagram, No. 6
FIG. 1 is a brochure diagram of a fourth embodiment of the present invention. 1...Intermediate frequency amplifier, 2...Demodulator, 3...Subtractor, 4...A/D converter,
5... Control signal generation circuit, 6, 11, 12.1
5...AND circuit, 7...NOR circuit, 8...Flip frog, 9°9a l 9
b! 9C... Control signal generator, 10...
...0a circuit, 13.16...NAND circuit, 14...NOT circuit, 17... switching circuit, 18... switching control circuit. Agent Patent Attorney Uchihara Otosu 3 Wasagi・4-Zo Kaya Left 1 / times 318

Claims (1)

【特許請求の範囲】[Claims] 入力信号に重畳される直流電圧が制御信号により制御さ
れる直流分制御器と、信号を複数の信号領域に区分する
中央識別値を含む奇数個の信号識別値と前記各信号領域
をそれぞれ2つの誤差領域に分割する偶数個の誤差識別
値とで前記直流分制御器の出力を多値識別して再生出力
信号と誤差信号とを出力するアナログ・ディンタル変換
器と、このアナログ・ディンタル変換器の出力から+4
i+記制御信号を発生する制御信号発生器とを備えた直
流電圧制御回路ておいて、前記制御信号発生器が少なく
とも前記中央識別値に接する正側および負側の2つを除
く前記各課等領域からイ峙られる誤差情報のみを使用し
、前記中央識別値より正せたは負の同一側にある前記各
誤差領域からの誤差情報はそれぞれ同一方向の制御情報
を与えるようにして前記制御信号を発生する制御信号発
生手段を含むことを特徴とする直流電圧制御回路。
a DC component controller in which a DC voltage superimposed on an input signal is controlled by a control signal; an odd number of signal discrimination values including a central discrimination value that divides the signal into a plurality of signal regions; an analog-to-digital converter that performs multi-value discrimination on the output of the DC component controller using an even number of error discrimination values divided into error regions, and outputs a reproduced output signal and an error signal; +4 from output
a DC voltage control circuit comprising a control signal generator that generates a control signal, wherein the control signal generator is applied to each of the sections except for at least two areas on the positive side and negative side that are in contact with the central identification value. The control signal is generated by using only the error information that can be detected from the central discrimination value, and by using error information from each of the error areas that are on the same positive or negative side of the central identification value, respectively, giving control information in the same direction. 1. A DC voltage control circuit comprising control signal generating means for generating a control signal.
JP58048249A 1983-03-23 1983-03-23 Dc voltage control circuit Granted JPS59174058A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP58048249A JPS59174058A (en) 1983-03-23 1983-03-23 Dc voltage control circuit
US06/591,752 US4544894A (en) 1983-03-23 1984-03-21 DC Voltage control circuits
CA000450157A CA1208708A (en) 1983-03-23 1984-03-21 Dc voltage control circuits
DE8484103181T DE3468800D1 (en) 1983-03-23 1984-03-22 Dc voltage control circuits
AU25994/84A AU557008B2 (en) 1983-03-23 1984-03-22 Demodulation control
EP84103181A EP0120474B1 (en) 1983-03-23 1984-03-22 Dc voltage control circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58048249A JPS59174058A (en) 1983-03-23 1983-03-23 Dc voltage control circuit

Publications (2)

Publication Number Publication Date
JPS59174058A true JPS59174058A (en) 1984-10-02
JPH0262983B2 JPH0262983B2 (en) 1990-12-27

Family

ID=12798160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58048249A Granted JPS59174058A (en) 1983-03-23 1983-03-23 Dc voltage control circuit

Country Status (1)

Country Link
JP (1) JPS59174058A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0486474A2 (en) 1985-06-29 1992-05-20 Nec Corporation Method for adapting a transversal equalizer, without carrier synchronism

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0486474A2 (en) 1985-06-29 1992-05-20 Nec Corporation Method for adapting a transversal equalizer, without carrier synchronism

Also Published As

Publication number Publication date
JPH0262983B2 (en) 1990-12-27

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