JPS59171233A - Automatic lock phase setting circuit - Google Patents
Automatic lock phase setting circuitInfo
- Publication number
- JPS59171233A JPS59171233A JP58046343A JP4634383A JPS59171233A JP S59171233 A JPS59171233 A JP S59171233A JP 58046343 A JP58046343 A JP 58046343A JP 4634383 A JP4634383 A JP 4634383A JP S59171233 A JPS59171233 A JP S59171233A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- output
- phase shifter
- identification
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はディジタル伝送用の受信器の識別再生におい
て再生クロックの位相設定を行なう自動クロック位相設
定回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic clock phase setting circuit for setting the phase of a reproduced clock during identification and reproduction of a receiver for digital transmission.
従来、この独の装置として第３図に示すものがあった。Conventionally, there was a device shown in FIG. 3 as this German-made device.
図において、（４）は受信ベースバンド信号（１）から
再生クロック信号を再生するクロック再生回路、（３）
は再生クロック信号を移相する手動移相器、（２）は手
動８．相器（３）により移相されたクロックを用いてベ
ースバンド信号（１）より受信データ信号（５）を識別
ＦＪ生ずる識別ゼ）生へである。In the figure, (4) is a clock recovery circuit that recovers a recovered clock signal from the received baseband signal (1), and (3)
8. is a manual phase shifter that shifts the phase of the recovered clock signal; (2) is a manual phase shifter; The received data signal (5) is generated from the baseband signal (1) using the clock phase shifted by the phase shifter (3).
次に動作について説明する。受信データ信号（５）は、
たとえは受信ベースバンド信号（」）からＩＩｊ生され
た再生クロック信号Ｃを用いて、識別再生器（２）で受
信ベースバンド信号（１）をシーンプリングすることに
よって得るのが一般的である。Next, the operation will be explained. The received data signal (5) is
For example, it is generally obtained by scene-pulling the received baseband signal (1) in the identification regenerator (2) using the recovered clock signal C generated from the received baseband signal ('').
第２図は、受信ベースバンド信号のアイパターンを示す
が、上記のザンプリングを行う時点は、この図の一点鎖
線で示した時点、υ（ｊち、アイが最も界きく開口して
いる時点にある必侠が：する。。、 。Figure 2 shows the eye pattern of the received baseband signal, and the points at which the above sampling is performed are at the point indicated by the dashed line in this figure, υ A certain chivalrous man: . . .
従来、サンプリング時点をこのアイ開口度の最も災ぎい
時点に設定するには、り・ラグ１盲□生向藷・□（４）
からの再生クロ′ツク信号、Ｃ，の位相を手動移相器（
３）により手動で設定するのか常であった。Conventionally, to set the sampling point to the most critical point for this eye opening degree, ri・lag 1 blind □ raw direction ・□ (4)
A manual phase shifter (
3) It was usual to set it manually.
しかしなから、伝送信号に１．、フェージング、非線形
性など伝送路によるひずみが生じて米た場合、タロツク
の位相は、１当初設定した位相からずれてしたはずのク
ロラダ位相は、八はやアイ開口度の最大点からずれてい
うこ乍かある。、。However, the transmission signal has 1. If distortions occur due to the transmission path, such as fading, nonlinearity, etc., the phase of the tarokku will be shifted from the initially set phase, but the phase of the clock will be shifted from the maximum point of the eye opening. There is. ,.
この発明は上記〒ような従来のもの′ア問題点に鑑みて
なされたもので、手動移相器の代りに可変移相器を用°
゛・第１′！：′識別ｉ相姦０他に該識別再生器より進
んだ又は遅れたターイミングで識別再生を行なう第２．
第３の識別再生器を設け、第２゜第３の両識別再相姦の
出力を用いて上記可変移相器の移相量を制御することに
より、上記のように伝送路に歪が生じて米てこれが原因
で受信ベースバンド信号をサンプリングする再生クロッ
ク信号、 、： 、 、、、ｏ？、、、位相がずれて米
た場合、自動的ｌど位相のずれを除去できる自動クロッ
ク位相設定回路を提供するこ′七を目的としている。This invention was made in view of the above-mentioned problems with the conventional method, and uses a variable phase shifter instead of a manual phase shifter.
゛・1st′! :'Identification i incest 0 In addition, the second.
By providing a third discrimination regenerator and controlling the amount of phase shift of the variable phase shifter using the outputs of the second and third discrimination regenerators, distortion is generated in the transmission path as described above. This causes the regenerated clock signal to sample the received baseband signal, , , , , , o? It is an object of the present invention to provide an automatic clock phase setting circuit that can automatically remove the phase shift when the phase shift occurs.
以下、この発明９一実施例を図について説明す・ る。Hereinafter, 91 embodiments of this invention will be explained with reference to the drawings.
第１′図において、（１）は受信ベースバフ ト（ｆ
％、（５）は受信ベースバンド信号（１）よりクロック
Ｃを再生す、るクロック再生回路、（８）はクロック再
生回路（５）からのクロックＣを移相する可変移相器”
Ｊｌ、５］は可変移相器（８１の出力め位相□をτだけ
進めｇ進み移相器、（７）は可変舒相器（８）の出力の
位相をτだけ遅らせる遅れ移相器、＋長）＋’５例え／
ば□ディレイフηツブフロップ（ＭＬｒＦ）で構晟され
、ぴ移相器（８）の、出力、を叩い工誉、信−一・バ了
ド信号は）から受信データ信号ＬＩ２１を識別再生する
第１の識別ｐ）止器、（３）１４）は同じ（Ｄ−ＦＦ等
で構成され、受信ベースバンド信号（１）が入力されそ
れぞれ上記進み移相器（６）および遅れ移相器（７）の
出方を用いて識別再生動作を行なう第２および第３の識
別再生器、（９）は第１゜第２の識別再生器＋２１ ＋
３＋の出力が入力される７４＜ ｌの排他的論理和（Ｅ
Ｘ ＯＲ） 回路、ａＯ）ハ第１を第３の識別再生器
ｔ２１ Ｉ４）の出力が入力される第２の排他的論理オ
ｐ（ＥＸＯｋ）回路、ｄｌ）は上記第１および第１２の
排他的論理和回路＋９） ＣＩ［ｊの出力によ鷲り上記
可変移相器（８）の移相量を制御する移相１制゛御手段
としてのアップ／ダウンカウンタで、アップ入力端子に
は第１の排他的論理和回路（９）の出１力が、タ゛ウン
入力端子には第２の排他的論理和回路叫・の出力がそれ
ぞれ入力されている。また（１３）はアップ／ダウンカ
ウンタＵ］）のリセット信号である。In Figure 1', (1) is the received base buffer (f
%, (5) is a clock regeneration circuit that regenerates clock C from the received baseband signal (1), and (8) is a variable phase shifter that shifts the phase of clock C from clock regeneration circuit (5).
Jl, 5] is a variable phase shifter (g leading phase shifter that advances the output phase □ of 81 by τ, and (7) is a lagging phase shifter that delays the output phase of the variable phase shifter (8) by τ. +long)+'5 example/
The output of the phase shifter (8), which is constructed with a delayed ? The identification p) stop devices, (3) and 14) are composed of the same (D-FF, etc.), and the received baseband signal (1) is inputted to the lead phase shifter (6) and the delay phase shifter (7), respectively. The second and third identification regenerators perform the identification reproducing operation using the appearance of the 1° second identification regenerator + 21 +
Exclusive OR (E
A second exclusive logic op (EXOk) circuit to which the output of the first and third identification regenerator t21 I4) is input, dl) is the first and twelfth exclusive An up/down counter is used as a phase shift 1 control means to control the amount of phase shift of the variable phase shifter (8) according to the output of CI[j, and the up input terminal has an up/down counter. The output of the first exclusive OR circuit (9) and the output of the second exclusive OR circuit (9) are input to the time input terminal, respectively. Further, (13) is a reset signal for the up/down counter U].
次に動作について説明する。Next, the operation will be explained.
今、伝送路・の泣によってクロック再生回路（５）の出
力クロックＣ位相が△だけ遅れたとする。この場合、４
１の１識別再生器（２）では１１表２図のサンプリング
時点ｔ１に示すようイこ、サントリング時点は、アイ開
口最大点よりΔだけ遅れることになる。また第２の識別
再生器（３）で“はサンプリング時点Ｌ３で識別再生す
ることになり、又、第３の識別再生器（４）では、サン
プリング時点ｔ２で識別再生する□ことになる。識別再
生器（２）出力は受信データ信号（１２）であり、識別
再生器（３）及び・（４）出力は受信データ信号（Ｉ４
に比べて＋τ進み又は遅れのクロックでサンプリングし
ている故、これを受信データと考えると、受信データと
しては、識別再生器（２）出ｐデークよ。Now, assume that the phase of the output clock C of the clock regeneration circuit (5) is delayed by Δ due to the failure of the transmission line. In this case, 4
In the case of the 1-identification regenerator (2), the sampling time is delayed by Δ from the maximum eye opening point, as shown at the sampling time t1 in Table 2. In addition, the second identification regenerator (3) will perform identification and reproduction at the sampling time point L3, and the third identification regenerator (4) will perform identification and reproduction at the sampling time t2.Identification The output of the regenerator (2) is the received data signal (12), and the output of the identification regenerator (3) and... (4) is the received data signal (I4).
Since it is sampled with a clock that is +τ ahead or behind compared to , if this is considered as received data, the received data is the output p data of the identification regenerator (2).
りは誤り率は大きい。ただしτはτ〉会であるよ。The error rate is high. However, τ is τ〉.
うに設定しておくことにす、る。・ ・ 、・
□＋１．．”ｒ、ＲＳ＋Ｊ。’ＩＥｒｆ、３２
１（３１゜、１．。、。、。４１．□ ヲの・Ｅ Ｘ
Ｏ，１ｌｉｔ・回路（９）で辿ると、その出力は両者の
出力が不一致の場合１１′となり、一致する場合ｆ０１
となる。ここで、・ＥＸ、ＯＲ回路（９）の出力が１１
１と ：なった場合は、識別再生器（３）出力デー
タが誤ったと考えるのが普通である。識別再生器＋２１
１４．１出力□の排他的論理和は同様に゛第２のＥＸＯ
Ｒ回路α０でとることにする。I decided to set it to .・ ・ ・ ・
□+1. ．． "r, RS+J.'IErf, 32
1 (31°, 1..,.,.41.□ Wono・E
O,1lit・If traced by circuit (9), its output will be 11' if the two outputs do not match, and f01 if they match.
becomes. Here, the output of EX and OR circuit (9) is 11
1 and :, it is normal to think that the output data of the identification regenerator (3) is incorrect. Identification regenerator +21
14.1 The exclusive OR of the output □ is similarly
Let us take R circuit α0.
９さて、Δ〜０ならは、Ｅ Ｘ、０．凡回路（９）出力
に」１１ □の出現する頻度とＥＸＯＲ回路（１０
）出力に１１１の出現する頻度は同等である。
□ 。9 Now, if Δ~0, then EX, 0. Ordinary circuit (9) The frequency of appearance of "11 □" in the output and the EXOR circuit (10
) The frequency with which 111 appears in the output is equivalent.
□.
識別再生器（２）のサンプリング時点・１．がアイ開口
最大点より△だけ遅れ、た場合、サントリング時点のア
イ開口度は、識別再生器（３）のτ進みのサンプリング
の方が識別出生器、４）の−ｒ遅れのサンプリングより
も入きい故、Ｅ Ｘ ＯＲ回路（９）出力の１１１発生
ガ４度の方かＥＸＯＲ回路（１０）のそれよりも小さく
なる。したかつて、ＥＸＯＲ回路（９）出力とＪｉ Ｘ
Ｏ枝回路（１０）出力をそれぞれアップ／ダウンカウ
ンタｆｉｌ）のアップ入力端子及びダウン入力端子に入
力して、一定時間カウントすれは、アップ／ダウンカウ
ンタ（１１］の内容は減少する。Sampling time of identification regenerator (2)・1. lags behind the maximum eye opening point by △, the eye opening degree at the point of santling is determined by the τ-advanced sampling of the identification regenerator (3) than the −r-delayed sampling of the identification generator (4). Because of the large input, the 111 generated signal of the output of the EXOR circuit (9) is 4 degrees, which is smaller than that of the EXOR circuit (10). Once, the EXOR circuit (9) output and Ji
When the output of the O-branch circuit (10) is input to the up input terminal and the down input terminal of the up/down counter fil) and counts for a certain period of time, the contents of the up/down counter (11) decrease.
同様に識別再生器（２）のサンプリング時点【１力アイ
開口＋ ｉυ′犬点より、へたけ進んだ場音、アップ／
ターランカウンタ（１１）の内容は増加する。従って、
アップ／ダウンカウンタ（１１１ｉこスレツー／ヨＪＬ
ドεを設（１ておき、ますリセツｌ−（Ｈ吋（１３）で
アップ／ダウンカウンタ（１１）をリセットした後、一
定時間カウントし、カウント終了時にカウント晴Ａをチ
ェックし、囚（６ｆ、ｆらはこのアップ／ダウンカウン
タ（１１）は（ｉ’Ｊ ４せず、Ａ〈−さならはＴｊｌ
変移相器（８）の出力位相を少々拒め、ノ〜〉→−さな
らは１丁変没２相器（８）の出力位相を少々遅らせるよ
りにして、同時にリセット信号ｔ１３＋によってアップ
／ダウンカウンタ（１１）をリセットした後、更１こカ
ウントを再開ずれは、識別再生器（２）のサンプリング
時点は常にアイ開１」度の最大付近（こおくことが可能
となる。Similarly, the sampling point of the identification regenerator (2) [1 force eye opening +
The content of the taran counter (11) increases. Therefore,
Up/down counter (111i this thread/yo JL
After setting up/down counter (11) with 1, reset the up/down counter (11) with H (13), count for a certain period of time, check the count clear A at the end of counting, and , f, this up/down counter (11) is (i'J 4, A<-bye Tjl
The output phase of the phase shifter (8) is slightly rejected, and the output phase of the two-phase shifter (8) is slightly delayed, and at the same time, the up/down counter is activated by the reset signal t13+. After resetting (11), it is possible to resume counting by one more time, so that the sampling time of the identification regenerator (2) is always near the maximum eye opening of 1 degree.
なＳ、上記実施例の説明はベースハンド伝送について述
べたか、；−発明はこれに限定されるものではなく、２
相、４相など、任意の整数Ｍに対し、Ｎ１相１） Ｓ
Ｋ信号伝送についても適用でき、同様の効果をｒするこ
とかできる。S. Did the description of the above embodiment refer to base hand transmission? - The invention is not limited thereto;
phase, 4 phases, etc., for any integer M, N1 phase 1) S
It can also be applied to K signal transmission, and similar effects can be obtained.
以」−のよう１こ、この発明によれば手動移相器の代り
にｉ’Ｔ変移相器を用い第１の識別再生器の他に第２．
第３の識別再生器を設り゛、この第２．第３のｄ哉別再
相姦の出力を用いてアイパターン最大開口点かｂの第１
の識別再生器のサンプリング時点のずれの方間を検出１
〜これにより（ｊＪ変移相器の移４目漬を制１１１ｉ１
１−てサンプリング時点を）Ｌに灰ずようｊこしたので
、伝送路に歪か生し７、ぞの歪か時々刻々変化したりす
ることが原因で、再生クロツクの位相か受信信号波形の
位相に比べてずれて米るような場音でも、自動的にその
ずれを除去することかできる効果がある。According to the present invention, an i'T phase shifter is used instead of a manual phase shifter, and a second identification regenerator is used in addition to the first identification regenerator.
A third identification regenerator is provided. Using the output of the third d and re-incest, the eye pattern maximum opening point or the first
Detecting the difference in the sampling time of the identification regenerator 1
〜Thus (111i1 to control the shift of the jJ phase shifter)
1) Since the sampling time point has been reduced to L), distortion may occur in the transmission path. 7. This distortion may change from time to time, causing the phase of the reproduced clock or the received signal waveform to change. Even if the field sound is out of phase, it can automatically remove the difference.
第１図は、不発ｌ！８の一実施例による自動クロック位
相段ボ回路のグ［１ツク図、第２図は受信へ一スパント
イア１吋のアイパターンの一例およびサンプリング時点
を示す図、第３図は従来の自動クロック位Ａｌｌ設定回
路のブ「コック図である。
図においで、（２）ないしく４）は第１ないし第３の識
別再生器、（５）はりａツク回生回路、（６）は進み移
相器、（７）は遅れ移相器、（８）はり＆移相器、ｉ９
） ＋！０！は第１、弔２の拮（＋１Ｌ的論理、＋１１
回路、（１１）はアップダウンカウンタ （杉・（↓］
ｉｉｔ ’ｉｌｉ制御手段）である。
なお図中向−符号は同−又は相当部分を示す。
代丹人 ８７ 更ｊ 信 −Figure 1 shows the misfire! Figure 1 is a diagram showing an example of an eye pattern and sampling time point for one span of one inch to the receiver, and Figure 3 is a diagram showing a conventional automatic clock phase stepboard circuit according to an embodiment of the invention. This is a block diagram of the All setting circuit. In the figure, (2) to 4) are the first to third discrimination regenerators, (5) the beam regeneration circuit, and (6) are the advance phase shifters. , (7) is a delay phase shifter, (8) beam & phase shifter, i9
) +! 0! is the 1st, the 2nd companion (+1L logic, +11
Circuit, (11) is up/down counter (Sugi・(↓)
iit 'ili control means). Note that the numbers in the figures indicate the same or equivalent parts. Daitanjin 87 Saraj Shin −
Claims (1)
ロンクｉＪＴ生回路と、上記クロックを移相する可変移
相器と、該可変移相器の出力の位相を進める３ｆｉみ移
相器と、」二記町変材・相器の出力の位相を遅らせる遅
れ移相器と、上記可変移相器の出力を用いて−１１記受
信ベースバンド信吋から受信デー８リ タ信号を識引杓生ずる第１の識別再生器と、−１−記受
情ベースバンド信号が入力されそれぞれ士、記進み移相
器および遅れ移相器の出力を用いて識別再生動作を行う
第２および第３の識別Ｐｓ生相姦、上記第］、第２の識
別再生器の出力か人力される第１の稍他的論月１和回路
と、−ト記第１．第３の識別再生器の出力が入力される
第２の排他的論理オ［１回路と５−に記第Ｊおよび第２
の排他曲論ｉ！７！利回路の出力により上記可変移相器
の移相はをｊｌｊ制御する移相＠ ｆｌｉ制御手段とを
伽えたことを特徴とする自動クロック位相設定回路。[Claims] (]) A Cronk iJT generation circuit that regenerates a clock from a received baseband signal, a variable phase shifter that shifts the phase of the clock, and a 3fi shifter that advances the phase of the output of the variable phase shifter. A phase shifter, a delay phase shifter that delays the phase of the output of the Nikimachi transformer/phase shifter, and the output of the variable phase shifter are used to convert the received data 8 retardation signal from the -11 received baseband signal. A first discrimination regenerator generates a signal, and a second discrimination regenerator receives a -1-digit reception baseband signal and performs a discrimination and reproduction operation using the outputs of the lead phase shifter and the delay phase shifter, respectively. 3rd identification Ps raw incest, the above-mentioned No. 1], a first altruistic logic sum circuit which is manually powered by the output of the second identification regenerator; The output of the third identification regenerator is inputted to the second exclusive logic circuit [1 circuit and the J and second
Exclusive song theory i! 7! An automatic clock phase setting circuit characterized in that it further comprises phase shift@fli control means for controlling the phase shift of the variable phase shifter according to the output of the variable phase shifter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58046343A JPS59171233A (en) | 1983-03-17 | 1983-03-17 | Automatic lock phase setting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58046343A JPS59171233A (en) | 1983-03-17 | 1983-03-17 | Automatic lock phase setting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59171233A true JPS59171233A (en) | 1984-09-27 |
| JPH0142537B2 JPH0142537B2 (en) | 1989-09-13 |
Family
ID=12744489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58046343A Granted JPS59171233A (en) | 1983-03-17 | 1983-03-17 | Automatic lock phase setting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59171233A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04301942A (en) * | 1991-03-28 | 1992-10-26 | Nec Corp | Eye pattern identifying and reproducing circuit |
| WO1994024792A1 (en) * | 1993-04-08 | 1994-10-27 | Northern Telecom Limited | Phase alignment methods and apparatus |
| US7016403B2 (en) | 2000-07-10 | 2006-03-21 | International Business Machines Corporation | Apparatus and method for determining the quality of a digital signal |
| JP2008124714A (en) * | 2006-11-10 | 2008-05-29 | Hitachi Ltd | Semiconductor integrated circuit device |
| US7474720B2 (en) | 2002-11-29 | 2009-01-06 | Hitachi, Ltd. | Clock and data recovery method and digital circuit for the same |
| JP2009212992A (en) * | 2008-03-06 | 2009-09-17 | Hitachi Ltd | Semiconductor integrated circuit device and eye open margin evaluation method |
| JP2009218946A (en) * | 2008-03-11 | 2009-09-24 | Hitachi Ltd | Signal recovery circuit |
| JP5232913B2 (en) * | 2009-04-30 | 2013-07-10 | 株式会社アドバンテスト | Clock generation apparatus, test apparatus, and clock generation method |
| JP2013219641A (en) * | 2012-04-11 | 2013-10-24 | Mitsubishi Electric Corp | Data transmission device |
-
1983
- 1983-03-17 JP JP58046343A patent/JPS59171233A/en active Granted
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04301942A (en) * | 1991-03-28 | 1992-10-26 | Nec Corp | Eye pattern identifying and reproducing circuit |
| WO1994024792A1 (en) * | 1993-04-08 | 1994-10-27 | Northern Telecom Limited | Phase alignment methods and apparatus |
| US5432480A (en) * | 1993-04-08 | 1995-07-11 | Northern Telecom Limited | Phase alignment methods and apparatus |
| US7016403B2 (en) | 2000-07-10 | 2006-03-21 | International Business Machines Corporation | Apparatus and method for determining the quality of a digital signal |
| US7474720B2 (en) | 2002-11-29 | 2009-01-06 | Hitachi, Ltd. | Clock and data recovery method and digital circuit for the same |
| JP2008124714A (en) * | 2006-11-10 | 2008-05-29 | Hitachi Ltd | Semiconductor integrated circuit device |
| JP2009212992A (en) * | 2008-03-06 | 2009-09-17 | Hitachi Ltd | Semiconductor integrated circuit device and eye open margin evaluation method |
| JP2009218946A (en) * | 2008-03-11 | 2009-09-24 | Hitachi Ltd | Signal recovery circuit |
| JP5232913B2 (en) * | 2009-04-30 | 2013-07-10 | 株式会社アドバンテスト | Clock generation apparatus, test apparatus, and clock generation method |
| US8897395B2 (en) | 2009-04-30 | 2014-11-25 | Advantest Corporation | Clock generating apparatus, test apparatus and clock generating method |
| JP2013219641A (en) * | 2012-04-11 | 2013-10-24 | Mitsubishi Electric Corp | Data transmission device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0142537B2 (en) | 1989-09-13 |
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