JPS59171171A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPS59171171A JPS59171171A JP4482083A JP4482083A JPS59171171A JP S59171171 A JPS59171171 A JP S59171171A JP 4482083 A JP4482083 A JP 4482083A JP 4482083 A JP4482083 A JP 4482083A JP S59171171 A JPS59171171 A JP S59171171A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- region
- metal
- gate electrode
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title description 10
- 150000001875 compounds Chemical class 0.000 title description 6
- 239000002184 metal Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 23
- 150000002500 ions Chemical class 0.000 claims abstract description 12
- 238000002844 melting Methods 0.000 claims abstract description 11
- 230000008018 melting Effects 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 229920001296 polysiloxane Polymers 0.000 claims 2
- OPFJDXRVMFKJJO-ZHHKINOHSA-N N-{[3-(2-benzamido-4-methyl-1,3-thiazol-5-yl)-pyrazol-5-yl]carbonyl}-G-dR-G-dD-dD-dD-NH2 Chemical compound S1C(C=2NN=C(C=2)C(=O)NCC(=O)N[C@H](CCCN=C(N)N)C(=O)NCC(=O)N[C@H](CC(O)=O)C(=O)N[C@H](CC(O)=O)C(=O)N[C@H](CC(O)=O)C(N)=O)=C(C)N=C1NC(=O)C1=CC=CC=C1 OPFJDXRVMFKJJO-ZHHKINOHSA-N 0.000 claims 1
- 229940126086 compound 21 Drugs 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 6
- 230000004913 activation Effects 0.000 abstract description 5
- 229910021332 silicide Inorganic materials 0.000 abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 230000003287 optical effect Effects 0.000 abstract description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 2
- 108091006146 Channels Proteins 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 10
- 150000002739 metals Chemical class 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- -1 silicon ions Chemical class 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000002547 anomalous effect Effects 0.000 description 1
- 208000027697 autoimmune lymphoproliferative syndrome due to CTLA4 haploinsuffiency Diseases 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は、化合物半導体Ｍ Ｅ Ｓ −Ｆ Ｅ ’Ｆを
セルフ・アラインメントツノ式で製造する際に用いて好
適な化合物半導体装置の製造方法にｌ！ｊｌ−４−る。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention provides a method for manufacturing a compound semiconductor device suitable for use in manufacturing a compound semiconductor MES-FE'F using a self-alignment horn method. jl-4-ru.
従来技術と問題点
一般に、例えは、（Ｊ ａΔＳを用いたＭ ｆ’： Ｓ
Ｆ１尤゛「を製造する際、ソース領域及びトレーイ
ンａｉ’ｊ域を形成するのｔこケート′成極をマスクと
１′る・イオン注入法を適用するセルフ・アラインメン
トツノ式を採って小型化し、ソース・グーＩ・間及び）
γ−１・トレイン間の抵抗を小さくしてｉＨ＋周波特＋
１１を向トすると共に高集積化することがマラなねれて
いる。Prior Art and Problems In general, an example is (M f' using J aΔS: S
When manufacturing the F1, the source region and the train region are formed using a self-alignment horn method that uses the electrode polarization as a mask and applies ion implantation to achieve miniaturization. , source goo I, and)
Reduce the resistance between γ-1 and train to improve iH+frequency characteristics+
11 and higher integration is becoming a trend.
その場合、注入されたイオンを活ＩＴＩ化する為、半導
体装置を一定のｌ（’Ｇ ？！ｉ＋にイイ１持された電
気ＤｊＣ旧ｉｌｉ人してアニールするが、この技？ｊ−
，に依ると半導体装置全体が１１１）’／ｒ情になるの
で、グー１電極直１；の活りＩｔ層（以下チャネル領域
と呼ぶ）に対して種々の悪影響を及はされる。例えは、
ギャリｊ−（７月１１分槓］、半絶縁性Ｇ ａへＳ基板
の熱変性に依る半絶縁１７１の劣化、ソース領域或いε
」トレイン領土・ｋからチャネル領域へのイオンの熱拡
散に依るナヤイ、小領域のキャリヤ濃度及びその分布の
変化、ＧａΔこりｊｌｌ＆とケート電極材料或いはＧａ
Ａｓ基４＆と保護Ｉｌψとの間、の熱膨張率差に依りア
ニール時に生ずるスト。In that case, in order to activate the ITI of the implanted ions, the semiconductor device is annealed using a certain amount of electricity ('G?!i+), but this technique...
, the entire semiconductor device becomes 111)'/r, which has various adverse effects on the active It layer (hereinafter referred to as channel region) of the electrode 1;. For example,
Gary J- (published on July 11th), Deterioration of semi-insulating 171 due to thermal degeneration of S substrate to semi-insulating Ga, source region or ε
'Nayai due to thermal diffusion of ions from the train region/k to the channel region, changes in the carrier concentration in the small region and its distribution, GaΔ stiffness jll & and the gate electrode material or Ga
Stroke occurs during annealing due to the difference in thermal expansion coefficient between the As group 4& and the protected Ilψ.
レスで誘起される界面でのイオンの異常拡散−基−１づ
くチ・・不″領域のキャリヤ濃度圧ｑ′り、雫分布９．
。Anomalous diffusion of ions at the interface induced by droplets - group-1 - carrier concentration pressure q' in the non-resistance region, droplet distribution 9.
.
前記したチャネル領域への影響は、デバイス特□性から
見ると主、とじて、闇値、−圧の変動として現われる。The above-mentioned influence on the channel region mainly appears as changes in the dark value and -pressure when viewed from the device characteristics.
従来、前記チャネル領域の影響の大きさは、基板毎に異
なる為、所望の闇値電圧を制御性良く得ることは困難と
・されてきた６、・ ・ 。Conventionally, it has been considered difficult to obtain a desired dark voltage with good controllability because the magnitude of the influence of the channel region varies from substrate to substrate6.
また、前記異當拡散：の・大きさは、、ゲート電極の向
きに依って相違する為、セルフ・アラインメント方式で
作製されるＧａＡ、ｐ−ＭＥＳ−ＦＥＴを基本デバイス
として備、えるＧ ａ ＡＳ集積回路Ｇミ於いては、へ
そのゲート電極の、向きを全て揃えなげればならない旨
の設計上の制御的が存在していた。In addition, since the size of the above-mentioned abnormal diffusion differs depending on the orientation of the gate electrode, Ga AS is equipped with a GaA p-MES-FET manufactured by a self-alignment method as a basic device. In the integrated circuit G-mi, there was a design control requirement that required all gate electrodes to be aligned in the same direction.
更に、前記したようなソース領域或いはトレイン領域か
らチャネル領域への２種類のイオンの拡散は、ＧａＡｓ
−ＭＥＳ−ＦＥＴのゲート長が短くなるにつれ、より大
きな闇値電圧の変動を招来、、する為、ゲート長が短い
、例えば１ 〔μｒｎ、 ）以−ト・ 置
のセルフ・アラインメンｉ・方式ＧａΔｓ−ＭＥＳ：、
■、・二・ＦＥ・実を闇値電圧がばらつかないように制
御性良く製造することは困難である。Furthermore, the diffusion of the two types of ions from the source region or train region to the channel region as described above is
-As the gate length of the MES-FET becomes shorter, it causes a larger fluctuation in the dark voltage. Therefore, when the gate length is short, for example, 1 [μrn, ), the self-alignment method GaΔs -MES:,
2. It is difficult to manufacture FE with good controllability so that the dark value voltage does not vary.
： このような↓ルシ＼、アラインメント方式でＧａ”
Ａ ｓ −ＭＥ Ｓ−Ｆ Ｂ’Ｔを製造する際にイオン
注入法を採用した場合の熱処理に関する問題と関連して
、ゲート電極を耐熱性が高い金属、所謂、高融点金属及
びそのシリサイドで形成し、イオンを活性化する為の高
温、少なくとも８００（℃）の冶１度での熱処理を経た
。後でやってもケート電極が安定なショット半特性を維
持できるようにする試みがなされている。 。: Like this ↓ Luci\, Ga” by alignment method
In connection with the problem of heat treatment when ion implantation is used to manufacture A s-ME S-F B'T, the gate electrode is formed of a metal with high heat resistance, a so-called high-melting point metal, and its silicide. Then, it underwent heat treatment at a high temperature of at least 800 (°C) to activate the ions. Attempts have been made to enable the cathode electrode to maintain stable shot semi-characteristics even after subsequent use. .
そのようなゲート電極となる高融点金属としては９、Ｗ
、 Ｔ ｉ Ｏ，３Ｗ０．７１ Ｍ ｏ ｑが、また
、それ等のシリ′＋１ブトとして、は１．例えば、竺Ｓ
・・、 ”］’ ｉ ０．３Ｖｊ’ｏ、７’ｓｊｘ ’
、 Ｍ ｏ Ｓ ｉ １．等が使用されている。然し乍
ら、このような高融点金属或いはそのシリサイドは、表
１に示すように、最も理想的な場合でも、Ａｕ、へ１等
の低抵抗金属に比較して比抵抗は１桁以上も大きく、そ
れをゲ°−ト電極材料として用いた場合にはゲート抵抗
の増大をＴすので、その面での性能低下は避けられない
。Examples of high melting point metals that can be used as such gate electrodes include 9 and W.
, T i O,3W0.71 M o q, and as their sili'+1 but, is 1. For example, Jiku S
..., ”]' i 0.3Vj'o, 7'sjx'
, M o S i 1. etc. are used. However, as shown in Table 1, even in the most ideal case, the resistivity of such high melting point metals or their silicides is more than an order of magnitude higher than that of low resistance metals such as Au and Al. When this material is used as a gate electrode material, the gate resistance increases, so a decrease in performance in this respect is unavoidable.
表１” ””′
金属湯 比抵抗〔９ｃｍ） ’Ｔ ｉ
Ｗ ’ ５’ Ｘ’ｌ ’０””５
Ｗ ５ 、 ｓ×’ｔ ｏ−６Ｍ
ｏ ” ５．６”’Ｘ ’ ｉ 、０−６Ｔ’
ｉ Ｗ Ｓ ｉ ” ８””Ｘ”’１’ ０−５ＷＳ
ｉ２ ３’ｘ Ｉ Ｏ”’Ｗｌ； Ｓ ｉ
３ ”ｌ’、 ｓ×’ｉ ｏ、：。Table 1” ””′ Metal hot water specific resistance [9cm) 'T i
W '5'X'l'0""5
W 5, s×'t o-6M
o ” 5.6”'X' i, 0-6T'
i W S i ” 8””X”’1’ 0-5WS
i2 3'x I O"'Wl; S i
3 ``l', s×'i o,:.
Ｍ’ｏ Ｓ ｉ ２ ’ ４ ×、、 ０
’−’ｉＡ ｕ ’２ 、’ ４’
Ｘ １ ’０＝ＡＩ２ ’ ”１’、’
６４×１”０−６′また、前記高融点金属シリサイドの
らちでは、Ｗ’Ｓ’ｉ ”Ｘ ’（Ｓ Ｉ ： １ ’
０ （モル％））がＡ’ｕ′の裏表子な拡散防止層とし
て働き、５０′ｏ ｃ″℃〕℃〕程度理を行なった後に
もＧ’ａＡｓとの間に良好なショット半特性を示すこと
及びＴｊ’Ｎ”：ｊ’Ａ’ｕ ｃ７）拡散防止層となる
ことが知られている。′
そして、実験に依ると、ＷＳ ｉ Ｘ （０，３≦Ｘ≦
０．８）／Ａｕ或いばＷＳ ｉ ｘ’＜’Ｏ、’ ３≦
Ｘ≦０．８）ンＴｉ／Ａｕ或いはＷＳｉＸ （０，３＄
Ｘ≦Ｏ’、 ８） ／Ｔ ｉ Ｎ’／Ａ ｕ等をケート
電極に適用した場合、７００・ｃ℃〕の温度で熱処理を
行なった後であっても良好なショットギ特性を維持てき
ることが確認されている。然し乍ら、これであっても、
セルフ・アラインメント方式を適用するＧ ａ ′Ａｓ
−Ｍ”Ｂ Ｓ −’Ｆ Ｅ Ｔの製造は不可能である
。M'o S i 2 ' 4 ×,, 0
'-'iA u '2, '4'
X 1 '0=AI2 '``1'','
64×1"0-6' Also, in the case of the high melting point metal silicide, W'S'i "X' (SI: 1'
0 (mol%)) acts as a diffusion prevention layer for A'u', and maintains good shot semi-characteristics with G'aAs even after 50'oC''°C]. and Tj'N'':j'A'u c7) It is known that it becomes a diffusion prevention layer. ′ And, according to the experiment, WS i X (0,3≦X≦
0.8)/Au or WS i x'<'O,' 3≦
X≦0.8) Ti/Au or WSiX (0.3$
X≦O', 8) When /T i N' /A u, etc. are applied to a cathode electrode, good shotgun characteristics can be maintained even after heat treatment at a temperature of 700 cm. has been confirmed. However, even with this,
G a ′As applying self-alignment method
-M''BS-'FET cannot be manufactured.
□その理由は、イオン注入法で形成されたソース領域及
びドレイン領域の活性化には８００（’Ｃ〕或いε韮そ
れ以□」二の温度に依る熱処理を要するからである。□The reason is that activation of the source and drain regions formed by ion implantation requires heat treatment at a temperature of 800°C ('C) or ε2 or higher.
発明の目的
本発明は、尋ルフ・アラインメン；方式及びイオン注入
法を適用して特性良好なＧ ａ Ａ ｓ −Ｍ ＥＳ
−Ｆ ＩＥ Ｔの如ぎ化合物半導体装置を再現性良く製
造する方法を提供しようとするものである。Purpose of the Invention The present invention provides a GaAs-M ES with good characteristics by applying a low-level alignment system and an ion implantation method.
- It is an object of the present invention to provide a method for manufacturing a compound semiconductor device such as F IET with good reproducibility.
発明の構成
本発明では、Ｇ 、ｌ Ａ’Ｓ”＝ Ｍ Ｅ Ｓ −Ｆ
Ｅ Ｔを含む化合物半導体装置をセルフ・アラインメ
ンＩ・方式で製造するに際し７．１０Ｊ融点金属或いは
そのシリザイ）・からなる層と該１１″ち周１点金属或
いはそのシリザイ１及びΔＩＪ等の低抵抗金属のいずれ
にも密着性が１に々ｆで目、つ前記層を成す金属と前記
低抵抗金属との金属学的反応を抑制し得る金属からなる
介在層とΔＵ等の低抵抗金属層とを順に積層した三層構
造をなすケート電極を採用し、ある程度の耐熱１（［と
良好な導電性を維持てきる。！、、うにし、そして、こ
のようなグー１電極を用いた場合、電気炉中でソース領
域及０］・し・イン領域の活性化に必要な８００（’Ｃ
）の温度で加熱することは不ｉ＋Ｊ能である為、レーザ
光或いはその他の光を照射してアニールを行なう、所謂
、光学的１段に依りアニールを行なう技術を適用するこ
とに依り、ケート電極をマスクとしてイオン注入法で形
成されたソース領域及びドレイン領域の活性化を行なう
ようにし、半導体装置を局部的に、しかも、ごく浅い部
分のみを昇温させるようにし、光か照射されない部分、
従っ−ζ熱処理か不要である部分への熱的な悪影響か及
ばないようにしている。Structure of the Invention In the present invention, G, lA'S"=MES-F
When manufacturing a compound semiconductor device containing ET using the self-alignment method, a layer consisting of a 7.10J melting point metal or its silica) and a low resistance layer such as the 11" circumferential one-point metal or its silica 1 and ΔIJ are used. An intervening layer made of a metal that has adhesion to any of the metals and is capable of suppressing a metallurgical reaction between the metal forming the layer and the low resistance metal, and a low resistance metal layer such as ΔU. Adopts a three-layered electrode with a three-layer structure laminated in order, and maintains a certain degree of heat resistance and good conductivity. 800('C) required for activation of source region and in region in electric furnace.
) Since it is impossible to heat the electrode at a temperature of The source and drain regions formed by the ion implantation method are activated using the mask as a mask, and the temperature of the semiconductor device is raised locally, and only in very shallow parts, so that the parts not irradiated with light,
Therefore, no adverse thermal effects are exerted on parts that are not required during the ζ heat treatment.
即ち、ケーｉ・領域或いは１・し・イン領域を熱処理す
る為に光照射しても、グーｌ−電極及びその−１・側の
チャネル領域は、光がケート電極表面−Ｃ反射される為
、？ｒ、！を度士昇することかない。ｉｊＬゲで、１）
；Ｊ記電気炉を用いた従来技術のような欠点は解消され
る。That is, even if light is irradiated to heat-treat the K-I region or the 1-S-IN region, the light is reflected from the K-I electrode and the channel region on its -1-side because the light is reflected by the K-I region or the 1-S region. ,? r,! There is no way to raise the degree. In ijL game, 1)
; The drawbacks of the prior art using the J electric furnace are eliminated.
ところで、本発明の場合、アニールは局部的な昇温で行
なわれるので、ショットキ・ノ＼リアを形成するケーＩ
・電極月利としては高融点金属或いはそのノリサイトを
使用する必要はないかに思われようが、例えば、レーザ
光を照射されたＣＪ ａΔＳ基板の表面は、電気炉でア
ニールした場合の温度以上に高温になるので、ソース領
域及びＩ−レイン領域に近接するゲート電極のエツジ部
分に於いてそのンヨノｌ−キ特性は劣化する虞があり−
２その為、本発明でもデー１〜電極は高融点金属或いは
そのソリサイトを使用するようにしている。By the way, in the case of the present invention, annealing is performed by locally increasing the temperature, so that the case that forms Schottky no.
・It may not be necessary to use a high-melting point metal or its norisite as an electrode, but for example, the surface of a CJ aΔS substrate irradiated with laser light may reach a temperature higher than that when annealed in an electric furnace. Because of the high temperature, there is a risk that the horizontal characteristics of the edge portion of the gate electrode near the source region and the I-rain region may deteriorate.
2. Therefore, in the present invention, a high melting point metal or its soricite is used for the electrode.
然し乍ら、このような電極月利を使用した場合には、前
記した通り、Ａｕ或いはΔｐ等と比較して比抵抗かがな
りｉＲｉ （なる。これを軽減する為には、高融点金属
或いはそのシリサイド層上に低抵抗金属層、例えは金層
を形成する。ところが、そのような低抵抗金属層と前記
高融点金属等の層とは密着し難い場合が多いし、また、
それ等金属の金属学的反応を抑制する必要かある場合も
多いので、ケーＩ・電極と低抵抗金属層との間にその役
割を果すことが出来る別の金属からなる層を介在さゼな
ければならない。However, when such an electrode monthly rate is used, as mentioned above, the specific resistance becomes higher than that of Au or Δp. A low resistance metal layer, for example a gold layer, is formed on the layer.However, it is often difficult for such a low resistance metal layer to adhere to the layer of the high melting point metal, etc.
In many cases, it is necessary to suppress the metallurgical reaction of such metals, so a layer made of another metal that can fulfill this role must be interposed between the electrode and the low-resistance metal layer. Must be.
発明の実施例
第１図乃至第４図は本発明一実施例を）す２説する為の
工程要所に於りる半導体装置の要部切断側面図であり、
次に、此れ等の図を参照しつつ説明する。Embodiment of the Invention FIGS. 1 to 4 are cross-sectional side views of essential parts of a semiconductor device at important process points for explaining an embodiment of the present invention.
Next, explanation will be given with reference to these figures.
第１図参照
■ 比抵抗ρ−１０７〔ΩＣｍ）以上である半絶縁性Ｇ
ａΔＳ基板■に例えは通常のフＡ−１−リソグラフィ技
術を適用し、チャネル領域形成用窓を有してなるフ、！
１・・レジスト膜（図示せず）を形成する。See Figure 1■ Semi-insulating G with specific resistance ρ-107 [ΩCm] or more
For example, an ordinary film A-1-lithography technique is applied to the aΔS substrate (2), and a channel region forming window is formed.
1. A resist film (not shown) is formed.
■ イオン注入法を通用し２、ｎ型す、Ｉ−：リフ領域
形成用のシリコン・イオン、即ら、２８Ｓ、 ４のＨら
込みを行なう。(2) Using the ion implantation method, silicon ions for forming 2, n-type, I-: riff regions, ie, 28S, 4H are implanted.
この時のイオン注入条件は次の１ｆｆｌりである。The ion implantation conditions at this time are the following 1ffl.
注入イオン Ｓｌ
注人工不ルキ ５９（ＫｅＶ）
注入量 １×１０１２〔Ｃ１■″′２〕ピ一ク濃
度 ｎ ｐ ＝ １． 、４． Ｘ Ｉ Ｏ１７（Ｃ
ｍ−”）（Ｌ、５ＳＩＩ論値）
ピーク深さ Ｒｐ＝０．０５’Ｃμｍ〕尚、ここに於
けるｎ型チャイ、）Ｌ−領域２及び後記するソース領域
並びにトレイン領域とも不純物としてシリコンを使用し
ているか、これに限定されるものではない。Implanted ion Sl Injected artificial silica 59 (KeV) Implanted amount 1×1012 [C1■″′2] Peak concentration n p = 1., 4. X I O17 (C
m-") (L, 5SII theoretical value) Peak depth Rp = 0.05'Cμm] In addition, silicon is used as an impurity in the n-type chai here,)L-region 2, and the source region and train region to be described later. used, but not limited to.
■ アニールを次の条件で行なって前記ソリ二ｌン・イ
オンを活性化してＩＩ型チャネル領域２を形成する。(2) Annealing is performed under the following conditions to activate the solinium ions and form a type II channel region 2.
加熱源 電気炉
保護膜 Ｓ ｉ ０２
温度 ８５０（”ｃ）
ｌｔ′１間 １５〔分〕
第２図参照
■ 例えば、スペッタ法を適用１． ＋？さを例えるよ
１０ ｔ） Ｌ）〜２０１）０ （入］ とし７ノこ
Ｗ Ｓ ｉ Ｏ，６層３を形成し７、例えは、反ＬＬ、
１ｔ１スパツタ法を適用し１ｉ２さを例えば１００へ５
００ （人）とし７ノ、二Ｔ ｉ Ｎからなる介在層４
を形成し、例えは、真空茄着法を適用し厚さを例えは２
０００−・３００ＯＣ人］とした低）氏ｔｊＵ金属）ｉ
５を形成する。Heating source Electric furnace protective film S i 02 Temperature 850 (''c) Between lt'1 15 [minutes] See Figure 2 ■ For example, apply the sputtering method 1. +? 0 (in) 7 saws W S i O, 6 form layer 3 7, for example, anti-LL,
Apply the 1t1 sputter method and change the 1i2 value to 100, for example, 5
Intervening layer 4 consisting of 00 (person) and 7 and 2 T i N
For example, by applying the vacuum deposition method, the thickness can be reduced to 2
000-・300OC person] low) Mr. tjU metal) i
form 5.
、二の！、層構造は、全体で厚さ４５００ Ｃ人〕稈
度にすると良く、また、タンクスラーン・ンＩＪサイｌ
、１ｔｔｌら、ＷＳｉＸにＩｊＱ ＤＪるＸ埴しよ、０
．３≦Ｘ≦０．８の範囲で選択すると良い。, second! , the layer structure should have a total thickness of 4,500 C.
, 1ttl et al., IjQ DJ Ru X Hanyo to WSiX, 0
．． It is preferable to select within the range of 3≦X≦0.8.
■ フＡ１−・リックゝ・ライ技術及び（−ライ・コー
ノチング技術を適用し、低抵抗金属層５、介在層４、Ｗ
Ｓ ｉ ｏ、６１ｆｍ ３のパターニンクを舶に行な
いケ−１・電極を形成−４“る。■ Applying the F-A1-rick-lie technology and the -Lie-conching technology, the low-resistance metal layer 5, the intervening layer 4, and the W
A pattern of Sio, 61 fm 3 is formed on the vessel to form a case 1 and an electrode.
第３図参照
■ スパッタ法を通用し７、ＡＩＮからなるレー″ｌ）
・アニール保護膜６を厚さ例えば５００〜２０００、／
ｌ：入〕ｈ′１隻に形成する。尚、この保護１１曹（ｉ
：、ｉ、必須てはない。Refer to Figure 3■ Sputtering method can be applied 7, and a laser beam made of AIN (1)
・The thickness of the annealing protective film 6 is, for example, 500 to 2000,/
l: Enter] h' Form into one ship. In addition, this protected 11th grade (i
:, i, not required.
■ 真空力ネ１法を適用；−２、Ａ ｕ）ＩＡ 、ｋ
ｌｔｇ、 、Ｘ例、：ｊ ＋；ｔ４１０００〜２０００
Ｃ人〕稈度にル成し、（丁から１、−）・１．をフ
ォト・リソクン゛ノイ（支術に−（バター−〜ンクし、
ソース・トレイン領域形成用と非−ｊ’−：＝−ル）；
］つ分被子υ用とを兼ねたマスク膜７を形成−８１る。■ Apply vacuum force net 1 method; -2, A u) IA, k
ltg, ,X example,:j+;t41000~2000
Person C] Formed to culm degree, (from 1, -), 1. Photo-resokunnoi (butter-~ink),
For source train region formation and non-j'-:=-le);
] Formation of a mask film 7 which also serves as the molecule υ.
第４図参照
■ イＡン注入法を適用し、ｎ４型ソース領域及びｎ＋
型！レイン領域を形成する４為の Ｓｉ＋の））ら込Ｉ
ノ・を行なう。Refer to Figure 4■ Applying the ion implantation method, the n4 type source region and n+
Type! 4)) Lakomi I of Si+ to form the rain region
Do ノ.
この１１、シのイオン注入条件は次の通ぞンで４する。The ion implantation conditions of 11 and 4 are as follows.
注入イオン Ｓｉ＋
’ｔ＋人ｌ矛ルギ ２００ （Ｋ ｅ Ｖ）？上人量
Ｉ Ｘ １． ０”’ （ｃｍ
−２）ピーク濃度 １１ ” Ｐ ＝ ５ 、 ３
Ｘ Ｉ Ｌ）” （ｃ、ｍ−”：１（ＬＳＳ理論値）
ピーク深さ Ｒ４ｐ ＝ ０ 、 １７ （／１ｍ
〕■ レーザ・アニールを次の条（’Ｉで行なって前
記シリコン・イオンを活性化し、１１＋型ソ一ス領１代
８及びｒ］＋バ：ｊ ｊ’ ｌ／−１’ン領域９を形成
する。Implanted ion Si + 't + human l energy 200 (K e V)? Shonin quantity I X 1. 0"' (cm
-2) Peak concentration 11” P = 5, 3
X I L)” (c, m-”: 1 (LSS theoretical value) Peak depth R4p = 0, 17 (/1m
]■ Laser annealing is performed in the following steps ('I) to activate the silicon ions and to form the 11+ type source region 1 8 and r] + bar:j j'l/-1' type region 9. Form.
加熱源 ルヒー・レーザ
（呆１１隻ＩＩＱ ΔｐＮ
！１６射量１ 、７ ＣＪ ／ｃａｎ２）面、ここでは
、レーザとし７てルヒー・レーザを使用し７ていイ）か
、これは他のレーザ、例えば、ＹへＧレー４Ｊ゛、アル
コン（Ａｒ） レーザ等を適用することかできるのは
云うまでもない。Heating source: Luhi laser (11 IIQ ΔpN ! 16 radiation dose 1, 7 CJ /can2) surface, here we use a Luhi laser as laser 7), or it can be used with other lasers, e.g. Needless to say, G laser 4J'', Arcon (Ar) laser, etc. can be applied to Y, Y, etc.
０Φ この（で、通常の技法を適用し、ソース電極、１
−し・イン電極等を形成して完成する。0Φ With this (, apply the usual technique, source electrode, 1
- Complete by forming the in-electrode, etc.
前記実施例では適用しなかつ７メこか、レーザ・アニー
ルｌ；’Ｉｔ＋ ｂこ注入イオンの活性化をより自効に
行な・う為、外部から加熱して、半導体装置を数百°Ｃ
に（呆つようにしても良い。本実施例に於けるゲート電
極は７００ 〔’Ｃ）程度の熱処理を加えてもシヨ・ノ
（−キｌＩＱ’Ｉ’ｌｌｔは劣化しないから、外部から
補助的に加Ｐ！シすることは何等差支えない。In the above embodiment, laser annealing was not applied and in order to more effectively activate the implanted ions, the semiconductor device was heated to several hundred degrees Celsius by external heating.
The gate electrode in this example does not deteriorate even if it is heat-treated to about 700 ['C], so external assistance is not required. There is no problem in adding P!shi to others.
発明の効果
本発明は、高７７４４ ｒ：巳金属或いはそのシリサイ
トからなりチー１〜電極の一部をなしてミ／ヨノトキ
バリアを形成する層と、該層をな一４金属及Ｏ・へＵ等
の低抵抗金属の何れにも密着・ｌ’ｌか良くまたそイ１
．堝′金属の全屈学的反応を抑制することも出来る金属
からなる介在層と、Δ１」等の低抵抗金属層と′（構成
された二層構造のケート電極をマスクとし−ごイオン注
入を１−１ないセルフ・アラインメント方代−ζノース
領戚及びトレイン領域を形成し、ソース領域及びトレイ
ン領域の活１〕を化の為の熱処理をレーザ・アニール、
フラッジｊ、・アニール等の光’Ｆ” 的手段を依って
行なうようζこし−（いるの゛ご、その加熱は局部的り
つ浅い部分のめり？’ ′６＋！＋さ一部るように１−
１、光か照射されない部分、即ら、熱処理か不要である
部分への熱的な悪影響が及はないよ・）に−・Ｊるごと
かできる。その結果、チャイル６１′Ｊ域に於６ノるキ
ャリヤ濃度は安定に維持され、闇稙電）１−の変すリノ
ば発生せず、船性均−な化合物半ｊＪ７体装Ｗを出現測
長く製造することか出来、しかも、そのゲート電極の導
電性は掘めて良好である。Effects of the Invention The present invention provides high 7744r metal or its silicide, which forms part of the electrode.
The layer forming the barrier and the layer should be closely attached to any of the metals and low resistance metals such as O and U.
．． The ion implantation is performed using a two-layered gate electrode consisting of an intervening layer made of a metal that can suppress the total refractive reaction of the metal, a low-resistance metal layer such as Δ1, and a two-layer gate electrode as a mask. 1-1 Self-alignment method - forming the ζ north region and the train region, and laser annealing and heat treatment for the activation of the source region and the train region.
Please use optical means such as flashing, annealing, etc. to do this.
1. There is no adverse thermal effect on areas that are not irradiated with light, that is, areas that do not require heat treatment. As a result, the carrier concentration in the Child 61'J area was maintained stably, and no change in 1-1 occurred, and a compound semi-JJ7 body W with uniform ship properties was observed. It can be manufactured for a long time, and the conductivity of the gate electrode is extremely good.
第１図乃至第４図は本発明−・実施例を説明する為の１
稈カＪｊす「にノ３追ノと）丁導体装置（（、” ａ
Ａ ｓ−Ｍト〕ｊ−一 ｌ・’ ｌ−１’ Ｔ）の要部
切１１Ｊｔ １１！１血１ｊシ１−ζある。。
＋Ｘ＋に於いて、１は゛Ｉ′−ＩＩＱ縁１ノロ、’Ｊ
２３ΔＳ′！′導体基板、２は１１型チヤ、−トル領域
、；）はＷＳｉｙ、からなりゲ−！・１・ｈ極の・部を
な−Ｊ層、４はＴ ｉ Ｎからなイ】介在層、５はＡＩ
Ｊからなる低抵抗金属ｊ−３６はＡ７！Ｎからなるし・
−リ“光照射保護膜、７はソース・トレイン領域形成用
とＪ１アご〜−−ル部分被覆用とを兼ね人−マスク１１
叉、１）及び９はンリ三１゛／′・イオンを４１人し７
て形成１−た１１４型ソース領ｊ・１４及び丁）”型Ｉ
・し２イン１！自１八である。
件、〜許出１頭人 富十通株ｊ−（会社代哩人弁理
１ 玉轟 久五部
（り（３名）
第 τ 図
第２図
第３図
３２５−
第４図
４．１５Figures 1 to 4 are diagrams for explaining the present invention--examples.
Culm KaJjsu ``Nino 3 Oinoto''
There is a cut of the main part of A s-M t]j-1 l・'l-1' T). . In +X+, 1 is ゛I'-IIQ edge 1 noro, 'J
23ΔS′! ``The game consists of a conductive substrate, 2 is an 11-inch channel, -tor area, ;) is WSiy, and !・Part 1 of the h pole is the J layer, 4 is the intervening layer from TiN, and 5 is the AI layer.
Low resistance metal j-36 consisting of J is A7! It consists of N.
- Re-light irradiation protective film, 7 serves both for forming the source/train region and for covering the J1 jaw ~ - - mask 11
Fork, 1) and 9 have 41 people and 7
Formed 1-114 type source region J, 14 and D)” type I
・2 in 1! I am 18 years old. (3 persons) Figure 2 Figure 3 325- Figure 4 4.15
Claims (1)
イ１からなる屓と該１４Ｇ融点金属或いはそのシリサイ
ｊ・及び低抵抗金属のいずれにも密着性か良好である（
！ｌ：共に該１１肩３・１：熱金属等と該低抵抗金属と
の金属・ｌ：的反斤、を抑制し＋ｊｌる金属からなる介
在Ｙ−と低抵抗金属層とが順に積層されてなろチー１〜
電極を形成し、次に、該ケート電極をマスクとしソース
領域及びルイン領域を形成する為の不純物イオンの導入
をマ■ない、次に、光学的−１段に依り＋ｉｉｉ記不純
物イメンの／ｉＩｉ性化を行なってソース領域及び）・
レイン領域を形成′Ｊる］二稈か含まれてなることを特
徴とする化合物２１＜導体装置の製造方法。The channel region -1 has good adhesion to both the high melting point metal or its silicone 1 and the 14G melting point metal or its silicone and the low resistance metal (
! l: Together with the 11 shoulder 3, 1: Metal between the hot metal, etc. and the low resistance metal, l: An intervening Y- made of a metal that suppresses the reaction between the hot metal, etc. and the low resistance metal, and a low resistance metal layer are laminated in order. Narochi 1~
An electrode is formed, and then, using the gate electrode as a mask, impurity ions are introduced to form a source region and a Ruin region. Source area and)・
A method for manufacturing a conductor device, characterized in that the compound 21 contains two culms forming a rain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4482083A JPS59171171A (en) | 1983-03-17 | 1983-03-17 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4482083A JPS59171171A (en) | 1983-03-17 | 1983-03-17 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59171171A true JPS59171171A (en) | 1984-09-27 |
Family
ID=12702076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4482083A Pending JPS59171171A (en) | 1983-03-17 | 1983-03-17 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59171171A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61166080A (en) * | 1984-12-28 | 1986-07-26 | Fujitsu Ltd | Field-effect transistor and manufacture thereof |
| JPS6351679A (en) * | 1986-08-20 | 1988-03-04 | Nec Corp | Semicondictor device |
| JPS63142681A (en) * | 1986-12-04 | 1988-06-15 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of field-effect transistor |
| JPS6489469A (en) * | 1987-09-30 | 1989-04-03 | Mitsubishi Electric Corp | Field-effect transistor and manufacture thereof |
| US6255679B1 (en) | 1998-06-29 | 2001-07-03 | Nec Corporation | Field effect transistor which can operate stably in millimeter wave band |
-
1983
- 1983-03-17 JP JP4482083A patent/JPS59171171A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61166080A (en) * | 1984-12-28 | 1986-07-26 | Fujitsu Ltd | Field-effect transistor and manufacture thereof |
| JPS6351679A (en) * | 1986-08-20 | 1988-03-04 | Nec Corp | Semicondictor device |
| JPS63142681A (en) * | 1986-12-04 | 1988-06-15 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of field-effect transistor |
| JPS6489469A (en) * | 1987-09-30 | 1989-04-03 | Mitsubishi Electric Corp | Field-effect transistor and manufacture thereof |
| US6255679B1 (en) | 1998-06-29 | 2001-07-03 | Nec Corporation | Field effect transistor which can operate stably in millimeter wave band |
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