JPS59169179A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS59169179A JPS59169179A JP4219683A JP4219683A JPS59169179A JP S59169179 A JPS59169179 A JP S59169179A JP 4219683 A JP4219683 A JP 4219683A JP 4219683 A JP4219683 A JP 4219683A JP S59169179 A JPS59169179 A JP S59169179A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- gate electrode
- gate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 22
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 15
- 229910052710 silicon Inorganic materials 0.000 abstract description 15
- 239000010703 silicon Substances 0.000 abstract description 15
- 229920005591 polysilicon Polymers 0.000 abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 230000009257 reactivity Effects 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract description 2
- 238000013329 compounding Methods 0.000 abstract 1
- -1 phosphorus ions Chemical class 0.000 abstract 1
- 150000003481 tantalum Chemical class 0.000 abstract 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- MANYRMJQFFSZKJ-UHFFFAOYSA-N bis($l^{2}-silanylidene)tantalum Chemical class [Si]=[Ta]=[Si] MANYRMJQFFSZKJ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910000476 molybdenum oxide Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- PQQKPALAQIIWST-UHFFFAOYSA-N oxomolybdenum Chemical compound [Mo]=O PQQKPALAQIIWST-UHFFFAOYSA-N 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体集積回路装置に関し、特に半導体集積回
路装置を構成する絶縁ゲート型電界効果トランジスタの
ゲート電極およびゲート絶縁膜の構成に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device, and more particularly to the structure of a gate electrode and a gate insulating film of an insulated gate field effect transistor constituting a semiconductor integrated circuit device.
絶縁ゲート型電界効果トランジスタ（以下、ＭＩ ５Ｆ
ＥＴという）のゲート電極として、従来の多結晶シリコ
ン層に変えて、多結晶シリコン層とその上のモリブデン
シリサイド層からなる２層膜を用いることが知られてい
る。このようなＭＩＳＦＥＴによれば、従来のシリコン
ゲートＭＩＳＦＥＴの有する利点をそのまま保持でき、
その上配線抵抗の減少による高速化を達成することがで
きる。Insulated gate field effect transistor (hereinafter referred to as MI 5F)
It is known to use a two-layer film consisting of a polycrystalline silicon layer and a molybdenum silicide layer thereon, instead of the conventional polycrystalline silicon layer, as a gate electrode for an ET (ET). According to such a MISFET, the advantages of the conventional silicon gate MISFET can be maintained,
Furthermore, higher speeds can be achieved due to the reduction in wiring resistance.
しかし、モリブデンＭＯは活性エネルギが大きく反応性
に富んでいろため、素子の電気的特性が不安定になると
いう問題があることが、本発明者の検討によって明らか
になったっまた、モリブデンシリサイド層の抵抗は、多
結晶シリコン層の抵抗よりかなり少さいものの、さらに
高速化を計ろうとする時の妨げとなる。However, as molybdenum MO has a large active energy and is highly reactive, the inventor's studies have revealed that there is a problem that the electrical characteristics of the device become unstable. Although the resistance is much lower than that of the polycrystalline silicon layer, it becomes a hindrance when trying to achieve even higher speeds.
本発明の目的は、素子の高速化に適し、かつ安定なゲー
ト電極構造を有するＭＩＳＦＥＴからなる牛導体装百を
提供することにある。An object of the present invention is to provide a conductor device comprising a MISFET that is suitable for increasing the speed of the device and has a stable gate electrode structure.
本発明の前記ならびにその池の目的と新規な特徴は１本
明細書の記述および添付図面からあきらかになるであろ
う。The objects and novel features of the present invention and its pond will become apparent from the description of the present specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとお１つである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、ＭＩＳＦＥＴのゲー）！極をタンタルシリサ
イド（ＴａＳｉ２）層と多結晶シリコン層との２層構造
とし、ゲート絶縁膜を窒化シリコン（Ｓｉ３Ｎ４）膜と
酸化シリコン（Ｓ ＋ ０２ ）膜の２層構造とするこ
とによって、特性の安定なＭＩＳＦＥＴを構成し、あわ
せてその高速化を達成するものである。In other words, MISFET game)! By making the pole a two-layer structure of a tantalum silicide (TaSi2) layer and a polycrystalline silicon layer, and the gate insulating film a two-layer structure of a silicon nitride (Si3N4) film and a silicon oxide (S + 02) film, the characteristics can be improved. It constitutes a stable MISFET and also achieves high speed.
発明の実施例を第１図から第４図により説明する。 Embodiments of the invention will be described with reference to FIGS. 1 to 4.
第１図のように、ｐ型シリコン基板１表面の選択的な領
域に周知の選択酸化法で、フィールド酸化シリコン膜２
を形成し、更にアクティブ領域表面に薄いゲート酸化シ
リコン膜３を形成し、その上に例えばＣＶＤ法（化学的
気相成長技術）により薄い窒化シリコン膜４を形成する
う次に全面にポリシリコン膜５を、ＣＶＤ法で形成し、
しかる後リンなどの不純物な拡散して、そのポリシリコ
ン５を低抵抗体に化成する。次に例えば、スパッタリン
グ法により、全面にタンタルシリサイド膜６な形成する
。As shown in FIG. 1, a field silicon oxide film 2 is formed on selective regions of the surface of a p-type silicon substrate 1 using a well-known selective oxidation method.
A thin gate silicon oxide film 3 is formed on the surface of the active region, a thin silicon nitride film 4 is formed thereon by, for example, CVD (chemical vapor deposition technology), and then a polysilicon film is formed on the entire surface. 5 is formed by CVD method,
Thereafter, an impurity such as phosphorus is diffused to form the polysilicon 5 into a low resistance material. Next, a tantalum silicide film 6 is formed on the entire surface by, for example, sputtering.
そして第２図のように、ホトリソグラフィを用いて、上
記のタンタルシリサイド、ポリシリコン、窒化シリコン
膜を順次エツチングし、ゲート電極パターンおよび必要
に応じて配線ノくターンを形成する。次に全面にヒ素、
リン等の不純物なイオン打込みし、シリコン基板ノ・１
表面のアクティブ領域で、かつゲート電極におおわれて
いない部分にイオン打込層１４を形成するう
ついで第３図のように、全面に層間絶縁膜、例えばＣＶ
Ｄ法によるリンシリケートガラス膜（ＰＳＧ膜）７を形
成するう続いて熱処理を行ない、前記イオン打込みされ
た不純物を活性化し、Ｎ 型ソース層８およびドレイン
層９を形成する。Then, as shown in FIG. 2, the tantalum silicide, polysilicon, and silicon nitride films are sequentially etched using photolithography to form a gate electrode pattern and, if necessary, a wiring turn. Next, arsenic all over the surface.
Impurity ions such as phosphorus are implanted into the silicon substrate.
After forming the ion implantation layer 14 in the active region of the surface and the part not covered with the gate electrode, as shown in FIG.
After forming a phosphosilicate glass film (PSG film) 7 by method D, heat treatment is performed to activate the ion-implanted impurities and form an N-type source layer 8 and a drain layer 9.
次いで第４図のように、ホトリングラフィにより、ソー
ス及びドレインに、コンタクト穴１０゜１１及び多層配
線用のコンタクト穴１２を設ける。Next, as shown in FIG. 4, contact holes 10.degree. 11 and contact holes 12 for multilayer wiring are formed in the source and drain by photolithography.
そして次に全面に、例えばスパッタリング法により、ア
ルミニウム膜を形成し、ホトリソグラフィにより、各々
の電極パターン１３ａ、１３ｂ、１３ｃを形成する。Then, an aluminum film is formed on the entire surface by, for example, sputtering, and each electrode pattern 13a, 13b, 13c is formed by photolithography.
以上のようにして形成したＭＩＳＦＥＴは、ゲ−）ｔｌ
ｉｌの上層６として、モリブデンシリサイドに代えて、
タンタルシリサイドを用いているため電気的に安定な特
性が得られるうすなわち、モリブデンは活性で反応性に
冨むため、ゲート電極を形成した後も安定でない。また
、モリブデンの酸化物は非常に不安定である（昇華性で
ある）ため、製造工程上安定なゲート電極が得にくいっ
これに対して、タンタルは反応性が小さく、またその酸
化物も非常に安定な物質であるため、非常に安定なゲー
ト電極が容易に得られるう
また、タンタルはモリブデンに比べて抵抗値が／１１さ
いため、ゲート配線の抵抗をより一層小さくできる。タ
ンタルシリサイド層に含有されるシリコンの量にもよる
が、モリブデンシリサイド層を用いた場合の約１／２に
ゲート配線の抵抗を小さくできる。The MISFET formed as described above is
As the upper layer 6 of il, instead of molybdenum silicide,
Since tantalum silicide is used, electrically stable characteristics are obtained; in other words, since molybdenum is active and highly reactive, it is not stable even after the gate electrode is formed. Additionally, since molybdenum oxide is extremely unstable (sublimable), it is difficult to obtain a stable gate electrode during the manufacturing process, whereas tantalum has low reactivity and its oxide is also extremely difficult to obtain. Since tantalum is a stable substance, it is easy to obtain a very stable gate electrode, and since tantalum has a resistance value of 11 times lower than that of molybdenum, the resistance of the gate wiring can be further reduced. Although it depends on the amount of silicon contained in the tantalum silicide layer, the resistance of the gate wiring can be reduced to about 1/2 of that when a molybdenum silicide layer is used.
一方、電極材料としてタンタルＴａを用いた場合の特有
の問題を、ゲート絶縁膜に窒化シリコン膜な用いること
で解決しているっ
すなわち１本発明者の検討によれば、前述したイオン打
込層１４な活性化するために行うアニールの際に、タン
タルが多結晶シリコン層中を拡散してゲート絶縁膜に達
し、このゲート絶縁膜が５ｉｎ２膜から成る場合その破
壊耐圧な劣化させることがわかった。さらに、この原因
は、タンタルが５ｉＯｚを環元１〜る性質な持っている
ため、ゲート５Ｉ０２膜が環元されてしまうことにある
ことがわかった。On the other hand, the problems peculiar to the use of tantalum Ta as an electrode material have been solved by using a silicon nitride film for the gate insulating film. It was found that during annealing to activate the 14-layer structure, tantalum diffuses through the polycrystalline silicon layer and reaches the gate insulating film, which deteriorates the breakdown voltage when the gate insulating film is made of a 5in2 film. . Furthermore, it has been found that the cause of this is that tantalum has a property of containing 5iOz as a ring element, so that the gate 5I02 film becomes ring element.
このよりなタンタルによる不良の原因な除くため酸化シ
リコン膜より重金属の拡散防止能力の高い窒化シリコン
膜を形成してメンタルが拡散により、酸化シリコン膜に
到達するのを阻止する一方、窒化シリコン膜よりシリコ
ン基板に対して接着性のよい酸化シリコン膜な形成して
界面の安定化を計っているつ
〔効果〕
（１） 反応性の少ない安定なタンタルシリサイドを
ゲー）！極の一部として用いているため、電気的に安定
な素子が得られる。In order to eliminate the cause of defects caused by tantalum, we form a silicon nitride film that has a higher ability to prevent heavy metal diffusion than a silicon oxide film, and prevents metal from reaching the silicon oxide film due to diffusion. A silicon oxide film with good adhesion to the silicon substrate is formed to stabilize the interface. (1) Stable tantalum silicide with low reactivity is used! Since it is used as part of the pole, an electrically stable element can be obtained.
（２）ゲート絶縁膜として、酸化シリコン膜の上にこれ
よりも安定で本金属の拡散防止能力の高い窒化シリコン
膜を形成しているため、ゲート電極としてタンタルシリ
サイドを用いても、高温熱処理によって上記ゲート材料
中のタンタルが酸化シリコン膜に拡散するのを防ぐこと
ができ、それによってゲート耐圧が劣化するのを防ぐこ
とができろ。(2) As the gate insulating film, a silicon nitride film is formed on top of the silicon oxide film, which is more stable and has a higher ability to prevent the diffusion of this metal, so even if tantalum silicide is used as the gate electrode, it can be removed by high-temperature heat treatment. It is possible to prevent the tantalum in the gate material from diffusing into the silicon oxide film, thereby preventing the gate breakdown voltage from deteriorating.
（３）ゲート電極を上層にタンタルシリサイド層、下層
にポリシリコン層の２層構造としているため、ゲート電
極とゲート絶縁膜との界面が劣化しない。(3) Since the gate electrode has a two-layer structure of the tantalum silicide layer as the upper layer and the polysilicon layer as the lower layer, the interface between the gate electrode and the gate insulating film does not deteriorate.
（４） ゲート絶縁膜を上層に電化シリコン膜、下層
に酸化シリコン膜の２層構造としているため、シリコン
基板と絶縁膜との界面が安定である。(4) Since the gate insulating film has a two-layer structure of an electrified silicon film as an upper layer and a silicon oxide film as a lower layer, the interface between the silicon substrate and the insulating film is stable.
（５１ゲート電極材料としてモリブデンな用いた場合よ
りもさらに高速化が可能である。(51) The speed can be further increased than when molybdenum is used as the gate electrode material.
以上発明者によってなされた発明を実施例にもとづき具
体的に説明したが、本発明は上記実施例に限定されるも
ので１工なく、その要旨を逸脱しない範囲で柚々変更可
能であることはいうまでもな（・０たとえば、タンタル
シリサイド層に代えてタンタル層を用いることも可能で
ある。Although the invention made by the inventor has been specifically explained based on the examples above, the present invention is not limited to the above-mentioned examples and can be modified without departing from the gist thereof. Needless to say (.0) For example, it is also possible to use a tantalum layer instead of the tantalum silicide layer.
第１図、第２図、第３図及び第４図は１本発明による牛
導体集積回路装置をその製造工程順に示す各断面図であ
る。
１・・・ｐ型シリコンウェハ、２・・フィールド酸化膜
、３・・・ゲート酸化シリコン、４・・・窒化シリコン
、５・・・ポリシリコン、６・・・タンタルシリサイド
、７・・・リンシリケートガラス膜、８・・・ソース層
、９・・・ドレイン層、１０・・・ソース上コンタクト
穴、１１・・・トンイン上コンタクト穴、１２・・・多
配線用コンタクト穴、１３ａ＋１３ｂ、１３ｃ・・・ア
ルミニウムｔｍ。1, 2, 3, and 4 are cross-sectional views showing a conductor integrated circuit device according to the present invention in the order of its manufacturing process. DESCRIPTION OF SYMBOLS 1... P-type silicon wafer, 2... Field oxide film, 3... Gate oxide silicon, 4... Silicon nitride, 5... Polysilicon, 6... Tantalum silicide, 7... Phosphorus Silicate glass film, 8... Source layer, 9... Drain layer, 10... Source upper contact hole, 11... Ton-in upper contact hole, 12... Multi-wiring contact hole, 13a+13b, 13c. ...Aluminum TM.
Claims (1)
リコン膜およびその上に形成された窒化シリコン膜とか
らなるゲート絶縁膜と、このゲート絶縁膜上に形成され
た多結晶シリコン層およびその上に形成されたタンタル
シリサイド層とからなるゲート電極とを有する絶縁ゲー
ト型電界効果トランジスタからなることを特徴とする半
導体集積回路装置。1. A semiconductor substrate, a gate insulating film consisting of a silicon oxide film formed on the surface of this substrate and a silicon nitride film formed thereon, a polycrystalline silicon layer formed on this gate insulating film, and its 1. A semiconductor integrated circuit device comprising an insulated gate field effect transistor having a gate electrode comprising a tantalum silicide layer formed thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4219683A JPS59169179A (en) | 1983-03-16 | 1983-03-16 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4219683A JPS59169179A (en) | 1983-03-16 | 1983-03-16 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59169179A true JPS59169179A (en) | 1984-09-25 |
Family
ID=12629250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4219683A Pending JPS59169179A (en) | 1983-03-16 | 1983-03-16 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59169179A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6290973A (en) * | 1985-06-25 | 1987-04-25 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS63221647A (en) * | 1987-03-10 | 1988-09-14 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| US5280190A (en) * | 1991-03-21 | 1994-01-18 | Industrial Technology Research Institute | Self aligned emitter/runner integrated circuit |
| US7099487B2 (en) | 2001-02-02 | 2006-08-29 | Temco Japan Co., Ltd. | Microphone with arm |
-
1983
- 1983-03-16 JP JP4219683A patent/JPS59169179A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6290973A (en) * | 1985-06-25 | 1987-04-25 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS63221647A (en) * | 1987-03-10 | 1988-09-14 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| US5280190A (en) * | 1991-03-21 | 1994-01-18 | Industrial Technology Research Institute | Self aligned emitter/runner integrated circuit |
| US7099487B2 (en) | 2001-02-02 | 2006-08-29 | Temco Japan Co., Ltd. | Microphone with arm |
| KR100840857B1 (en) * | 2001-02-02 | 2008-06-23 | 가부시기가이샤 템코 재팬 | Microphone with arm |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0523055B2 (en) | ||
| JPS59169179A (en) | Semiconductor integrated circuit device | |
| JPS62298161A (en) | Manufacture of semiconductor integrated circuit device | |
| JPH1064898A (en) | Manufacturing method of semiconductor device | |
| JPS61150376A (en) | Semiconductor device | |
| JPS6028141B2 (en) | Manufacturing method for semiconductor devices | |
| JPS59208772A (en) | Manufacture of semiconductor device | |
| JPH0431193B2 (en) | ||
| JP2511852B2 (en) | Method for manufacturing semiconductor device | |
| JPH0217930B2 (en) | ||
| JPH01298758A (en) | Manufacture of semiconductor device | |
| JPS59231863A (en) | Insulated gate semiconductor device and manufacture thereof | |
| JPH0466108B2 (en) | ||
| JP2705583B2 (en) | Method for manufacturing semiconductor device | |
| JPS61251164A (en) | Manufacture of bi-mis integrated circuit | |
| JPH02194653A (en) | Mis transistor | |
| JPS60133759A (en) | Manufacture of semiconductor device | |
| JPH02218164A (en) | Mis type field-effect transistor | |
| JPS6148778B2 (en) | ||
| JPS60195972A (en) | Manufacture of semiconductor device | |
| JPS60193330A (en) | Method for diffusing impurities into semiconductor | |
| JPS5933825A (en) | Manufacture of semiconductor device | |
| JPS6254959A (en) | Manufacture of mis semiconductor device | |
| JPH03204968A (en) | Semiconductor device and manufacture thereof | |
| JPH0697276A (en) | Manufacture of semiconductor device |