JPS59168657A - Manufacture of hybrid integrated circuit device - Google Patents
Manufacture of hybrid integrated circuit deviceInfo
- Publication number
- JPS59168657A JPS59168657A JP4256183A JP4256183A JPS59168657A JP S59168657 A JPS59168657 A JP S59168657A JP 4256183 A JP4256183 A JP 4256183A JP 4256183 A JP4256183 A JP 4256183A JP S59168657 A JPS59168657 A JP S59168657A
- Authority
- JP
- Japan
- Prior art keywords
- base board
- hardened
- resin
- integrated circuit
- adhesive resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000004840 adhesive resin Substances 0.000 claims abstract description 9
- 229920006223 adhesive resin Polymers 0.000 claims abstract description 9
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 239000011347 resin Substances 0.000 claims abstract description 8
- 238000000576 coating method Methods 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 3
- 239000004593 Epoxy Substances 0.000 abstract description 2
- 230000006355 external stress Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 238000007789 sealing Methods 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 229920002050 silicone resin Polymers 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 235000014121 butter Nutrition 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3405—Edge mounted components, e.g. terminals
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は混成集積回路装置の製造方法に関する。[Detailed description of the invention] The present invention relates to a method of manufacturing a hybrid integrated circuit device.
混成集積回路装置の製造方法は該装置にを求される各固
有の条件によシ種々の方法が採用されている。たとえば
（１）レーザースクライプによる基板分割、（２）チ
ップ状等個別部品の搭載接続、（３）該部品の接続部保
護の為の樹脂塗布・硬化、（４１外部リード接続、（５
）外装樹脂の塗布−硬化の組合せにより製造される。本
発明はこのような混成集積回路の製造方法に関する。Various methods are employed for manufacturing hybrid integrated circuit devices depending on the unique conditions required for the device. For example, (1) dividing the board by laser scribing, (2) mounting and connecting individual parts such as chips, (3) applying and curing resin to protect the connection parts of the parts, (41 external lead connection, (5)
) Manufactured by a combination of coating and curing of exterior resin. The present invention relates to a method of manufacturing such a hybrid integrated circuit.
以下従来の技術について図面によシ説明する。The conventional technology will be explained below with reference to the drawings.
従来の技術によれは第１図（ａｌに示す如く混成集積回
路用基板１（以下基板１と称す）上にレーザースクライ
ビング法によシスクライブ溝を形成した後スナツピング
によシ基板分割を行い、所定の基板外形寸法を得る。そ
の後、第１図（ｂｌに示す如く基板１の所定の位置にチ
ップ状等の個別部品を搭載した後ワイヤボンディング法
等によシ相互接続を行った後、該接続部分の保護の為シ
リコン系樹脂３を塗布・硬化する。さらに外部接続用リ
ード４を基板１の所定の位置に配置、リードフレームボ
ンディング等によシ接続した後第１図（ｃｌに示す如く
外装用シリコン系樹脂５をフローコート法等によシ塗布
・硬化させる。前８ピ従来技術によれば第１図（ｄｉに
示す如く基板ｌのスナツピング後のスクライプライ／側
稜部にはレーザー光源としてＹＡＧを用いた場合、再凝
固部２（以下バリ２と称す。）が形成されておシ、外装
用シリコン系樹脂５を塗布しても本混成集積回路装置を
プリント配線板に実装する際等の取扱い時に該装置端面
を接触させた場合バリ２が該装置よシ分離され、プリン
ト配線板及び周辺の個別部品等上に飛赦し、個別部品の
性格上ホコリ等に敏感である場合は該装置を実装して構
成されるシステムに悪影響を及はす。又、該装置端面に
ビンセット等の工具によシ局部的に接触された場合核装
置端面の綾部セラミックが欠け、甚しい場合は近傍の配
線パターンが欠損するといった重大なる品質低下を伴う
恐れが充分存在していた。According to the conventional technology, as shown in FIG. After that, as shown in FIG. A silicone resin 3 is applied and cured to protect the parts.Furthermore, external connection leads 4 are placed at predetermined positions on the board 1, and after connection by lead frame bonding etc. A silicone-based resin 5 is applied and cured by a flow coating method or the like.According to the prior art, as shown in FIG. When YAG is used, re-solidified portions 2 (hereinafter referred to as burrs 2) are formed, and even when the exterior silicone resin 5 is applied, it is difficult to mount this hybrid integrated circuit device on a printed wiring board, etc. If the end face of the device comes into contact with the device during handling, burrs 2 will separate from the device and fly onto printed wiring boards and surrounding individual parts, etc., and if the individual parts are sensitive to dust etc. due to their nature, the device may be damaged. In addition, if the end face of the device is locally touched by a tool such as a bottle set, the ceramic ridge on the end face of the nuclear device may be chipped, and in severe cases, damage to the surrounding area may be caused. There was a strong possibility that this would lead to serious quality deterioration, such as loss of wiring patterns.
本発明の目的は配線パターン欠損のない安定した品質の
混成集積回路装置を提供することにある。An object of the present invention is to provide a hybrid integrated circuit device with stable quality and no wiring pattern defects.
本発明の％徴は、部品搭載及び外部リード接続終了後基
板のパターン面上にその外周に沿って接着性樹脂を印刷
法によシ矩形枠状に塗布・硬化させ、しかる後外装用樹
脂を塗布・硬化させる混成集積回路装置の製造方法にあ
る。The characteristic of the present invention is that after mounting components and connecting external leads, adhesive resin is applied and cured in a rectangular frame shape along the outer periphery on the patterned surface of the board by a printing method, and then the exterior resin is applied. The present invention relates to a method of manufacturing a hybrid integrated circuit device by coating and curing.
本発明の実施例による混成集積回路装置について図面に
より説明すると、第２図（，１１に示す如く基板１上に
レーザースクライビング法によりスクライプ溝を形成し
た後スナツピングにょシ基板分割を行い、その後第２図
（１＞１に示す如く基板Ｉの所定の位置にチップ状等の
個別部品を搭載した後、ワイヤボンディング法等によシ
相互接続を行った後、該接続部分の保財！の為、シリコ
ン系樹脂３を塗布・硬化させる。さらに外部接続用リー
ドを基板１の所定の位置に配置、リードフレームボンデ
ィング法によシ接続する。しかる後基板のパターン面上
にその外周に沿ってエポキシ糸等の接着性樹脂発明方法
によると基板端稜部のバリ２は第２図（ｄｉに示す如く
接着性樹脂６にょシ固定され、外部応力による飛散を防
止することが出来、又、接着性樹脂６により基板端稜部
自体が補強されることがら該稜部のセラミック欠けや近
傍の配線バター／欠損等の発生を防止することが可能と
なる。さらに接着性樹脂６が基板ｌの外周に沿って矩形
枠状に印刷されることから、外部接続用リードの基板１
（Ｉｌｌでの接続部の補強を兼ねることにより該接続
部が直接、外部応力にさらされることなく接続強度の向
上をも合せて実現可能となるものである。A hybrid integrated circuit device according to an embodiment of the present invention will be explained with reference to the drawings. As shown in FIG. As shown in Figure (1>1), after mounting individual parts such as chips at predetermined positions on the board I and interconnecting them by wire bonding, etc., in order to preserve the properties of the connected parts, A silicone resin 3 is applied and cured.Furthermore, external connection leads are placed at predetermined positions on the substrate 1 and connected using the lead frame bonding method.After that, an epoxy thread is placed on the patterned surface of the substrate along its outer periphery. According to the adhesive resin invented method, the burr 2 on the edge of the substrate is fixed to the adhesive resin 6 as shown in FIG. Since the edge of the board 6 is reinforced, it is possible to prevent the occurrence of ceramic chipping at the ridge and wiring butter/defects in the vicinity.Furthermore, the adhesive resin 6 is applied along the outer periphery of the board l. Because it is printed in a rectangular frame shape, the board 1 of the external connection lead
(By also reinforcing the connection portion at Ill, the connection portion is not directly exposed to external stress, and the connection strength can also be improved.
第１図（ａ） 、 （ｂ） 、 ｒｃ） 、 （ｄ）は
従来の技術による＆ｆｆｉ方法を示す拡大断面図、第２
図（ａｌ 、 （ｂ） 、 （Ｃ１、（ｄｉは本発明に
よる製造方法を示す拡大断面図である。
尚、図において、１・・・・・・基板、２・・・・・・
バ１ハ３・・・・・・シリコン系樹脂、４・・・・・・
外部接続用リード、５・・・・・・外装用シリコン系樹
脂、６・・・・・・接着性樹脂である。
（Ｃ）
（θう
乙
（Ｃ〕
叢 ２図Figures 1 (a), (b), rc), and (d) are enlarged cross-sectional views showing the conventional &ffi method;
Figures (al, (b), (C1, (di) are enlarged sectional views showing the manufacturing method according to the present invention. In the figures, 1...substrate, 2...
B1 H3... Silicone resin, 4...
Lead for external connection, 5...Silicone resin for exterior, 6...Adhesive resin. (C) (θUotsu (C) Fig. 2
Claims (1)
にその外周に沿って接着性樹脂を印刷法によシ矩形枠状
に塗布、硬化させ、しかる後外装用樹脂を塗布・硬化さ
せることを特徴とする混成集積回路装置の製造方法。After mounting the components and connecting external leads, adhesive resin is applied onto the patterned surface of the board along its outer periphery in a rectangular frame shape using a printing method and cured, and then exterior resin is applied and cured. A method for manufacturing a hybrid integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4256183A JPS59168657A (en) | 1983-03-15 | 1983-03-15 | Manufacture of hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4256183A JPS59168657A (en) | 1983-03-15 | 1983-03-15 | Manufacture of hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59168657A true JPS59168657A (en) | 1984-09-22 |
Family
ID=12639454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4256183A Pending JPS59168657A (en) | 1983-03-15 | 1983-03-15 | Manufacture of hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59168657A (en) |
-
1983
- 1983-03-15 JP JP4256183A patent/JPS59168657A/en active Pending
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