JPS59161149A - Timing synchronizing circuit - Google Patents

Timing synchronizing circuit

Info

Publication number
JPS59161149A
JPS59161149A JP58035348A JP3534883A JPS59161149A JP S59161149 A JPS59161149 A JP S59161149A JP 58035348 A JP58035348 A JP 58035348A JP 3534883 A JP3534883 A JP 3534883A JP S59161149 A JPS59161149 A JP S59161149A
Authority
JP
Japan
Prior art keywords
signal
circuit
output
converter
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58035348A
Other languages
Japanese (ja)
Other versions
JPH0223106B2 (en
Inventor
Yasutsune Yoshida
吉田　「やす」玄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58035348A priority Critical patent/JPS59161149A/en
Priority to CA000448593A priority patent/CA1208311A/en
Priority to DE8484102234T priority patent/DE3485782T2/en
Priority to AU25228/84A priority patent/AU556574B2/en
Priority to US06/585,653 priority patent/US4528512A/en
Priority to EP84102234A priority patent/EP0118119B1/en
Publication of JPS59161149A publication Critical patent/JPS59161149A/en
Publication of JPH0223106B2 publication Critical patent/JPH0223106B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
    • H04L7/0335—Gardner detector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To always hold an optimum timing by supplying the output of a logical circuit as the control signal of a voltage controlled oscillator through an LPF. CONSTITUTION:A discriminating circuit 10 discriminates waveforms m1-m4, and a signal G goes to ''1'' in case of m1-m2. Also, an inversion G goes to ''1'' in case when the waveforms are m3-m4. On the other hand, a logical circuit 9 has a circuit for inverting the polarity of a signal X2 in case when the signal inversion G is ''1'', and also holding the nearest past signal X2 by one of the waveforms m1-m4 in case when the signal G and the inversion G are both zero, and by an output of the circuit 9, an error signal APC for detecting shift of a sampling point by an A/D converter 11 is obtained. Accordingly, when the output of the circuit 9 is supplied as a control signal of a voltage controlled oscillator 5 through an LPF6, a timing signal is always supplied to the converter 11 by an optimum timing.

Description

【発明の詳細な説明】 本発明は帯域制限をうけたベースバンド信号よりタイミ
ング信号を再生するタイミング同期回路に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing synchronization circuit that reproduces a timing signal from a band-limited baseband signal.

デジタル搬送波伝送方式に用いられる復調装置において
、復調された信号をデジタル信号に変換するためにはタ
イミング信号が必要となる。このタイミング信号を再生
する手段として従来種々使われてきたが、その１つとし
て第１図に示される如きのものがある。１は位相検波器
、２は全波整流回路、３は位相同期回路、４は位相比較
器、５は電圧制御発振器、６は低域ろ波器、７は位相シ
フタ、８は１ビツトＡ／Ｄコンバータである。第１図は
変調波が２′ＭＩＰＳＫ波の場合であり、以下動作を説
明する。入力Ｐ　Ｓ　Ｋ信号は位相検波器１で基準搬送
波によ抄復調され、２値のベースバンド信号になる。復
調ベースバンド信号は全波整流回路２に供給され、ここ
で２逓倍され、タイミング信号が抽出される。この抽出
信号は次に通常の位相同期回路３に供給される。この位
相同期回路３において、入力抽出タイミング信号に位相
同期し且つ、狭帯域で帯域制限されたジッタ成分の少な
い再生タイミング信号が得られる。回路３の出力は位相
シフタ７を介してＡ／Ｄ　（アナログ／デジタル）コン
バータ８に入力され、復調ベースバンド信号をサンプリ
ング整形するためのタイミング信号として使用される。In a demodulator used in a digital carrier wave transmission system, a timing signal is required to convert a demodulated signal into a digital signal. Various means have been used to reproduce this timing signal, one of which is shown in FIG. 1 is a phase detector, 2 is a full-wave rectifier circuit, 3 is a phase locked circuit, 4 is a phase comparator, 5 is a voltage controlled oscillator, 6 is a low-pass filter, 7 is a phase shifter, 8 is a 1-bit A/ It is a D converter. FIG. 1 shows a case where the modulated wave is a 2' MIPSK wave, and the operation will be explained below. The input PSK signal is demodulated by a reference carrier wave in a phase detector 1, and becomes a binary baseband signal. The demodulated baseband signal is supplied to a full-wave rectifier circuit 2, where it is doubled and a timing signal is extracted. This extracted signal is then supplied to a conventional phase locked circuit 3. In this phase synchronization circuit 3, a reproduced timing signal with few jitter components which is phase synchronized with the input extraction timing signal and whose band is limited in a narrow band is obtained. The output of the circuit 3 is input to an A/D (analog/digital) converter 8 via a phase shifter 7, and is used as a timing signal for sampling and shaping the demodulated baseband signal.

この時、復調ベースバンド信号が最適タイミングでサン
プリングされるように、位相シフタ７にて位相調整する
必要がある。このようガ回路においても、ジッタ成分の
少ないタイミング信号を再生できるが、位相調整をしな
ければならないという欠点があった。At this time, it is necessary to adjust the phase using the phase shifter 7 so that the demodulated baseband signal is sampled at the optimum timing. Although such a circuit can also reproduce a timing signal with less jitter components, it has the disadvantage that phase adjustment must be performed.

本発明の目的は、ジッタ成分の少ない再生タイミング信
号を得ることができ、且つ位相調整が不要で、常に最適
タイミングに保つことができるタイミング同期回路を提
供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a timing synchronization circuit that can obtain a reproduction timing signal with less jitter components, does not require phase adjustment, and can always maintain optimal timing.

以下、図面を用いて詳細に説明する。Hereinafter, a detailed explanation will be given using the drawings.

第２図は本発明の実施例で、９は論理回路、１０は判別
回路、１１は２ピツ）Ａ／Ｄコンバータ。FIG. 2 shows an embodiment of the present invention, where 9 is a logic circuit, 10 is a discrimination circuit, and 11 is a 2-pin A/D converter.

又は、第３図は第２図の回路の説明図である。Alternatively, FIG. 3 is an explanatory diagram of the circuit of FIG. 2.

以下、動作を説明する。位相検波器１の出力の復調ベー
スバンド信号は何らかの帯域制限をうけたものとし、第
３図（ａ）におけるｍ１〜ｍ４で示される如き波形を含
むものとする。このような復調ベースバンド信号はＡ／
Ｄコンバータ１１にてサンプリングされ、第３図（ａ）
の基準レベルＬｌ　、　Ｌ２およびＬ３によりデータ信
号ＸＩ、Ｘ２に変換される。仁の復調ベースバンド信号
ｍとデータＸＩ。The operation will be explained below. It is assumed that the demodulated baseband signal output from the phase detector 1 is subjected to some kind of band restriction and includes waveforms as shown by m1 to m4 in FIG. 3(a). Such a demodulated baseband signal is A/
Sampled by the D converter 11, as shown in Fig. 3(a).
are converted into data signals XI, X2 by reference levels Ll, L2 and L3. Jin's demodulated baseband signal m and data XI.

Ｘ２との関係は第１表のようになる。The relationship with X2 is as shown in Table 1.

第１表 第３図（ｂ）におけるＴ−１，Ｔｏ、ＴＩは３タイムス
ロット間における最適サンプリング点を表わしており、
今、信号ｍ１〜ｍ４がサンプリング点Ｔ−１〜Ｔ１でサ
ンプリングされれば復調ベースバンド信号の位置（Ａ　
１＊ａ−１１ＢＯ＠ｂｏ、ＣＩＩＣＩ）を判別している
データ信号Ｘ２はＩｌｌあるいは１０１が等確率で出力
されるが、今、十Δｔあるいは一Δｔのタイミングでサ
ンプリングされ死時データ信号Ｘ２の出力は第２表の如
くになる。T-1, To, and TI in Table 1, Figure 3(b) represent the optimal sampling points between the three time slots,
Now, if signals m1 to m4 are sampled at sampling points T-1 to T1, the position of the demodulated baseband signal (A
The data signal X2 that discriminates 1*a-11BO@bo, CIICI) is output with equal probability of Ill or 101, but now it is sampled at the timing of 10 Δt or 1 Δt and the death data signal X2 is output. is as shown in Table 2.

第２表 第２表より、出力Ｘ２において波形ｍ１〜ｍ２即ち点Ｔ
Ｏでの微係数の極性が正である復調ベースバンド信号の
場合、サンプリング点が＋Δｔになった時常に１、反対
に−Δｔになった時、常に０となる。一方、波形ｍ３〜
ｍ４即ち点Ｔｏでの微係数の極性が負である復調ベース
バンド信号の場合には、ｍ１〜ｍ２と逆極性の出力Ｘ２
を得ることができるので、出力Ｘ２の極性を逆にしてや
ればｍ３〜ｍ４の場合と同じとなる。このように復調５
− ベースバンド信号の点Ｔｏでの微係数の極性を判別し、
その結果でＸ２を論理操作すれば、その出力はサンプリ
ング点のずれを検出する誤差信号となり得る。第２図に
おいて判別回路１０は波形ｍ１〜ｍ４を判別するもので
、信号Ｇはｍ　ｌ　−ｍ　２の場合１となる。又信号Ｇ
は波形ｍ３〜ｍ４の場合１となる。論理回路９は信号Ｘ
２を信号Ｇが１の場合極性反転させ、且つ信号Ｇ及び任
が共に００場合は波形ｍ１〜ｍ４のうちいずれかで且つ
一番近い過去の信号Ｘ’２を保持する回路を有するもの
であり、論理回路９の出力でＡ／Ｄコンバータ１１での
サンプリング点ずれを検出する誤差信号ＡＰＣが得られ
る。よりて回路９の出力を低域ろ波器６を介して電圧制
御発振器５０制御信号として供給してやれば、第２図の
回路はＡ／Ｄコンバータ１１に常に最適タイミングでタ
イミング信号が供給されるように動作する。Table 2 From Table 2, at output X2, waveforms m1 to m2, that is, point T
In the case of a demodulated baseband signal in which the polarity of the differential coefficient at O is positive, it is always 1 when the sampling point reaches +Δt, and always 0 when the sampling point becomes −Δt. On the other hand, waveform m3~
In the case of a demodulated baseband signal where the polarity of the differential coefficient at point To is negative, the output X2 has the opposite polarity to m1 to m2.
can be obtained, so if the polarity of the output X2 is reversed, it will be the same as in the case of m3 to m4. In this way demodulation 5
- determine the polarity of the differential coefficient at point To of the baseband signal;
If X2 is logically operated on the result, the output can become an error signal for detecting the deviation of the sampling point. In FIG. 2, a discrimination circuit 10 discriminates waveforms m1 to m4, and the signal G becomes 1 when m l -m2. Also signal G
is 1 for waveforms m3 to m4. Logic circuit 9 receives signal
2, when the signal G is 1, the polarity is inverted, and when both the signal G and the signal G are 00, the circuit holds one of the waveforms m1 to m4 and the closest past signal X'2. , an error signal APC for detecting a sampling point shift in the A/D converter 11 is obtained from the output of the logic circuit 9. Therefore, if the output of the circuit 9 is supplied as a control signal to the voltage controlled oscillator 50 via the low-pass filter 6, the circuit shown in FIG. works.

第４図は、論理回路９および判定回路１０の具体的な実
施例で、１２〜１６．２４はＤタイプフリップフロップ
、１７は振幅比較器、１８はＯＲ６一 ／Ｎ０１１ゲート、１９．２０はＯＲゲート、２１〜２
３はＡＮＤゲートである。フリップフロップ１２〜１４
は３ビツトのメモリーとして動作し、フリップフロップ
１２及び１４の出力Ｙｌ、Ｙ−１が振幅比較器１７に入
力される。振幅比較器１７はコンバータにおいて、サン
プリング点ＴＯでの復調ベースバンド信号の微係数の極
性を判別するもので、点Ｔ−１とＴＩでのデータ比較に
よって判定している。即ち、０から１の変化の時は微係
数の極性は正とし、１からＯの変化の時はその逆となる
。振幅比較器１７の出力として、Ｇ、Ｇが出力され、波
形ｍ１〜ｍ２の時Ｇが１、又ｍ３〜ｍ４の時Ｇが１とな
る。ゲート２０〜２２は信号Ｇが１の場合Ｘ２をそのま
ま出力し、右信号が１の場合にはＸ２を極性反転させ出
力するように動作する。又、ＡＮＤゲート２３出力には
信号Ｇ。FIG. 4 shows a concrete example of the logic circuit 9 and the judgment circuit 10, in which 12 to 16.24 are D-type flip-flops, 17 is an amplitude comparator, 18 is an OR6-/N011 gate, and 19.20 is an OR Gate, 21-2
3 is an AND gate. flip flop 12~14
operates as a 3-bit memory, and outputs Y1 and Y-1 of flip-flops 12 and 14 are input to an amplitude comparator 17. The amplitude comparator 17 in the converter determines the polarity of the differential coefficient of the demodulated baseband signal at the sampling point TO, and this determination is made by comparing data at points T-1 and TI. That is, the polarity of the differential coefficient is positive when changing from 0 to 1, and vice versa when changing from 1 to O. G and G are output as the output of the amplitude comparator 17, and G is 1 when the waveforms are m1 to m2, and G is 1 when the waveforms are m3 to m4. The gates 20 to 22 operate to output X2 as is when the signal G is 1, and to invert the polarity of X2 and output it when the right signal is 1. Also, the signal G is output to the AND gate 23.

てのどちらか一方が１の場合タイミング信号を送出し、
信号Ｇ、ｎがともに０の時には出力をＯとするように動
作する。よってフリップフロップ２４の出力には波形ｍ
１〜ｍ４の場合には、ＯＲゲート２０の出力をそのまま
出力し、ｍｌ〜ｍ４以外の場合には、現時点から１番近
い過去のｍ１〜ｍ４波形のいずれかの時のＸ２信号を保
持するように動作する。If either one of them is 1, a timing signal is sent,
When both signals G and n are 0, the output is set to 0. Therefore, the output of the flip-flop 24 has a waveform m
In the case of 1 to m4, the output of the OR gate 20 is output as is, and in the case other than ml to m4, the X2 signal at any of the m1 to m4 waveforms in the past closest to the current time is held. works.

第５図は振幅比較器１７の具体的な実施例であり、２５
〜２６はＯＲ／ＮＤＲゲート、２７〜２８はＡ　Ｎ　Ｉ
）ゲートである。FIG. 5 shows a specific embodiment of the amplitude comparator 17, and 25
~26 are OR/NDR gates, 27~28 are ANI
) is a gate.

第６図はＱＡＭ変調波等を検波した復調ベースバンド信
号が４値の場合の実施例であり、２９は３ビツトＡ／Ｄ
コンバータ、３０は判別回路である。Figure 6 shows an example in which the demodulated baseband signal obtained by detecting a QAM modulated wave etc. is a four-value signal, and 29 is a 3-bit A/D signal.
Converter 30 is a discrimination circuit.

第７図は第６図の説明図で４値のベースバンド信号とコ
ンバータ２９の出力Ｘ１〜Ｘ３との関係を表わしている
。第６図において復調ベースバンド信号が４値の場合に
は、第７図の如く、入力信号の位置を判定するデータ信
号はＸ３となるので、論理回路９にはＸ３が入力される
。３０は第２図の場合と同一機能の信号Ｇ、Ｇを出力し
、それらは論理回路９に入力される。その結果論理回路
９出力にはサンプリング点ずれを検出する誤差信号ＡＰ
Ｃが得られるので、それを低域ろ波器６を介して電圧制
御発振器５に制御信号として与えてやれば、第６図の回
路は４値の復調ベースバンド信号に適用できる。タイミ
ング回路として動作する。FIG. 7 is an explanatory diagram of FIG. 6 and shows the relationship between the four-level baseband signal and the outputs X1 to X3 of the converter 29. In FIG. 6, when the demodulated baseband signal is four-valued, the data signal for determining the position of the input signal is X3, as shown in FIG. 7, so X3 is input to the logic circuit 9. 30 outputs signals G and G having the same function as in the case of FIG. 2, and these are input to the logic circuit 9. As a result, the logic circuit 9 outputs an error signal AP that detects the sampling point shift.
Since C is obtained, if it is given as a control signal to the voltage controlled oscillator 5 via the low-pass filter 6, the circuit of FIG. 6 can be applied to a four-level demodulated baseband signal. Operates as a timing circuit.

第８図は判別回路３０の実施例であり、３１〜３６はＤ
タイプフリップフロップ、３７は振幅比較器である。以
下動作を説明する。フリップフロップ３１．３４の出力
には信号Ｘｉ、Ｘ２のＴ１時のデータＹ１が得られ、フ
リップフロップ３３゜３６の出力には信号Ｘｉ、Ｘ２の
Ｔ−１時のデータＹ−１が得られるので、それらを振幅
比較器３７に入力して、ここで復調ベースバンド信号の
微係数の極性を判別する。今、Ｔ−１時の４値信号をＡ
Ｔ−１，Ｔ１時の４値信号をＡ’ｌ”ｌとすると、振幅
比較器３７では、ＡＴｌ−ＡＴ−１冨Ｍを演算させ、Ｍ
が正即ち１０時の微係数が正の時出力Ｇに１、Ｍが負、
即ちＴ０時の微係数が負の時、出方百に１を出力する。FIG. 8 shows an embodiment of the discrimination circuit 30, and 31 to 36 are D
type flip-flop, 37 is an amplitude comparator. The operation will be explained below. The data Y1 at T1 of the signals Xi and X2 is obtained at the output of the flip-flops 31 and 34, and the data Y-1 at T-1 of the signals Xi and , are input to the amplitude comparator 37, where the polarity of the differential coefficient of the demodulated baseband signal is determined. Now, the 4-level signal at T-1 is A
Assuming that the four-level signal at T-1 and T1 is A'l''l, the amplitude comparator 37 calculates ATl-AT-1 and M.
is positive, that is, when the differential coefficient at 10 is positive, the output G is 1, and M is negative.
That is, when the differential coefficient at time T0 is negative, 1 is output for the output.

ＡＴ−１，ＡＴＩけフリップフロップ３１．３３．３４
．３６の出力から論理演算によって得られる。AT-1, ATI flip-flop 31.33.34
．． It is obtained from the output of 36 by logical operation.

９− 以上のように２値及び４値の復調ベースバンド信号に適
用できる本発明による実施例を説明したが、本発明はこ
れに限られるものではなく、これ以上の多値ベースバン
ド信号に適用できる。たと路に供給すればよい。9- As described above, the embodiments according to the present invention that can be applied to binary and quaternary demodulated baseband signals have been described, but the present invention is not limited to this, and can be applied to multilevel baseband signals of higher levels. can. All you have to do is supply it to the road.

以上説明したように、本発明は帯域制限をうけたベース
バンド信号に対して適用されるもので、実施例において
の帯域制限の条件は第３図の如き波形応答が得られるも
のを用いたが、帯域制限の条件が変われば、当然第３図
における波形応答が変化する。その場合には、その条件
に適合するように判別回路１０あるいは３０を変える必
要がある。第２図、第６図の実施例においてはデジタル
搬送波伝送方式に用いられるタイミング同期回路として
説明したが、本発明はこれに限定されるものではなく、
第３図（ａ）に示されるようなペースパ１０− ンド信号を伝送するベースバンド伝送方式に対しても適
用可能である。判別回路の実施例として第４図及び第８
図をあげたが、この回路に求められることはサンプリン
グ時点でのベースバンド信号の微係数の極性を判別する
機能であり、種々の実現手段が考えられ、第４，８図に
限定されない。As explained above, the present invention is applied to a band-limited baseband signal, and the band-limiting conditions in the embodiment were such that a waveform response as shown in FIG. 3 was obtained. , if the band-limiting conditions change, the waveform response in FIG. 3 will naturally change. In that case, it is necessary to change the discrimination circuit 10 or 30 to match the condition. Although the embodiments shown in FIGS. 2 and 6 are explained as timing synchronization circuits used in a digital carrier wave transmission system, the present invention is not limited to this.
It is also applicable to a baseband transmission system for transmitting a pace band signal as shown in FIG. 3(a). 4 and 8 as examples of the discrimination circuit.
Although the figure is shown, what is required of this circuit is a function of determining the polarity of the differential coefficient of the baseband signal at the time of sampling, and various implementation means are possible, and are not limited to those shown in FIGS. 4 and 8.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はタイミング同期回路の従来例、第２図は本発明
によるタイミング同期回路の実施例、第３図は第２図の
説明図、第４図は本発明による判別回路及び論理回路の
実施例、第５図は第４図の振幅比較器、第６図は本発明
によるタイミング同期（ロ）路の他の実施例、第７図は
第６図の説明図、第８図は第６図の判別回路の実施例で
ある。 図において、１・・・・・・位相比較器、２・・・・・
・全波整流回路、３・・・・・・位相同期回路、４・・
・・・・位相比較器、５・・・・・・電圧制御発振器、
６・・・・・・低域ろ波器、７・・・・・・位相シフタ
ー、８・・・・・・１ビツトＡ／Ｄコンバータ、９・・
・・・・論理回路、１０および３０・・・・・・判別回
路％　１１・・・・・・２ビツトＡ／Ｄコンバータ、１
２〜１６．２４および３１〜３６・・・・・・Ｄタイプ
フリップフルツブ、１７および３７・・・・・・振幅比
較器、１８゜２５および２６・・・・・・ＯＲ／Ｎ　Ｏ
Ｒゲート、１９および２０・・・・・・ＯＲゲート、２
１〜２３．２７および２８・・・・・・ＡＮＤゲート、
２９・・・・・・３ビツトＡ／Ｄコンバータ、である。FIG. 1 is a conventional example of a timing synchronization circuit, FIG. 2 is an embodiment of a timing synchronization circuit according to the present invention, FIG. 3 is an explanatory diagram of FIG. 2, and FIG. 4 is an implementation of a discrimination circuit and a logic circuit according to the present invention. For example, FIG. 5 shows the amplitude comparator shown in FIG. 4, FIG. 6 shows another embodiment of the timing synchronization (b) path according to the present invention, FIG. This is an example of the discrimination circuit shown in the figure. In the figure, 1... phase comparator, 2...
・Full-wave rectifier circuit, 3... Phase synchronized circuit, 4...
... Phase comparator, 5 ... Voltage controlled oscillator,
6...Low pass filter, 7...Phase shifter, 8...1 bit A/D converter, 9...
...Logic circuit, 10 and 30 ...Discrimination circuit% 11 ...2-bit A/D converter, 1
2~16.24 and 31~36...D type flip full tube, 17 and 37...amplitude comparator, 18°25 and 26...OR/N O
R gate, 19 and 20...OR gate, 2
1 to 23.27 and 28...AND gate,
29...3-bit A/D converter.

Claims (1)

【特許請求の範囲】[Claims] 帯域制限をうけたベースバンド信号からタイミング信号
を再生するタイミング同期回路において、制御電圧によ
って発振周波数が変化する電圧制御発振器と、前記電圧
制御発振器の出力を用いて、前記ベースバンド信号をサ
ンプリング整形するＡ／Ｄコンバータと、前記Ａ／Ｄコ
ンバータ出力からサンプリング点での前記ベースバンド
信号の微係数の極性を判別する判別回路と、前記判別回
路出力から前記Ａ／Ｄコンバータ出力のうち前記ベース
バンド信号の位置判別を行う位置判別信号に論理操作を
行うことによって前記制御信号を得る論理回路とを具備
することを特徴とするタイミング同期回路。In a timing synchronization circuit that reproduces a timing signal from a band-limited baseband signal, the baseband signal is sampled and shaped using a voltage-controlled oscillator whose oscillation frequency changes depending on a control voltage, and the output of the voltage-controlled oscillator. an A/D converter; a determination circuit that determines the polarity of the differential coefficient of the baseband signal at a sampling point from the output of the A/D converter; and a determination circuit that determines the baseband signal of the output of the A/D converter from the output of the determination circuit. and a logic circuit that obtains the control signal by performing a logical operation on a position determination signal for determining the position of the timing synchronization circuit.
JP58035348A 1983-03-04 1983-03-04 Timing synchronizing circuit Granted JPS59161149A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP58035348A JPS59161149A (en) 1983-03-04 1983-03-04 Timing synchronizing circuit
CA000448593A CA1208311A (en) 1983-03-04 1984-03-01 Timing synchronizing circuit for demodulators
DE8484102234T DE3485782T2 (en) 1983-03-04 1984-03-02 CLOCK SYNCHRONIZATION CIRCUIT.
AU25228/84A AU556574B2 (en) 1983-03-04 1984-03-02 Timing synchronizing circuit
US06/585,653 US4528512A (en) 1983-03-04 1984-03-02 Timing synchronizing circuit for demodulators
EP84102234A EP0118119B1 (en) 1983-03-04 1984-03-02 Timing synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58035348A JPS59161149A (en) 1983-03-04 1983-03-04 Timing synchronizing circuit

Publications (2)

Publication Number Publication Date
JPS59161149A true JPS59161149A (en) 1984-09-11
JPH0223106B2 JPH0223106B2 (en) 1990-05-22

Family

ID=12439351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58035348A Granted JPS59161149A (en) 1983-03-04 1983-03-04 Timing synchronizing circuit

Country Status (6)

Country Link
US (1) US4528512A (en)
EP (1) EP0118119B1 (en)
JP (1) JPS59161149A (en)
AU (1) AU556574B2 (en)
CA (1) CA1208311A (en)
DE (1) DE3485782T2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6171736A (en) * 1984-09-17 1986-04-12 Nec Corp Differential coefficient discriminating circuit
WO1988005235A1 (en) * 1987-01-12 1988-07-14 Fujitsu Limited Discrimination timing control circuit
JPH04298142A (en) * 1991-03-26 1992-10-21 Nec Corp Clock synchronization circuit
US5789988A (en) * 1996-03-07 1998-08-04 Nec Corporation Clock recovery circuit for QAM demodulator

Families Citing this family (13)

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Publication number Priority date Publication date Assignee Title
JPS6156555A (en) * 1984-08-27 1986-03-22 Nec Corp Demodulator
JPS61137446A (en) * 1984-12-10 1986-06-25 Nec Corp Demodulating device
JPH0732391B2 (en) 1985-05-28 1995-04-10 日本電気株式会社 Clock synchronization circuit
US4794341A (en) * 1985-11-05 1988-12-27 Signal Processors Limited Digital filters and demodulators
WO1989000365A1 (en) * 1987-06-30 1989-01-12 Ant Nachrichtentechnik Gmbh Timing system
WO1989002200A1 (en) * 1987-08-28 1989-03-09 Case/Datatel Adaptive jitter-tracking method and system
US4790941A (en) * 1988-03-18 1988-12-13 Separation Dynamics, Inc. Fluid decontamination system
FR2634083B1 (en) * 1988-07-06 1991-04-12 Alcatel Thomson Faisceaux METHOD FOR CONTROLLING THE PHASE OF THE RHYTHM RECOVERED IN A DIGITAL DEMODULATION AND DEVICE FOR CARRYING OUT SUCH A METHOD
US4964117A (en) * 1988-10-04 1990-10-16 Vtc Incorporated Timing synchronizing circuit for baseband data signals
JPH0369238A (en) * 1989-08-08 1991-03-25 Mitsubishi Electric Corp Demodulated data discriminating device
DE69318594T2 (en) * 1992-02-24 1998-11-26 Philips Electronics N.V., Eindhoven Transmission system with a receiver with improved clock regeneration means
JPH07154439A (en) * 1993-11-26 1995-06-16 Nec Eng Ltd Demodulator
US20140369395A1 (en) * 2013-06-13 2014-12-18 Lsi Corporation Error Detection Based on Superheterodyne Conversion and Direct Downconversion

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5917916B2 (en) * 1975-12-26 1984-04-24 日本電気株式会社 Isoudouukisouchi
JPS5925500B2 (en) * 1978-03-03 1984-06-18 日本電気株式会社 Carrier wave regeneration circuit
JPS57131151A (en) * 1981-02-06 1982-08-13 Nec Corp Carrier wave reproducing circuit
CA1180416A (en) * 1981-05-19 1985-01-02 Botaro Hirosaki Timing recovery circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6171736A (en) * 1984-09-17 1986-04-12 Nec Corp Differential coefficient discriminating circuit
WO1988005235A1 (en) * 1987-01-12 1988-07-14 Fujitsu Limited Discrimination timing control circuit
US4912726A (en) * 1987-01-12 1990-03-27 Fujitsu Limited Decision timing control circuit
JPH04298142A (en) * 1991-03-26 1992-10-21 Nec Corp Clock synchronization circuit
US5789988A (en) * 1996-03-07 1998-08-04 Nec Corporation Clock recovery circuit for QAM demodulator

Also Published As

Publication number Publication date
JPH0223106B2 (en) 1990-05-22
AU556574B2 (en) 1986-11-06
US4528512A (en) 1985-07-09
AU2522884A (en) 1984-09-06
EP0118119B1 (en) 1992-06-24
CA1208311A (en) 1986-07-22
DE3485782T2 (en) 1993-01-28
DE3485782D1 (en) 1992-07-30
EP0118119A2 (en) 1984-09-12
EP0118119A3 (en) 1987-11-04

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