JPS59155947A - Multilayer interconnection method - Google Patents

Multilayer interconnection method

Info

Publication number
JPS59155947A
JPS59155947A JP3058083A JP3058083A JPS59155947A JP S59155947 A JPS59155947 A JP S59155947A JP 3058083 A JP3058083 A JP 3058083A JP 3058083 A JP3058083 A JP 3058083A JP S59155947 A JPS59155947 A JP S59155947A
Authority
JP
Japan
Prior art keywords
wiring
resist
sections
film
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3058083A
Other languages
Japanese (ja)
Inventor
Toshiki Ehata
敏樹 江畑
Kenichi Kikuchi
健一 菊地
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP3058083A priority Critical patent/JPS59155947A/en
Publication of JPS59155947A publication Critical patent/JPS59155947A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To remove a short circuit due to the insufficient strength of an upper side wiring by solftening sections except the connecting section of upper and lower wirings at a temperature of 500 deg.C or less, temporarily filling the sections except the connecting section with an insulating protective film, which can be removed by gas plasma, and removing the protective film after forming the upper side wiring in an air bridge method, through which wiring metals on the upper side and the lower side cross in three dimensions without through an insulating layer, in multilayer interconnection technique for an IC. CONSTITUTION:Lower layer metallic wirings 21 are formed through photolithography and a lift-off method, the whole surface is coated with an Si3N4 film 24, and connecting sections 25 of an upper layer and a lower layer are removed. A resist 23 is formed only to a crossing section and the peripheral region of the crossing section through the film 24, and baked at a temperature of 500 deg.C or less higher than a temperature where the resist softens, and the resist 23 is formed to a hemispherical shape by surface tension. An upper layer wiring 22 is applied while being fast stuck to the surface and crossing the resist 23, and end sections are connected to the lower layer wirings 21 through the connecting sections 25. The unnecessary resist 23 positioned under the wiring 22 is removed through plasma etching by O2 gas, and the upper layer wiring 22 in which a deformation, etc. are not generated, is acquired.

Description

【発明の詳細な説明】 技術分野 本発明は半導体基板上にトランジスタ、抵抗、コイル、
コンデンサ等の電子部品を形成し相互に接続したいわゆ
る集積回路の構造製造技術に関するものである。
[Detailed Description of the Invention] Technical Field The present invention provides transistors, resistors, coils, etc. on a semiconductor substrate.
The present invention relates to structural manufacturing technology for so-called integrated circuits in which electronic components such as capacitors are formed and interconnected.

背景技術 集積回路の動作速度を高速化し、かつ低消費電力化を図
るには素子の微細化回路の高集積度化が必須である。こ
れに伴ない各部品及びそれらを相互に接続するための配
線が近接し、さらに配線間の交叉部が増加するこ゛とに
なる。
BACKGROUND ART In order to increase the operating speed of integrated circuits and reduce power consumption, it is essential to miniaturize elements and increase the degree of integration of circuits. As a result, each component and the wires for connecting them to each other are brought closer to each other, and the number of intersections between the wires increases.

その結果、とくに配線容量が増加し、動作速度の低減に
つながる。これを防ぐために有効な配線間の絶縁法が必
要となる。
As a result, the wiring capacitance in particular increases, leading to a reduction in operating speed. To prevent this, an effective method of insulating the wiring is required.

このような目的に対する有効な手段にエアブリッジ法が
ある。これは図1に示すように集積回路内において、下
側の金属配線と上側の金属配線とが交叉する場合に両者
間に絶、碌膜を介さず、上側の配線金属が立体交叉する
多層配線技術である。
The air bridge method is an effective means for achieving this purpose. As shown in Figure 1, in an integrated circuit, when lower metal wiring and upper metal wiring intersect, there is no separation between them, and the upper metal wiring intersects in three dimensions. It's technology.

この方法の特徴は2種の配線は比誘電率の最も小さい空
気で絶縁さ−れているため他の任意の絶縁膜を用いる場
合に比して両配線間の容量が最も小さくなることにある
。このため回路内の配線容量が低減され集積回路の動作
速度が改善される。しかしながらエアブリッジは構造上
上層配線が中空に浮いた状態にあり、エアブリッジ形成
後は表面に接触することができなくなる。このため、以
後の工程において、以下のような様々な技術的問題点制
約が生じる。
The feature of this method is that the two types of wiring are insulated with air, which has the lowest dielectric constant, so the capacitance between both wirings is the smallest compared to when using any other insulating film. . This reduces the wiring capacitance within the circuit and improves the operating speed of the integrated circuit. However, due to the structure of the air bridge, the upper layer wiring is suspended in the air, and cannot contact the surface after the air bridge is formed. For this reason, various technical problems and restrictions as described below arise in subsequent steps.

すなわち、 1)高周波特性向上のため基板厚さを裏面から薄くする
場合、化学エツチングVて必要な保護膜の形成が必要で
ある。一方機械的研磨によって基板を薄くする場合基板
表面に接触する必要がある。
That is, 1) When thinning the substrate from the back side in order to improve high frequency characteristics, it is necessary to form a necessary protective film by chemical etching. On the other hand, when thinning a substrate by mechanical polishing, it is necessary to contact the substrate surface.

2)基板上に多数繰り返して形成された半導体装置を分
離しチップ化するスクライブ、セパレー斗の工程では表
面に破片や汚れが付着したり傷を付けたりすることを防
ぐために裏1mから加工処理を施すことが多く、必然的
に表面に接触することになる。
2) In the scribing and separating process, in which semiconductor devices that have been repeatedly formed on a substrate are separated and made into chips, processing is performed starting from the back 1m to prevent debris and dirt from adhering to the surface or causing scratches. It is often applied and inevitably comes into contact with the surface.

3)チップ化した半導体装置を−っずっパッケージへ装
Jaするボンディング工程ではコレットや真空ピンカッ
トにてチップ表面側を吸着することになる。
3) In the bonding process of mounting a semiconductor device in the form of a chip into a package, the front surface of the chip is adsorbed using a collet or a vacuum pin cut.

・1・)最終的に集積回路に保護膜を形成する場合、外
部へih気気後接続とり出す゛ため保護j摸にR口部を
設ける。ここで通常のコンタクト露光にょるホトリソグ
ラフィを適用する場合、基板表面はホトマスクに強く密
着されることになる。
・1.) When a protective film is finally formed on the integrated circuit, an R opening is provided on the protective layer to take out the connection to the outside after the Ih atmosphere. If photolithography using normal contact exposure is applied here, the substrate surface will be tightly adhered to the photomask.

またエアブリッジをもつ回路は段差が大きくエアブリッ
ジ形成後に表面全体に均一に保護j1%を形成すること
は困難である。
In addition, a circuit with an air bridge has a large step difference, and it is difficult to uniformly form the protection j1% on the entire surface after forming the air bridge.

以上の工程ぼたは取扱いはエアブリッジを保護するとい
う点からは実施できないものであり、上述と同等の工程
を実施するためには煩雑な工程を附加することになる。
The above-mentioned process cannot be handled from the viewpoint of protecting the air bridge, and in order to carry out the same process as the above, a complicated process will be added.

この場合半導体装置の生産性、歩留りが著しく悪化する
という問題点が生じる。
In this case, a problem arises in that the productivity and yield of semiconductor devices are significantly deteriorated.

一方、エアブリッジ自身構造的に弱いものであり僅かの
外方に占っても上層配線が切れたり、下層配線と接触す
ることが多く歩留りが低いという問題がある。また、配
線間の接触を防ぐため上層配線をできるだけ高い位置に
形成することが多く段差切れの危険がある。
On the other hand, the air bridge itself is structurally weak, and there is a problem in that even if the air bridge moves outward slightly, the upper layer wiring may break or come into contact with the lower layer wiring, resulting in a low yield. Furthermore, in order to prevent contact between wirings, the upper layer wiring is often formed at a position as high as possible, and there is a risk of step breakage.

発明の開示 本発明は上記従来技術の問題点を解決する新しい゛ト導
体装置1′1−構造を提供するものである。
DISCLOSURE OF THE INVENTION The present invention provides a new conductor device 1'1-structure that solves the problems of the prior art described above.

以下−実施例を図に即して説明する。図2は一実施例を
説明するための製作工程図である。まず通常のフォトリ
ソグラフィとリフトオフ法によって下)+、’Qの配線
金属21を形成した後、プラズマC,VD法で厚さQJ
77mの窒化シリコン膜24を保護JJ%として形成す
る。上層・下層配線の接続部25と集積回路のパッドの
部分以外にレジストパターンを形成し、これをマスクと
してCF、ガスプラズマにて窒化シリコンj漢24をエ
ツチングする(図2−(A))。マスクとなったレジス
トパターンを灰化処理で除去した後、回転塗布法で2.
5μm厚のフ第1・レジスト(0FPR−800)を塗
りフォトリングラフィでエアブリッジを形成する交叉部
及びその周辺領域にのみレジスト23を残す。(図2−
(B)、1)この後200 ’Cの温度で20分間ベー
クした。この時の温度はレジストが軟化する温度より十
分高いためレジストが流れ表面張力によって半球状の形
状となる。(図2−(C))次いで下層配線と同等の方
法により上層配線22を形成する。(図2−(D))絶
縁膜23の断面は軟化して殆んど円に近い状態であるた
め上層配線が絶縁1漢23の段差部で断線するいわゆる
段差切れが解消できた。続い−て酸素ガスのプラズマエ
ツチングによりエアブリッジ構造のフォトレジスト膜2
8を除去し図2−(E)に示すようなエアブリッジとす
る。以後、裏面研磨、スクライブ、セバレニト、ポンデ
ィング等の組立工程や保護膜形成工程を従来技術をその
まま適用して半導体装置を実現することができる。ここ
でエアブリッジ構造の窒化シリコン膜38を除去する工
程はガスプラズマによるエツチングであり、組立工程の
中で基板表面に接触する必要がなくなる時点まで絶縁膜
28を残しておくこともできる。
Hereinafter, embodiments will be described with reference to the drawings. FIG. 2 is a manufacturing process diagram for explaining one embodiment. First, a wiring metal 21 of (lower)
A 77 m thick silicon nitride film 24 is formed as a protection JJ%. A resist pattern is formed in areas other than the connection portion 25 of the upper layer/lower layer wiring and the pad of the integrated circuit, and using this as a mask, the silicon nitride film 24 is etched with CF and gas plasma (FIG. 2-(A)). After removing the resist pattern that served as a mask by ashing treatment, 2.
A first resist (0FPR-800) with a thickness of 5 μm is applied, and the resist 23 is left only at the intersection where an air bridge is to be formed and its surrounding area by photolithography. (Figure 2-
(B), 1) This was followed by baking at a temperature of 200'C for 20 minutes. Since the temperature at this time is sufficiently higher than the temperature at which the resist softens, the resist flows and takes on a hemispherical shape due to surface tension. (FIG. 2-(C)) Next, the upper layer wiring 22 is formed by the same method as the lower layer wiring. (FIG. 2-(D)) Since the cross section of the insulating film 23 is softened and almost circular, so-called step breakage in which the upper layer wiring is broken at the step portion of the insulating layer 23 can be eliminated. Subsequently, the photoresist film 2 with an air bridge structure is formed by oxygen gas plasma etching.
8 is removed to form an air bridge as shown in FIG. 2-(E). Thereafter, a semiconductor device can be realized by applying conventional techniques to assembly processes such as back polishing, scribing, sebarenite, and bonding, and to forming a protective film. The step of removing the silicon nitride film 38 of the air bridge structure is gas plasma etching, and the insulating film 28 can be left until it is no longer necessary to contact the substrate surface during the assembly process.

これによりエアブリッジが損傷して歩留りが低下すると
いう問題が解決できる。実施例では絶縁膜23にフォト
レジストを用いたが、500℃以下でできるだけ低温側
で軟化し、ガスプラズマで絶縁膜24に対して選択的に
除去できる材料であれば本発明の要件を満たすものであ
り、何らフォトレシストに制限されるものでない。
This solves the problem that the air bridge is damaged and the yield is reduced. In the embodiment, photoresist was used for the insulating film 23, but any material that softens at a temperature as low as 500° C. or lower and can be selectively removed from the insulating film 24 with gas plasma satisfies the requirements of the present invention. and is not limited to photoresist in any way.

また絶縁膜24・は形成または除去する工程において絶
縁膜23と互いに独立して加工処理できれば本発明の目
的を満たすものであり、材料としては窒化シリコンに何
ら限定されるものでなく、例えばポリイミド樹脂などの
有機樹脂膜、酸化シリコン、酸化アルミナ等の無機化合
物膜を用いることもできる。
Further, the object of the present invention is satisfied if the insulating film 24 can be processed independently from the insulating film 23 in the process of forming or removing it, and the material is not limited to silicon nitride, for example, polyimide resin. It is also possible to use an organic resin film such as, or an inorganic compound film such as silicon oxide or alumina oxide.

発明の効果 本発明では、上層・下層の配線の接続部以外が絶縁ノ漢
で保護された状態でエアブリッジを形成するものであり
、l)’iJ配線の強度不足で生じる配線間の短絡を防
ぐと共に工程上表面に接触することがなくなるまで絶縁
膜23を残すことができる。
Effects of the Invention In the present invention, an air bridge is formed with the parts other than the connecting portions of the upper and lower layer wiring protected by an insulator. In addition to preventing this, the insulating film 23 can be left until it no longer comes into contact with the surface during the process.

さらに段差切れをもなくすことができるためエアブリッ
ジの歩留り、信頼性が飛躍的に向上するものである。
Furthermore, since step cuts can be eliminated, the yield and reliability of air bridges can be dramatically improved.

【図面の簡単な説明】[Brief explanation of the drawing]

図1はエアブリッジ構造の一例、図2 (A)、(B)
、(C)、(D)、(E)は本発明の実施例の一例を説
明するための製作工程図である。 11.2.1・・・下側の配線 12.22・・・上側の配線 23・・・エアブリッジのための絶縁膜24・・・・保
護のための絶縁膜 25・・・上層・下層配線の接続部
Figure 1 is an example of an air bridge structure, Figure 2 (A), (B)
, (C), (D), and (E) are manufacturing process diagrams for explaining an example of an embodiment of the present invention. 11.2.1... Lower wiring 12.22... Upper wiring 23... Insulating film for air bridge 24... Insulating film for protection 25... Upper layer/lower layer Wiring connection

Claims (2)

【特許請求の範囲】[Claims] (1)集積回路の多層配線技術のうち上側と下側の配線
金属が絶縁膜を介さずに立体交叉するエアブリッジ法に
おいて、上・下配線の接続部以外が絶縁性保護膜でおお
われていることを特徴とする多層配線方法。
(1) In the air bridge method, which is a multilayer wiring technology for integrated circuits in which the upper and lower wiring metals intersect three-dimensionally without an insulating film, the parts other than the connecting parts of the upper and lower wirings are covered with an insulating protective film. A multilayer wiring method characterized by:
(2)上記請求範囲1において、上層配線を形成するた
めに丁層配線及び交叉部をおおう絶縁性材料が500 
’C以下の温度で軟化し、かつガスプラズマで除去でき
る拐料であることを特徴とする特許請8求の範囲第1項
記載の多層配線方法。
(2) In Claim 1 above, the insulating material covering the lower layer wiring and the crossing portion to form the upper layer wiring is 500%
9. The multilayer interconnection method according to claim 8, wherein the thinning material is softened at a temperature of 0.1C or lower and can be removed by gas plasma.
JP3058083A 1983-02-24 1983-02-24 Multilayer interconnection method Pending JPS59155947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3058083A JPS59155947A (en) 1983-02-24 1983-02-24 Multilayer interconnection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3058083A JPS59155947A (en) 1983-02-24 1983-02-24 Multilayer interconnection method

Publications (1)

Publication Number Publication Date
JPS59155947A true JPS59155947A (en) 1984-09-05

Family

ID=12307787

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3058083A Pending JPS59155947A (en) 1983-02-24 1983-02-24 Multilayer interconnection method

Country Status (1)

Country Link
JP (1) JPS59155947A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH025213A (en) * 1988-06-23 1990-01-10 Sharp Corp Manufacture of thin film magnetic head

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH025213A (en) * 1988-06-23 1990-01-10 Sharp Corp Manufacture of thin film magnetic head
JP2501873B2 (en) * 1988-06-23 1996-05-29 シャープ株式会社 Method of manufacturing thin film magnetic head

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