JPS59154051A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59154051A
JPS59154051A JP58028964A JP2896483A JPS59154051A JP S59154051 A JPS59154051 A JP S59154051A JP 58028964 A JP58028964 A JP 58028964A JP 2896483 A JP2896483 A JP 2896483A JP S59154051 A JPS59154051 A JP S59154051A
Authority
JP
Japan
Prior art keywords
lead frame
frame
resin
mold
plastic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58028964A
Other languages
Japanese (ja)
Inventor
Masahiro Yamada
正弘 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP58028964A priority Critical patent/JPS59154051A/en
Publication of JPS59154051A publication Critical patent/JPS59154051A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a packaging method having a structure of strong water resistance by using a lead frame coated with plastic resin material. CONSTITUTION:The material coated with the plastic resin 202 such as resin at the top is used for the outer lead part of the lead frame 201 made of a metallic material such as 4-2 alloy. A chip 203 is mounted on said frame and wire-bonded by means of Au wires 204, and the whole frame is set in a mold, thereafter fused plastic mold material 205 is cast and hardened. The titled device formed thereby improves in the hermetic property of the lead frame part and becomes reinforced in moisture resistance.

Description

【発明の詳細な説明】 本発明は、トランスファーモールドパッケージであシな
がら従来のモールド品よシも、信頼性とくに耐水性が強
い構造を有するパッケージング法を提供するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a packaging method that has a structure that is more reliable and particularly water resistant than conventional molded products, although it is a transfer molded package.

従来、半導体素子の実装方法に於いて、高信頼性を必要
とする分野での用途に対しては、セラミック系のハーメ
チック封じしたパッケージが用いられていた。このよう
にセラミック系パッケージを用いる理由は、従来のプラ
スチックモールド品（以下モールド品）Ｋ比べ、特に、
耐水性が明確に強いからである。ところが、セラミック
系パッケージは、モールド品に比ベコスト的には、数な
いし十倍と高いため、市場の要求としてコスト的に安価
なモールド品を望む声が多い。そこで、本発明は、従来
からのモールド品に手を加えることによシ、耐水性が強
化出来る構造を提供するものである。Conventionally, in semiconductor device mounting methods, ceramic hermetically sealed packages have been used for applications in fields that require high reliability. The reason for using ceramic packages in this way is that compared to conventional plastic molded products (hereinafter referred to as molded products),
This is because the water resistance is clearly strong. However, the cost of ceramic packages is several to ten times higher than that of molded products, so there are many market demands for molded products that are inexpensive. Therefore, the present invention provides a structure in which water resistance can be enhanced by modifying a conventional molded product.

第一図に、従来例として、モールドフラットパッケージ
品の断面図を示す。４−２７０イ等の伝導性良い金属で
出来たリードフレーム１０１上に、半導体チップ１０２
を、接着し、金線１０３のワイヤーボンディング後、型
の中で溶けたプラスチック材料を流し固め、先の半導体
素子１０２、ＩＪ−ドフレーム１０１の一部を、ブヲス
チツク１０４で封じている。このモールド品の水分の侵
入経路について考える。プラスチック材料は基本的に水
分を通すことが知られているが、実際のモールド品の耐
湿性不良を調べてみると、プラスチック材料を通して入
った水分で起こると考えられるチツブ中央の腐食は稀で
あフはとんどが、ポンディングパッド部の腐食として現
れる。これは、水分の侵入経路が、第１図の矢印に示す
ように、リードフレーム１０１に沿ってモールド内に入
ってくると考えられ、る。これは、リードフレームとプ
ラスチック材料の密着性があまシよくないことに帰因し
ているからであり、従来のモールド品では、このリード
フレームを介して入ってくる水分は、防ぐことは困難で
ある。FIG. 1 shows a cross-sectional view of a molded flat package product as a conventional example. A semiconductor chip 102 is mounted on a lead frame 101 made of a highly conductive metal such as 4-270I.
After wire-bonding the gold wire 103, the melted plastic material is poured into a mold and solidified, and the semiconductor element 102 and a part of the IJ-board frame 101 are sealed with a book stick 104. Let us consider the route of moisture intrusion into this molded product. It is known that plastic materials basically allow moisture to pass through, but when we investigated the moisture resistance of actual molded products, we found that corrosion in the center of the chip, which is thought to be caused by moisture entering through the plastic material, is rare. Most of the damage appears as corrosion on the bonding pad. This is because moisture enters the mold along the lead frame 101 as shown by the arrow in FIG. This is due to poor adhesion between the lead frame and the plastic material, and with conventional molded products, it is difficult to prevent moisture from entering through the lead frame. be.

本発明は、リードフレームとモールド樹脂の密着を上げ
ることによシ、耐湿性が強化されるパッケージを提供す
るものである。、第２図に、本発明の実施例を示す。４
−２アロイ等のメタル材料によるリードフレーム２０１
の、外部リード部に、先にレジン等のブヲスチツク樹脂
２０２を施こした物を用い、チ、ツブ２０３を、リード
フレームにマウントし、Ａｕ線２０４でワイヤーポンデ
ィングを行ない、リードフレーム全体を、型にセットし
たのち、溶解したブヲスチツクモールド材料２０５を流
し固める。これによって形成された本発明の半導体装置
は、従来の方法に比べ、ブヲスチツクモールド樹脂２０
５と先にコーティング処理によって形成したブヲスチツ
ク樹脂２０２を介しＣリードフレーム２０１を封じるた
め、リードフレーム部の気密性が、向上する。これによ
シ耐湿性の強化された半導体装置となる。The present invention provides a package whose moisture resistance is enhanced by increasing the adhesion between the lead frame and the molding resin. , FIG. 2 shows an embodiment of the present invention. 4
-2 Lead frame 201 made of metal material such as alloy
The outer lead part of the lead frame is first coated with a plastic resin 202 such as resin, and the tip 203 is mounted on the lead frame, and wire bonding is performed using Au wire 204 to complete the entire lead frame. After setting in the mold, the melted book stick mold material 205 is poured and solidified. The semiconductor device of the present invention formed by this method is different from the conventional method in that the semiconductor device of the present invention is formed using a book-stick mold resin 20%.
5. Since the C lead frame 201 is sealed via the book stick resin 202 previously formed by a coating process, the airtightness of the lead frame portion is improved. This results in a semiconductor device with enhanced moisture resistance.

【図面の簡単な説明】[Brief explanation of drawings]

第１図：従来のモールドパッケージエＣ第２図：本発明
のモールドパッケージＩＣ２０２が、プラスチックコー
ティング材板　　　上 出願人　株式会社諏訪精工舎Figure 1: Conventional molded package IC Figure 2: The molded package IC202 of the present invention is made of a plastic coating material plate.Applicant: Suwa Seikosha Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] トランスファモールドパッケージ封じされる半導体装置
に於いて、プラスチック樹脂材料によるコーティング処
理されたリードフレームを用いていることを特徴とする
半導体装置。1. A semiconductor device sealed in a transfer mold package using a lead frame coated with a plastic resin material.
JP58028964A 1983-02-22 1983-02-22 Semiconductor device Pending JPS59154051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58028964A JPS59154051A (en) 1983-02-22 1983-02-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58028964A JPS59154051A (en) 1983-02-22 1983-02-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59154051A true JPS59154051A (en) 1984-09-03

Family

ID=12263094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58028964A Pending JPS59154051A (en) 1983-02-22 1983-02-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59154051A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61147555A (en) * 1984-12-21 1986-07-05 Toshiba Corp Semiconductor device
JPS61265845A (en) * 1985-05-20 1986-11-25 Fujitsu Ltd Semiconductor device
US4794446A (en) * 1985-10-25 1988-12-27 Mitsubishi Denki Kabushiki Kaisha Electrode device and a method for making the same
JPH02161759A (en) * 1988-12-14 1990-06-21 Nec Corp Resin-sealed semiconductor device
WO1992004729A1 (en) * 1990-09-10 1992-03-19 Olin Corporation Leadframe for molded plastic electronic packages
CN102629595A (en) * 2012-04-18 2012-08-08 无锡凤凰半导体科技有限公司 Component encapsulating structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61147555A (en) * 1984-12-21 1986-07-05 Toshiba Corp Semiconductor device
JPS61265845A (en) * 1985-05-20 1986-11-25 Fujitsu Ltd Semiconductor device
US4794446A (en) * 1985-10-25 1988-12-27 Mitsubishi Denki Kabushiki Kaisha Electrode device and a method for making the same
JPH02161759A (en) * 1988-12-14 1990-06-21 Nec Corp Resin-sealed semiconductor device
WO1992004729A1 (en) * 1990-09-10 1992-03-19 Olin Corporation Leadframe for molded plastic electronic packages
US5122858A (en) * 1990-09-10 1992-06-16 Olin Corporation Lead frame having polymer coated surface portions
CN102629595A (en) * 2012-04-18 2012-08-08 无锡凤凰半导体科技有限公司 Component encapsulating structure

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