JPS59152881U - Digital image capture device - Google Patents
Digital image capture deviceInfo
- Publication number
- JPS59152881U JPS59152881U JP4661783U JP4661783U JPS59152881U JP S59152881 U JPS59152881 U JP S59152881U JP 4661783 U JP4661783 U JP 4661783U JP 4661783 U JP4661783 U JP 4661783U JP S59152881 U JPS59152881 U JP S59152881U
- Authority
- JP
- Japan
- Prior art keywords
- digital
- memory
- digital image
- image capture
- capture device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図はこの考案の実施例装置の構成を示すブロック図
、第2図は従来装置の構成を示すブロック図である。
1・・・・・・CRTドライブ回路、2・・・・・・C
RT、3・・・・・・レンズ、4・・・・・・シャッタ
機構、5・・・・・・フィルム、6・・・・・・サンプ
リング回路、9・・・・・・ディジタル画像メモリ、1
0・・・・・・メモリコントロール回路、11・・・・
・・D/A変換器、12・・・・・ゼデオ信号発生回路
、13・・・・・・撮影開始ボタン、14・・・・・・
積算回路、15・・・・・・露光時間メモリ。FIG. 1 is a block diagram showing the configuration of an embodiment of this invention, and FIG. 2 is a block diagram showing the configuration of a conventional device. 1...CRT drive circuit, 2...C
RT, 3...Lens, 4...Shutter mechanism, 5...Film, 6...Sampling circuit, 9...Digital image memory ,1
0...Memory control circuit, 11...
...D/A converter, 12...Zedeo signal generation circuit, 13...shooting start button, 14...
Integration circuit, 15... Exposure time memory.
Claims (1)
た画像をフィルムに記録する装置において、前記画像メ
モリの特定領域のディジタル値を積算するディジタル積
算回路と、この積算回路の。 ディジタル積算値でアドレスされ、ディジタル積算値に
対応したシャッタ開放時間制御信号を出力するディジタ
ルメモリとよりなり、前記ディジタルメモリの出力制御
信号で前記CRTとフィルムとの間に介在するシャッタ
機構を制御するようにしたことを特徴とするディジタル
画像撮影装置。[Claims for Utility Model Registration] A device for recording an image read out from a digital image memory and displayed on a CRT onto a film, comprising: a digital integration circuit for integrating digital values in a specific area of the image memory; . It consists of a digital memory that is addressed by the digital integrated value and outputs a shutter opening time control signal corresponding to the digital integrated value, and the shutter mechanism interposed between the CRT and the film is controlled by the output control signal of the digital memory. A digital image capturing device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4661783U JPS59152881U (en) | 1983-03-30 | 1983-03-30 | Digital image capture device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4661783U JPS59152881U (en) | 1983-03-30 | 1983-03-30 | Digital image capture device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59152881U true JPS59152881U (en) | 1984-10-13 |
Family
ID=30177169
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4661783U Pending JPS59152881U (en) | 1983-03-30 | 1983-03-30 | Digital image capture device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59152881U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5598781A (en) * | 1979-01-23 | 1980-07-28 | Tokyo Shibaura Electric Co | Display image photograph unit |
-
1983
- 1983-03-30 JP JP4661783U patent/JPS59152881U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5598781A (en) * | 1979-01-23 | 1980-07-28 | Tokyo Shibaura Electric Co | Display image photograph unit |
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