JPS59143370A - Semiconductor rectifying device - Google Patents
Semiconductor rectifying deviceInfo
- Publication number
- JPS59143370A JPS59143370A JP1603283A JP1603283A JPS59143370A JP S59143370 A JPS59143370 A JP S59143370A JP 1603283 A JP1603283 A JP 1603283A JP 1603283 A JP1603283 A JP 1603283A JP S59143370 A JPS59143370 A JP S59143370A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- semiconductor layer
- rectifier
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000000694 effects Effects 0.000 claims description 29
- 239000012535 impurity Substances 0.000 claims description 9
- 230000007547 defect Effects 0.000 claims description 3
- 229910001385 heavy metal Inorganic materials 0.000 claims description 2
- 229910001020 Au alloy Inorganic materials 0.000 claims 1
- 230000002457 bidirectional effect Effects 0.000 claims 1
- 239000003353 gold alloy Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 abstract description 13
- 238000003475 lamination Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008094 contradictory effect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000723353 Chrysanthemum Species 0.000 description 1
- 235000007516 Chrysanthemum Nutrition 0.000 description 1
- 206010024229 Leprosy Diseases 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体整流装置、特に整流用ダイオードに関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor rectifier, and in particular to a rectifier diode.
〔従来技術〕
電子計算機およびそれに連なる各種端末機器、あるいは
各種システム機器の′電源として、比較的低電圧の直流
安定化電源全装する。商用交流電源から低電圧の直流安
定化電源を得るためには種々の方法があるが、小型、高
効率の特徴を持つスイッチングレギュレータ方式が優れ
ている。[Prior Art] A relatively low-voltage DC stabilized power supply is fully installed as a power source for electronic computers and various terminal equipment connected thereto, or various system equipment. There are various methods for obtaining a low-voltage DC stabilized power supply from a commercial AC power supply, but the switching regulator method is superior due to its small size and high efficiency.
上述のような電源に用いられる整流用ダイオードとして
は低損失性、安定性および高速性が要求されるが、従来
公知のダイオードではこれらの点で不満足であった。す
なわち、第１図にその例を示す周知のショットキバリヤ
ダイオードでは逆方向漏れ電流が大きくかつ耐圧が数十
■程腿と低く熱的に不安定であるという欠点があった。Rectifier diodes used in power supplies such as those described above are required to have low loss, stability, and high speed, but conventionally known diodes have been unsatisfactory in these respects. That is, the well-known Schottky barrier diode, an example of which is shown in FIG. 1, has the drawbacks of large reverse leakage current, low withstand voltage of several tens of microns, and thermal instability.
また、第２図にその１例を示すｐｎ接合型のダイオード
では比較的高耐圧が得られるが低損失性が十分でないと
いう欠点があった。Further, a pn junction type diode, an example of which is shown in FIG. 2, has a drawback that although a relatively high breakdown voltage can be obtained, the loss is not sufficiently low.
本発明の目的は、従来の整流ダイオードの欠点を解決し
、低損失性、高速性に優れると共に高耐圧の半導体整流
装置を提供することにある。An object of the present invention is to solve the drawbacks of conventional rectifying diodes and to provide a semiconductor rectifying device that has low loss, high speed, and high breakdown voltage.
不発羽生導体整流装置の特徴とするところは、一対の主
電極間の半導体基体が、主電流通路となる第１の領域と
主電流通路全実質的にとり囲、むように設けられ、ｐｎ
接合を有し、このｐｎ接合が逆バイアスされたときに生
じる空乏層により主電流通路全ピンチオフする機能金有
する第２の領域とからなシ、第１の領域の少くともピン
チオンされる部分に重金属又は格子欠陥等のキャリヤ補
償作用を引起す手段全導入したことにある。The feature of the unexploded Hanyu conductor rectifier is that the semiconductor substrate between the pair of main electrodes is provided so as to substantially surround the first region serving as the main current path and the entire main current path;
The second region has a function of pinching off the entire main current path due to the depletion layer generated when this pn junction is reverse biased, and the first region has a heavy metal at least in the portion that is pinched off. Alternatively, all means for causing carrier compensation effects such as lattice defects have been introduced.
このように主電流上流す第１の領域と主電流を実質的に
流さない第２の領域とを備え、逆阻止状態においては第
２の領域で生じる空乏層によって第１の領域がピンチオ
ンされ逆電流が阻止される構成となっているので、第１
の領域の構造を高耐圧化とは一般に相反する関係にある
低損失かつ高速化という点のみから設計でき、よって低
損失、高速、高耐圧を備えた半導体基体内Ｒを実現でき
る。また、第１の領域のピンチオンされる部分はキャリ
ヤ補償作用により抵抗率が高くなっているので、ｐｎ接
合からの静電的影響音強く受はピンチオフ効果が強くな
るので、ピンチオフ會起すための構造寸法上の制限が大
幅に緩和され、素子製造が極めて容易になる。In this way, it has a first region through which the main current flows and a second region where the main current does not flow substantially, and in the reverse blocking state, the first region is pinched on by the depletion layer generated in the second region and the reverse occurs. Since the current is blocked, the first
The structure of the region can be designed only from the viewpoint of low loss and high speed, which are generally in a contradictory relationship with high withstand voltage, and therefore it is possible to realize R in the semiconductor substrate with low loss, high speed, and high withstand voltage. In addition, since the portion of the first region that is pinched has a high resistivity due to the carrier compensation effect, the electrostatic sound from the pn junction is strongly affected, and the pinch-off effect becomes stronger. Dimensional restrictions are significantly relaxed, and device manufacturing becomes extremely easy.
以下、実禰例として示した図面により本発明の詳細な説
明する。Hereinafter, the present invention will be explained in detail with reference to the drawings shown as practical examples.
第３図及び第４図において、一対の主表面１０１及び１
０２を有する半導体基体１００は、一対の主表面間に、
カソード電極５にオーミック接触するｎ層型層１、層１
に隣接しそれよりも低濃度のｎ型ベース層２、層２に隣
接して層２との間にｐｎ接合を形成しアノード電極６に
達するストライプ状のｐ＋型層３および層３よりも薄く
て低濃度のｐ型層４を有し、少くとも層２の概略１ｏで
示す領域には金（Ａｕ）がドープされている１これによ
って半導体基体内に、ｎ層層の第１の部分ｌａ、ｎ層の
第１の部分２ｂ及び９層４とで構成され７’（第１の積
層構造部Ｉと、ｎ層層の第２の部分１ｂ、ｎ層の第２の
部分２ｂ、ｐ＋層３とで構成され第１の積層構造部Ｉを
包囲する第２の積層構造部■とが形成される。一方の主
表面１０２に露出するｐｒｔ接合は、酸化膜９で保護さ
れている。In FIGS. 3 and 4, a pair of main surfaces 101 and 1
02, between a pair of main surfaces,
n-type layer 1, layer 1 in ohmic contact with cathode electrode 5
an n-type base layer 2 adjacent to and having a lower concentration than the layer 2, a striped p+ type layer 3 adjacent to the layer 2 forming a pn junction with the layer 2 and reaching the anode electrode 6; has a lightly doped p-type layer 4 and is doped with gold (Au) at least in the region indicated generally at 1o of layer 21. , the first part 2b of the n-layer and the nine-layer 4 7' (the first laminated structure part I, the second part 1b of the n-layer, the second part 2b of the n-layer, the p+ layer 3 and a second laminated structure part (2) surrounding the first laminated structure part I is formed.The prt junction exposed on one main surface 102 is protected by an oxide film 9.
この実癩例装置の半導体基体は一辺が約４震の正方形状
である。この装置は周知の半導体製造技術を用いて作製
し得る。その−例を概略説明すれば次の通りである。The semiconductor substrate of this leprosy example device has a square shape of approximately 4 squares on each side. This device can be fabricated using well-known semiconductor manufacturing techniques. An example of this will be briefly explained as follows.
まず、ｎ＋型のシリコン単結晶ウェハを準備し、その一
方面全面に約６Ω確の抵抗率のｎ型シリコン単結晶層を
約１５μｍの厚さにエピタキシャル成長する。これをシ
リコン基板とする。次に、リン（Ｉ） ）を単結晶ウェ
ハの他方面から選択的に将来ペレタイズされたとき半導
体基体周縁となる個所に拡散して他方面に露出しかつエ
ピタキシャル成長したｎ＋層に連らなるｎ１型層を形成
する。First, an n+ type silicon single crystal wafer is prepared, and an n type silicon single crystal layer having a resistivity of about 6 Ω is epitaxially grown on the entire surface of the wafer to a thickness of about 15 μm. This is used as a silicon substrate. Next, phosphorus (I) is selectively diffused from the other side of the single crystal wafer into the area that will become the periphery of the semiconductor substrate when it is pelletized in the future, and is exposed on the other side and continues to the epitaxially grown n+ layer. form a layer.
次に、単結晶ウェハの他方面から酸化膜をマスクとして
ほう素（Ｂ ）を選択的に拡散してｐ＋型層３を約５μ
ｍの深さに形成する。更に他方面からほう素イオンを打
込み、熱処理を施してｐ型層４を形成する。続いてエピ
タキシャル成長したｎ＋層表面に金を蒸着し、約９１５
Ｃで２０分熱処理して金をシリコン基板１００内に拡散
させる。次に、シリコン基板１００の両面の所定部に例
えばｋｔ８ ｉ、またはｃｒ−Ｎｉ−Ａｇの積層膜を蒸
着してアノード電極６およびカソード電極５を形成する
。なお、８１０２膜９は上述した拡散工程で、あるいは
別途ＣＶＤ法等により堆積される。Next, boron (B) is selectively diffused from the other side of the single crystal wafer using the oxide film as a mask to form a p+ type layer 3 of about 5 μm.
Form to a depth of m. Further, boron ions are implanted from the other side and heat treatment is performed to form the p-type layer 4. Subsequently, gold was deposited on the surface of the epitaxially grown n+ layer to a thickness of approximately 915 nm.
Gold is diffused into the silicon substrate 100 by heat treatment at C for 20 minutes. Next, a laminated film of, for example, kt8i or cr-Ni-Ag is deposited on predetermined portions of both surfaces of the silicon substrate 100 to form the anode electrode 6 and the cathode electrode 5. Note that the 8102 film 9 is deposited by the above-mentioned diffusion process or by a separate CVD method.
この装置のアノード・カソード両電極間にアノード電極
６がカソード電極５に対して正の電位となるような屯田
を刃口えると、ｐｎｎ＋ｎｎ外ら成る第１の積層構造部
■に順電流の殆んどが流れる。When a field is inserted between the anode and cathode electrodes of this device so that the anode electrode 6 has a positive potential with respect to the cathode electrode 5, most of the forward current flows to the first laminated structure part (2) consisting of pnn+nn. The water flows.
次に両電極間にカソード電極５がアノード電極６に対し
て正の電位となるよりな重圧を加えると、第２の積層構
造部■のｐ＋ ｎ 接合７から空乏層が第１の積層構
造部ｌｌｌ１ｌｌに伸び、第１の積ｊ−構造部Ｉの１０
で示した領域（以下チャネル部と称す）をピンチオフし
逆電圧が阻止される。本実Ｉ４ｉ例では、チャネルＳＦ
（１０の抵抗率は金をドープしたことによるキャリヤ補
償作用により、もとのエピタキシャル成長層の抵抗率よ
りも高くなっており、約５００Ωｍである。耐圧の高い
ｐ＋ ｎ接合７が逆電圧を阻止するので、ｐ型層４とｎ
型層２０間のｐｎ接合１１を、高耐圧化と一般に相反す
る高速低損失化の面のみから設計できる。本実施例では
ｐ型層４の厚さを約１μｍと薄くかつ不純物濃度を低く
しである。このようにすると、順方向動作時にｎ型ベー
ス層２へのキャリヤ注入量が少くなり、このため高速化
と共に、ｐｎ接合１１に印加される接合域圧が低くなっ
て低損失化が図れる。Next, when more pressure is applied between the two electrodes so that the cathode electrode 5 has a positive potential with respect to the anode electrode 6, the depletion layer flows from the p+ n junction 7 of the second laminated structure part 2 to the first laminated structure part. lll1ll, first product j - 10 of structure I
By pinching off the region shown in (hereinafter referred to as channel section), reverse voltage is blocked. In the real I4i example, channel SF
(The resistivity of 10 is higher than the resistivity of the original epitaxial growth layer due to the carrier compensation effect caused by doping with gold, and is about 500 Ωm.The high withstand voltage p+n junction 7 prevents reverse voltage. Therefore, p-type layer 4 and n
The pn junction 11 between the mold layers 20 can be designed only from the viewpoint of high speed and low loss, which are generally contradictory to high breakdown voltage. In this embodiment, the thickness of the p-type layer 4 is as thin as about 1 μm, and the impurity concentration is low. In this way, the amount of carriers injected into the n-type base layer 2 during forward operation is reduced, and as a result, the speed is increased and the junction region pressure applied to the pn junction 11 is lowered, resulting in lower loss.
第５図及び第６図にｐ型層４０表面不純物損度Ｎａｐに
対する順電圧降下と逆回復時間ｔ□との関係を示すが、
Ｎｓｐを１０１！１Ｃ１ｎ匂のオーダーにすると、通常
の１０”ｃｍ−”のオーダーに比べて順電圧が約０．１
ｖ減となり低損失に、またｔ ｒｒが約１／３〜１／４
と高速になることがわかる。FIGS. 5 and 6 show the relationship between the forward voltage drop and the reverse recovery time t□ with respect to the surface impurity loss Nap of the p-type layer 40.
If Nsp is on the order of 101!1C1n, the forward voltage will be about 0.1 compared to the normal order of 10"cm-".
V is reduced, resulting in low loss, and trr is approximately 1/3 to 1/4
You can see that it becomes faster.
第７図に、本実施例装置の嶋流密度１００Ａ／ｃｒｉ、
での順電圧降下を示す。チャネル部１００幅Ｗを狭くす
ると順電圧降下が高くなるが、その増加の割合は顕著で
なく、高さ０．０２Ｖ程度であり低損失性を保つ。これ
に対し、第８図に示すように、逆阻止′醒圧はチャネル
幅Ｗを狭くすると大幅に上昇する。Ｗが３０μｍ程度の
ときには逆阻止電圧がｐｎｎ＋接合１１で決る値を持つ
が、Ｗが２２μｍより小さくなるとｐ＋ ｎ接合７の静
電効果が現れ（９）
て逆阻市′ポ圧が上昇しはじめる。Ｗが１２μｍになる
と逆阻止電圧が１５０■と高くなり十分な効果が得られ
る。FIG. 7 shows the island flow density of the device of this embodiment, 100 A/cri,
shows the forward voltage drop at When the width W of the channel portion 100 is narrowed, the forward voltage drop increases, but the rate of increase is not significant and the height is about 0.02 V, maintaining low loss. On the other hand, as shown in FIG. 8, the reverse blocking pressure rises significantly when the channel width W is narrowed. When W is about 30 μm, the reverse blocking voltage has a value determined by the pnn+ junction 11, but when W becomes smaller than 22 μm, the electrostatic effect of the p+ n junction 7 appears (9) and the reverse blocking voltage begins to rise. . When W is 12 μm, the reverse blocking voltage becomes as high as 150 μm, and a sufficient effect can be obtained.
静電効果が現れるチャネル幅及び十分な効果が得られる
チャネル幅はチャネル部１０の抵抗率に依存し、抵抗率
が高くなる程広くなる。第９図はこの関係を示した図で
ある。チャネル部１０の抵抗率は、エピタキシャル層の
抵抗率と金などのキャリヤ補償作用を起す不純物の拡散
温度を制御して調節できる。The channel width at which the electrostatic effect appears and the channel width at which a sufficient effect is obtained depend on the resistivity of the channel portion 10, and the higher the resistivity, the wider the channel width becomes. FIG. 9 is a diagram showing this relationship. The resistivity of the channel portion 10 can be adjusted by controlling the resistivity of the epitaxial layer and the diffusion temperature of an impurity such as gold that causes a carrier compensation effect.
第９図で実線で示す２１．２２は本実施例のように半導
体層２がｎ型の場合、破線で示す３１゜３２は本実施例
とはｐｍ、ｎ型領域が全て逆になり、層２がｐ型の場合
である。このように、ｐ型。21.22 shown by a solid line in FIG. 9 is an n-type semiconductor layer 2 as in this embodiment, and 31° 32 shown by a broken line is a layer in which the pm and n-type regions are all reversed from this embodiment. 2 is a p-type case. In this way, p-type.
ｎ型を逆にしても本実姉例と同様の効果が得られる。２
１．３１は静電効果が現れて逆阻止電圧が上りはじめる
チャネル幅を表し、２２．３２は十分な効果を得られる
チャネル幅を示す。この図かられかるように、チャネル
幅を容易に実現できる寸法として３μｍ以上とすると、
層２がｎ型の場（１０）
合にはチャネル部の抵抗率が９Ωｍ以上で逆阻止電圧上
昇の効果を得られ、３３Ω口以上で１５０■以上の高耐
圧と十分な効果を得られる。層２がｐ型の場合には、対
応する抵抗率はそれぞれ２７Ωｍ及び１００Ω鋸である
。Even if the n-type is reversed, the same effect as in this example can be obtained. 2
1.31 represents the channel width at which the electrostatic effect appears and the reverse blocking voltage begins to rise, and 22.32 represents the channel width at which a sufficient effect can be obtained. As can be seen from this figure, if the channel width is set to 3 μm or more as a dimension that can be easily realized,
When the layer 2 is n-type (10), the effect of increasing the reverse blocking voltage can be obtained when the resistivity of the channel portion is 9 Ωm or more, and the sufficient effect of a high breakdown voltage of 150 μm or more can be obtained when the resistivity of the channel portion is 33 Ω or more. If layer 2 is p-type, the corresponding resistivities are 27 Ωm and 100 Ωm, respectively.
第１０図は本発明の他の実施例の断面構造図であり、第
４図と同じところは、同じ符号で示しである。本実施例
が第３図及び第４図の実施例と異なるところは、第１の
積層構造部Ｉにおいて、ｐ型層４がなく、ｎ型層２とア
ノード電極６の間にショットキバリヤ１２が形成されて
いる点にある。FIG. 10 is a cross-sectional structural diagram of another embodiment of the present invention, and the same parts as in FIG. 4 are indicated by the same symbols. This embodiment differs from the embodiments shown in FIGS. 3 and 4 in that in the first stacked structure portion I, there is no p-type layer 4, and a Schottky barrier 12 is provided between the n-type layer 2 and the anode electrode 6. It is at the point where it is formed.
この構造では、主電流通路の接合がｐｎ接合でなくショ
ットキ接合なので第３図及び第４図の実施例の場合よシ
も高速かつ低損失になり、高耐圧化については光の実姉
例と同様の効果が得られる。In this structure, the junction of the main current path is not a pn junction but a Schottky junction, so it has higher speed and lower loss than the embodiments shown in Figs. 3 and 4, and the high breakdown voltage is similar to the optical sister example. The effect of this can be obtained.
第１１図に、このような構造で逆阻止電圧が上りはじめ
るチャネル幅とチャネル部抵抗率の関係４１．５１と１
５０Ｖの高耐圧を得られるチャネル幅とチャネル部抵抗
率の関係４２．５２を示す。Figure 11 shows the relationship 41.51 and 1 between channel width and channel resistivity at which the reverse blocking voltage begins to rise in such a structure.
The relationship 42.52 between the channel width and the channel resistivity that allows a high breakdown voltage of 50V to be obtained is shown.
４１．４２は層２が本実施例のようにｎ型の場合、（１
１）
５１．５２は第１０図の構造とｐ型、ｎ型を反転し、層
２がｐ型の場合である１図示のように、層２がｎ型の場
合、チャネル部の抵抗率が９Ωｍ以上で逆阻止電圧上昇
の効果を得られ、１６６Ω画以上で十分な効果が得られ
る。層２がｐ型の場合、対応する抵抗率はそれぞれ２７
Ωｚ、５ｏｏΩｃｎ１である。41.42 is (1
1) 51.52 is the case where the p-type and n-type are reversed from the structure in Figure 10, and the layer 2 is the p-type.1 As shown in the figure, when the layer 2 is the n-type, the resistivity of the channel part is At 9 Ωm or more, the effect of increasing the reverse blocking voltage can be obtained, and at 166 Ωm or more, a sufficient effect can be obtained. If layer 2 is p-type, the corresponding resistivity is 27
Ωz, 5ooΩcn1.
第１２図は本発明の更に他の実症例による断面構造図で
ある。本実施例が第３図及び第４図の実施例と異なると
ころは半導体層４がｐ型ではなくｎ＋型であり、層２が
層４を介してアノード電極６にオーム性の接続をしてい
る点にある。この構造では第１の積層構造部Ｉに整流性
の接合がないので、高耐圧を出すのは難しいが、より高
速低損失の素子が得られる利点がある。チャネル幅が広
いと整流性が得られにくいが、チャネル幅を狭くすると
整流効果が現れる。FIG. 12 is a cross-sectional structural diagram of still another actual case of the present invention. This embodiment differs from the embodiments shown in FIGS. 3 and 4 in that the semiconductor layer 4 is of the n+ type instead of the p-type, and the layer 2 is ohmically connected to the anode electrode 6 through the layer 4. It is in the point where it is. In this structure, since there is no rectifying junction in the first laminated structure portion I, it is difficult to produce a high breakdown voltage, but it has the advantage of providing a higher speed and lower loss element. If the channel width is wide, it is difficult to obtain rectification, but if the channel width is narrowed, a rectification effect appears.
第１３図にチャネル幅とチャネル部抵抗率の関係を示す
。実線６１．６２は層２がｎ型の場合、破線７１．７２
は本実施例とｐ型、ｎ型を逆転し、（１２）
層２がｐ型になっている場合である。６１．７１は整流
ダイオードとして実用に供することのできる逆阻止電圧
５０Ｖを得られるチャネル幅、６２゜７２は１００■の
良好な逆阻止電圧を得られるチャネル幅を示す。図示の
ようにチャネル幅を実用的な加工寸法３μｍとして、層
２がｎ型の場合、チャネル部抵抗率が７１Ωロ以上、好
ましくは１．１００Ω口以上で良好な逆阻止覗圧を得ら
れる。FIG. 13 shows the relationship between channel width and channel resistivity. The solid line 61.62 is the dashed line 71.72 when layer 2 is n-type.
(12) This is the case where the p-type and n-type are reversed from the present embodiment, and the layer 2 is of the p-type. 61.71 indicates a channel width at which a reverse blocking voltage of 50 V can be obtained that can be used practically as a rectifier diode, and 62°72 indicates a channel width at which a good reverse blocking voltage of 100 μ can be obtained. As shown in the figure, when the channel width is set to a practical processing dimension of 3 μm and the layer 2 is of n-type, a good reverse blocking pressure can be obtained when the channel resistivity is 71Ω or more, preferably 1.100Ω or more.
層２がｐ型の場合、対応する抵抗率はそれぞれ２１０Ω
ｃｎｒ 、 ３，３００Ωｍである。If layer 2 is p-type, the corresponding resistivity is 210Ω, respectively.
cnr, 3,300 Ωm.
以上、本発明を特定の実施例について説明したが、本発
明はこれらに限られることなく、例えば、キャリヤ補償
作用を起す不純物として全以外のものを用いる場合にも
適用することができる。例えば白金を用いることができ
、この場合キャリヤ補償作用が弱いのでドープ前の層２
の抵抗率を高くすることを要求されるが、金を用いた場
合よりも逆漏れ電流が少いという効果がある。もちろん
キャリヤ補償作用を引起すものであれば他の不純物をド
ープしても良く、また、例えば放射線照射等（１３）
によって導入された格子欠陥等を利用しても良い。Although the present invention has been described above with reference to specific embodiments, the present invention is not limited thereto, and can be applied, for example, to cases where impurities other than pure are used as the impurity that causes the carrier compensation effect. For example, platinum can be used; in this case, since the carrier compensation effect is weak, the layer 2 before doping can be used.
Although it is required to have a high resistivity, it has the effect of lower reverse leakage current than when gold is used. Of course, other impurities may be doped as long as they cause a carrier compensation effect, and lattice defects introduced by, for example, radiation irradiation (13) may also be used.
また、素子の構造も第３図、第４図、第１０図。The structure of the element is also shown in FIGS. 3, 4, and 10.
第１２図の第１の積層構造部Ｉがストライプ状でも良い
し、それ以外、例えば、円形、角形９曲線状で第２の積
層構造部■がそれを包囲するようにしてもよい。The first laminated structure I in FIG. 12 may have a striped shape, or it may have another shape, such as a circle or a rectangular curved shape, and the second laminated structure I surrounds it.
以上説明したように本発明によれば、高速、低損失、高
耐圧の特性を。つ半導体整流装置を容易に製造すること
ができる。As explained above, according to the present invention, the characteristics of high speed, low loss, and high withstand voltage are achieved. A semiconductor rectifier can be easily manufactured.
第１図及び第２図は従来例の整流ダイオードの断面構造
図、第３図及び第４図は本発明の一実施例の構造を示す
概略図、第５図ないし第８図は本発明の一長施例の特性
を説明するための各種特性図、第９図は本発明の一実施
例の構造による効果を説明するだめの図、第１０図は他
の実施例の構造を示す概略図、第１１図は他の実施例の
構造による効果を説明するだめの図、第１２図は本発明
のさらに他の実砲例の構造を示す概略図、第１３（１４
）
図はこの実施例の構造による効果を説明するための図で
ある。
１・・・ｎ＋型層、２・・・ｎ型ベース層、３・・・ｐ
＋型層、５・・・カソード電極、６・・・アノード電極
、１０・・・チ（１５）
３５１−
第 乙 霞
（へン “［−７′□３ ＠ｕ【
Ｎ５Ｆ（ｃ／ｒｒＬ−３）
ナヤ辛）し 暢 Ｗ （）’机）
拓８図
午ヤ和し 幅 Ｗ （％帆）
午ヤキＪし都Ｊ艮Ｊた本 （え。１）
第 １０ 図
拓７１図
午ヤ午ｊし都右（Ｊ電車（几Ｃ叛）
菊 ／Ｚ 図
第 ／３ 関
ヂャ挙ル郵抵読十（Ａｃ恨）1 and 2 are cross-sectional structural diagrams of conventional rectifier diodes, FIGS. 3 and 4 are schematic diagrams showing the structure of an embodiment of the present invention, and FIGS. Various characteristic diagrams for explaining the characteristics of the first embodiment, FIG. 9 is a diagram for explaining the effects of the structure of one embodiment of the present invention, and FIG. 10 is a schematic diagram showing the structure of another embodiment. , FIG. 11 is a diagram for explaining the effects of the structure of another embodiment, FIG. 12 is a schematic diagram showing the structure of still another example of the actual gun of the present invention, and FIG.
) The figure is a diagram for explaining the effects of the structure of this embodiment. 1...n+ type layer, 2...n type base layer, 3...p
+ type layer, 5... cathode electrode, 6... anode electrode, 10... chi (15) 351- No. Otsu Kasumi (Hen "[-7'□3 @u[ N5F(c/rrL- 3) Nayashin)shinobu W ()'Desk) Raku 8 drawing 71 illustrations width W (% sail) illustration 71 illustrations J Shito Right (J Train (几C 叛) Chrysanthemum /Z Diagram No. 3 Kanjiya Guru Post Resistance Reading Ten (Ac Grudge)
Claims (1)
両生表面にコンタクトする一対の主電極と金有し、半導
体基体は一方の主表面に隣接する一方導゛眠型の第１の
半導体層の第１の部分と、第１の半導体層に隣接し第１
の半導体層より低い不純物濃度を有する一方導成型の第
２の半導体層の第１の部分と、第２の半導体層の第１の
部分と他方の主表面に隣接し、第２の半導体層の第１の
部分との間にｐｎ接合を形成する他方導電屋の第３の半
導体層からなる一方の積層構造部と、第１の半導体層の
＄２の部分と、第２の半導体層の第２の部分とで形成さ
れ一方の積層構造部で包囲された他方の積層構造部とか
ら成９、他方の積層構造部は一方の積層構造部のｐｎ接
合を逆バイアスした時に生じる空乏層の拡がりによって
ピンチオフされる寸法形状となっており、かつ他方の積
層構造部の第２の半導体層の第２の部分の少くとも空乏
層によってピンチオンされる個所にはキャリヤ補償作用
を引起す手段が導入されていること’ｔ％徴とする半導
体整流装置。 ２、特許請求の範囲第１項において、他方の積層構造部
が、第２の半導体層の第２の部分及び他方の主表通に隣
接し、第２の半導体層の第２の部分との間にｐｎｎ金合
金形成第３の半導体層よりも低不純濃度でかつ厚さの薄
い他方導電型の第４の半導体層を有することを特徴とす
る半導体整流装置。 ３、ｔ￥ｉ許稍求の範囲第１項において、他方の積層構
造部の第２の半導体層の第２の部分が、主電極の一方と
整流性の接触をすることを特徴とする半導体整流装置。 ４、特許請求の範囲第１項において、他方の積層構造部
の第２の半導体層の第２の部分が、主電極の一方とオー
ム性の低抵抗接続をしていることを特徴とする半導体整
流装置。 ５、特許請求の範囲第４項において、他方の積層構造部
の第２の半導体層の第２の部分が、それよシも高不純物
製置の一方導電型の第５の半導体層を介して主１ＪＬ＆
の一方に低抵抗接続していることを特徴とする半導体整
流装置。 ６、％許請求の範囲第１項、第２項、第３項、第４項、
或いは第５項において、キャリヤ補償作用を有する手段
が、重金Ｆ４原子を含む不純物でおること全特徴とする
半導体！＠流装置。 ７、特許請求の範囲第１項、第２項、第３項、第４項、
或いは第５項において、キャリヤ補償作用を引起す手段
が半導体中の格子欠陥であることを特徴とする半導体整
流装置。[Scope of Claims] 1. A semiconductor substrate having a pair of main surfaces, a pair of main electrodes in contact with the bidirectional surfaces of the semiconductor substrate, and a metal, the semiconductor substrate being adjacent to one of the main surfaces. a first portion of the first semiconductor layer; and a first portion adjacent to the first semiconductor layer;
a first portion of a second semiconductor layer of one conductivity type having an impurity concentration lower than that of the semiconductor layer; One laminated structure part consists of a third semiconductor layer of the other conductive layer forming a pn junction with the first part, a $2 part of the first semiconductor layer, and a second part of the second semiconductor layer. 9, the other stacked structure is formed by the expansion of the depletion layer that occurs when the pn junction of one stacked structure is reverse biased. and a means for causing a carrier compensation effect is introduced at least at a portion of the second portion of the second semiconductor layer of the other stacked structure portion that is pinched off by the depletion layer. Semiconductor rectifier with 't% characteristics. 2. In claim 1, the other laminated structure portion is adjacent to the second portion of the second semiconductor layer and the other main street, and is connected to the second portion of the second semiconductor layer. A semiconductor rectifying device characterized by having a fourth semiconductor layer of the other conductivity type which has a lower impurity concentration and a thinner thickness than the pnn gold alloy formed third semiconductor layer between the layers. 3. Range of requirements for t￥i In item 1, the semiconductor is characterized in that the second portion of the second semiconductor layer of the other stacked structure portion is in rectifying contact with one of the main electrodes. Rectifier. 4. The semiconductor according to claim 1, wherein the second portion of the second semiconductor layer of the other laminated structure has an ohmic low resistance connection with one of the main electrodes. Rectifier. 5. In claim 4, the second portion of the second semiconductor layer of the other stacked structure is formed through a fifth semiconductor layer of one conductivity type which is also highly impurity-doped. Main 1JL&
A semiconductor rectifier characterized by a low resistance connection to one side of the rectifier. 6. Percentage Scope of Claims 1, 2, 3, 4,
Alternatively, in item 5, the semiconductor is characterized in that the means having a carrier compensation effect is an impurity containing a heavy metal F4 atom! @Flow device. 7. Claims 1, 2, 3, 4,
Alternatively, the semiconductor rectifier according to item 5, wherein the means for causing the carrier compensation effect is a lattice defect in the semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1603283A JPS59143370A (en) | 1983-02-04 | 1983-02-04 | Semiconductor rectifying device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1603283A JPS59143370A (en) | 1983-02-04 | 1983-02-04 | Semiconductor rectifying device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59143370A true JPS59143370A (en) | 1984-08-16 |
Family
ID=11905228
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1603283A Pending JPS59143370A (en) | 1983-02-04 | 1983-02-04 | Semiconductor rectifying device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59143370A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5017976A (en) * | 1988-12-02 | 1991-05-21 | Kabushiki Kaisha Toshiba | Semiconductor device having intermediate layer for pinching off conductive path during reverse bias application |
| EP0568269A2 (en) * | 1992-04-28 | 1993-11-03 | Mitsubishi Denki Kabushiki Kaisha | Diode and method for manufacturing the same |
| JP2006295062A (en) * | 2005-04-14 | 2006-10-26 | Rohm Co Ltd | Semiconductor device |
| US7932133B2 (en) | 2004-06-14 | 2011-04-26 | Tyco Electronics Corporation | Circuit protection method using diode with improved energy impulse rating |
-
1983
- 1983-02-04 JP JP1603283A patent/JPS59143370A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5017976A (en) * | 1988-12-02 | 1991-05-21 | Kabushiki Kaisha Toshiba | Semiconductor device having intermediate layer for pinching off conductive path during reverse bias application |
| EP0568269A2 (en) * | 1992-04-28 | 1993-11-03 | Mitsubishi Denki Kabushiki Kaisha | Diode and method for manufacturing the same |
| EP0568269A3 (en) * | 1992-04-28 | 1995-04-19 | Mitsubishi Electric Corp | Diode and method for manufacturing the same. |
| US7932133B2 (en) | 2004-06-14 | 2011-04-26 | Tyco Electronics Corporation | Circuit protection method using diode with improved energy impulse rating |
| JP2006295062A (en) * | 2005-04-14 | 2006-10-26 | Rohm Co Ltd | Semiconductor device |
| WO2006112291A1 (en) * | 2005-04-14 | 2006-10-26 | Rohm Co., Ltd. | Semiconductor device |
| US7535075B2 (en) | 2005-04-14 | 2009-05-19 | Rohm Co., Ltd. | Semiconductor device |
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