JPS59139624A - Heating method of sample - Google Patents
Heating method of sampleInfo
- Publication number
- JPS59139624A JPS59139624A JP1405483A JP1405483A JPS59139624A JP S59139624 A JPS59139624 A JP S59139624A JP 1405483 A JP1405483 A JP 1405483A JP 1405483 A JP1405483 A JP 1405483A JP S59139624 A JPS59139624 A JP S59139624A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- sample
- along
- edge
- per unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010438 heat treatment Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 title claims description 8
- 230000007423 decrease Effects 0.000 claims description 2
- 230000003247 decreasing effect Effects 0.000 abstract description 5
- 235000012431 wafers Nutrition 0.000 abstract 5
- 238000000137 annealing Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67115—Apparatus for thermal treatment mainly by radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体ウェハなどの試料に棒状の赤外線ランプ
によジ赤外線ビームを照射してウェハの加熱を行う方法
に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for heating a sample such as a semiconductor wafer by irradiating the sample with a di-infrared beam from a rod-shaped infrared lamp.
（ｂ） 技術の背景
例えばシリコンウェハ上に二酸化シリコン（Ｓｉ０２〕
等の絶縁膜を形成し、その上に多結晶シリコン層を形成
し、これにレーザビームやランプを用いたアニールを行
なって単結晶シリコン層を形成する技術が単結晶シリコ
ン層を多層に積層して構成される三次元（立体）集積回
路の製造において重要なものとなってくる。(b) Technical background For example, silicon dioxide (Si02) is deposited on a silicon wafer.
The technology involves forming an insulating film, forming a polycrystalline silicon layer on top of it, and annealing it using a laser beam or lamp to form a single-crystal silicon layer. This will become important in the production of three-dimensional (three-dimensional) integrated circuits composed of three-dimensional integrated circuits.
この際ウェハ全面に多結晶シリコン層を形成し、ウェハ
表面全体をカバーするような大きさの棒状ヒータ（ラン
プ）を走査してアニールすることによシ、結晶方位のそ
ろった大面積の単結晶シリコン領域が得られる。At this time, a polycrystalline silicon layer is formed on the entire surface of the wafer, and by scanning and annealing a rod-shaped heater (lamp) large enough to cover the entire wafer surface, a large-area single crystal with uniform crystal orientation can be formed. A silicon region is obtained.
（ｃ） 従来技術と問題点
従来のこのようなランプアニールのようすを第１図に示
す。(c) Prior art and problems FIG. 1 shows a conventional lamp annealing process.
同図（ａ）に示すように多結晶シリコン層が形成された
ウェハ１上を赤外線ランプによる線状のビーム２が矢印
の方向に走査する。これによシ多結晶シリコン層は加熱
され、溶融した後固化し単結晶化してゆく。As shown in FIG. 1A, a linear beam 2 from an infrared lamp scans in the direction of the arrow over a wafer 1 on which a polycrystalline silicon layer is formed. As a result, the polycrystalline silicon layer is heated, melted, and then solidified to become a single crystal.
従来はビーム２の強度および走査速度を一定としていた
。この時のウェハ内の位置に対するウェハ面の温度を同
図（ｂ）に示す。Conventionally, the intensity and scanning speed of the beam 2 were kept constant. The temperature of the wafer surface with respect to the position within the wafer at this time is shown in FIG. 4(b).
ウェハ１の温度はビームの輻射による温度分布成分（一
点鎖線３）と、ウェハ内（多結晶シリコンも含む）の熱
伝導による温度分布成分（破線４）とによシ実線５に示
す分布となる。The temperature of the wafer 1 has a distribution shown by a solid line 5, which is determined by a temperature distribution component due to beam radiation (dotted chain line 3) and a temperature distribution component due to heat conduction within the wafer (including polycrystalline silicon) (dashed line 4). .
すなわち、ウェハ上の走査終了位置方向にそって温度が
高くなっておシ、ウェハは過剰な加熱を受けることにな
る。That is, the temperature increases along the direction of the scanning end position on the wafer, and the wafer is subjected to excessive heating.
このような過剰アニールを行うとウェハの後半で単結晶
化されるべきシリコン層が剥離したシ、更に、三次回路
の場合、既に完成した下層のＬＳＩの素子特性を損った
シする。逆に、そのようなことが起こらない様に輻射強
度を下げると、今度は、ウェハの前半で充分なアニール
が行われなくなる。If such excessive annealing is performed, the silicon layer to be single-crystalized in the latter half of the wafer will be peeled off, and furthermore, in the case of a tertiary circuit, the device characteristics of the already completed underlying LSI will be impaired. Conversely, if the radiation intensity is lowered to prevent this from happening, sufficient annealing will not be performed in the first half of the wafer.
したがって、一定輻射強度で一定速度の走査では均一な
アニールは不可能である。Therefore, uniform annealing is not possible with constant radiation intensity and constant speed scanning.
（ｄ） 発明の目的
本発明は、従来のこのような欠点を解消し、ウェハを均
一に加熱することのできる加熱方法を提供することを目
的とする。(d) Object of the Invention It is an object of the present invention to provide a heating method that can eliminate these conventional drawbacks and uniformly heat a wafer.
（ｅ）発明の構成
上記目的を実現するための本発明は、試料上で該試料の
一端部から他端部へ線状ビームを歩査して該試料を加熱
する方法において、該試料に対する単位面積当シおよび
単位時間当シのビーム照射量を該他端部方向に沿って漸
次増大させた後減少させることを特徴とする。(e) Structure of the Invention To achieve the above object, the present invention provides a method for heating a sample by walking a linear beam from one end of the sample to the other end. It is characterized in that the beam irradiation amount per area and per unit time is gradually increased along the direction of the other end and then decreased.
（ｆ） 発明の実施例 第２図は本発明の詳細な説明する図である。(f) Examples of the invention FIG. 2 is a diagram explaining the present invention in detail.
第１の実施例としては、第２図に実線６で示すように、
ウェハの端部Ｂの方向に沿ってビームの強度を漸次減少
させる。As a first embodiment, as shown by the solid line 6 in FIG.
The intensity of the beam is gradually decreased along the direction of the edge B of the wafer.
これによって第１図に実線５で示す温度分布のかたより
を補償し、均一な温度分布を得ることができる。As a result, it is possible to compensate for the bias in the temperature distribution shown by the solid line 5 in FIG. 1, and to obtain a uniform temperature distribution.
第２の実施例としては、第２図に破線７で示すようにビ
ームの走査速度を端部Ｂの方向に沿って漸次増大させる
。In a second embodiment, the scanning speed of the beam is gradually increased along the direction of the end B, as indicated by the broken line 7 in FIG.
これら第１．第２の実施例はつまシウエハの単位面積に
対する単位時間当シのビームの照射量をウェハの端部Ｂ
の方向に沿って初め僅か増加させ、次に漸次減少させて
いることになる。これによシ、ウェハ面内の温度分布を
均一化することができる。These first. In the second embodiment, the amount of beam irradiation per unit time per unit area of the wafer is calculated from the edge B of the wafer.
At first, it increases slightly along the direction of , and then gradually decreases. This makes it possible to make the temperature distribution within the wafer surface uniform.
（ｇ） 発明の詳細
な説明したように本発明によればウェハ内の温度分布を
均一にすることができ、従って多結晶シリコンを単結晶
化する場合には、ウェハ全面にわたって均一、同質の単
結晶シリコン層が得られる。又照射量はウェハの到る所
、必要最小限に出来るから、三次元回路の下層ＬＳＩの
素子を熱的に破損するおそれもない。(g) As described in detail, according to the present invention, the temperature distribution within the wafer can be made uniform, and therefore, when polycrystalline silicon is made into a single crystal, uniform and homogeneous single crystals can be formed over the entire surface of the wafer. A crystalline silicon layer is obtained. Furthermore, since the amount of irradiation can be kept to the minimum required everywhere on the wafer, there is no risk of thermally damaging the underlying LSI elements of the three-dimensional circuit.
第１図は従来の加熱方法を説明するための図、第２図は
本発明の詳細な説明するための図である０
図において、１はウェハ、２はビーム、６はウェハ上で
のビームの強度分布を示す線、７はウェハ上でのビーム
の走査速度の変化を示す線である。Fig. 1 is a diagram for explaining the conventional heating method, and Fig. 2 is a diagram for explaining the present invention in detail. In the figures, 1 is a wafer, 2 is a beam, and 6 is a beam on the wafer. A line 7 indicates the intensity distribution of the beam, and a line 7 indicates the change in the beam scanning speed on the wafer.
Claims (1)
して該試料を加熱する方法において、該試料に対する単
位面積自フおよび単位時間車シのビーム照射量を該他端
部方向に沿って両次増大させた後減少させること全特徴
とする試料の加熱方法０In a method of heating a sample by scanning a linear beam from one end of the sample to the other end of the sample, the amount of beam irradiation on the sample per unit area and per unit time is determined in the direction of the other end. A method of heating a sample characterized by bidimensional increase and then decrease along 0
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1405483A JPS59139624A (en) | 1983-01-31 | 1983-01-31 | Heating method of sample |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1405483A JPS59139624A (en) | 1983-01-31 | 1983-01-31 | Heating method of sample |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59139624A true JPS59139624A (en) | 1984-08-10 |
| JPH0454964B2 JPH0454964B2 (en) | 1992-09-01 |
Family
ID=11850370
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1405483A Granted JPS59139624A (en) | 1983-01-31 | 1983-01-31 | Heating method of sample |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59139624A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8314360B2 (en) * | 2005-09-26 | 2012-11-20 | Ultratech, Inc. | Apparatuses and methods for irradiating a substrate to avoid substrate edge damage |
| US11465141B2 (en) | 2016-09-23 | 2022-10-11 | Alveo Technologies, Inc. | Methods and compositions for detecting analytes |
| US11473128B2 (en) | 2014-10-06 | 2022-10-18 | Alveo Technologies, Inc. | System and method for detection of nucleic acids |
-
1983
- 1983-01-31 JP JP1405483A patent/JPS59139624A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8314360B2 (en) * | 2005-09-26 | 2012-11-20 | Ultratech, Inc. | Apparatuses and methods for irradiating a substrate to avoid substrate edge damage |
| US11473128B2 (en) | 2014-10-06 | 2022-10-18 | Alveo Technologies, Inc. | System and method for detection of nucleic acids |
| US11465141B2 (en) | 2016-09-23 | 2022-10-11 | Alveo Technologies, Inc. | Methods and compositions for detecting analytes |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0454964B2 (en) | 1992-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6412088B2 (en) | ||
| WO1993019484A1 (en) | Rapid thermal annealing using thermally conductive overcoat | |
| JPS58223320A (en) | Diffusing method for impurity | |
| JPH0410216B2 (en) | ||
| US4737233A (en) | Method for making semiconductor crystal films | |
| JPS59139624A (en) | Heating method of sample | |
| JPH0419698B2 (en) | ||
| JPH0377657B2 (en) | ||
| JPS61116820A (en) | Annealing method for semiconductor | |
| JPH027415A (en) | Formation of soi thin film | |
| JPH0883766A (en) | Method for crystallizing amorphous silicon and manufacture of thin film transistor | |
| JPH0420254B2 (en) | ||
| JPH025295B2 (en) | ||
| JPS58139423A (en) | Lateral epitaxial growing method | |
| JPH07107894B2 (en) | Annealing method for polycrystalline thin film substrate | |
| JPS5833822A (en) | Preparation of semiconductor substrate | |
| JPS5983993A (en) | Growth of semiconductor layer of single crystal | |
| JPH03280418A (en) | Manufacture of semiconductor film | |
| JPS59121823A (en) | Fabrication of single crystal silicon film | |
| JPH0453124A (en) | Manufacture and apparatus for single-crystal silicon thin film | |
| JPH0351091B2 (en) | ||
| JPS5835917A (en) | Manufacture of semiconductor device | |
| JPH02260526A (en) | Crystalline semiconductor film and formation thereof | |
| JPH027414A (en) | Formation of soi thin film | |
| JPH01147825A (en) | Manufacture of semiconductor device |