JPS59127839A - Inactivation of surface of iv-v group element compound semiconductor - Google Patents
Inactivation of surface of iv-v group element compound semiconductorInfo
- Publication number
- JPS59127839A JPS59127839A JP268283A JP268283A JPS59127839A JP S59127839 A JPS59127839 A JP S59127839A JP 268283 A JP268283 A JP 268283A JP 268283 A JP268283 A JP 268283A JP S59127839 A JPS59127839 A JP S59127839A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- group element
- compound semiconductor
- group
- iii
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 150000001875 compounds Chemical class 0.000 title claims abstract description 23
- 230000002779 inactivation Effects 0.000 title 1
- 239000010408 film Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000010409 thin film Substances 0.000 claims abstract description 11
- 229910021478 group 5 element Inorganic materials 0.000 claims description 6
- 230000000415 inactivating effect Effects 0.000 claims description 5
- 230000007547 defect Effects 0.000 abstract description 10
- 238000000151 deposition Methods 0.000 abstract description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 11
- 238000002161 passivation Methods 0.000 description 5
- 229910005540 GaP Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 241000981595 Zoysia japonica Species 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- ZZUFCTLCJUWOSV-UHFFFAOYSA-N furosemide Chemical compound C1=C(Cl)C(S(=O)(=O)N)=CC(C(O)=O)=C1NCC1=CC=CO1 ZZUFCTLCJUWOSV-UHFFFAOYSA-N 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、ｌ Ｖｋ化合物半導体表面の不活性化法に
関するものである。Ｉ−Ｖｋ化合物半導体は、光愼龍累
子あるいはマイクロ波素子材料として大いに活用されて
いるが、Ｓｉ半導体における熱酸化によるＳ ｉＵｚ腺
のような良好な界面特性を示す表面不活性化膜は得られ
ていなム。ｉ −ｖ化合物半導体衆面の不活性化法とし
て酸化法と絶縁物准槓法の２棟類に大別されるが、いず
れの方法でも、表面では、Ｖ族元素が選択的に欠乏し易
いために、不活性化膜（絶縁膜）／半導体界面には、多
くのＶＭ欠陥が存在し、それに起因するｌ１ｉＩｉ循度
の界面局在準位が形成される。このような界面局在準位
は、通常Ｉ Ｑ１２（ＩＩＩ ２ｅ〜−１以上と尚密度
であるために、半導体表面の７工ルミ準位を固定して、
半導体の表面ポテンシャルを形成する。この表面ポテン
シャルは、絶縁膜上に金属電極を形成した金属／絶縁膜
／半導体（ＭＩＤ）ダイオードに外部電圧を印加するこ
とによって変化させることが可能であるが、＾ｖｆｊ度
に存在する界面局在準位のために、制御できる表面ポテ
ンシャルの範囲は限られてしまう。−例として砒化ガリ
ウム（Ｉ族がガリウム、Ｖ族が砒素）半導体について説
明する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for passivating a lVk compound semiconductor surface. I-Vk compound semiconductors are widely used as microwave device materials, but surface passivation films that exhibit good interfacial properties such as SiUz glands produced by thermal oxidation in Si semiconductors have not been obtained. I haven't been able to do it. Methods for passivating large surfaces of i-v compound semiconductors are broadly divided into two types: oxidation methods and insulator deposition methods, but with either method, group V elements tend to be selectively depleted on the surface. Therefore, many VM defects exist at the passivation film (insulating film)/semiconductor interface, and a localized level at the interface with l1iIi circulation is formed due to this. Since such interface localized levels are usually dense at IQ12(III2e~-1 or higher), the 7-luminium level on the semiconductor surface is fixed,
Forms the surface potential of the semiconductor. This surface potential can be changed by applying an external voltage to a metal/insulating film/semiconductor (MID) diode with a metal electrode formed on an insulating film, but it is possible to Due to the level, the range of surface potential that can be controlled is limited. - As an example, a gallium arsenide (I group is gallium, V group is arsenic) semiconductor will be explained.
砒化ガリウム半導体表面において、Ｖ族元素の砒素が選
択的に欠乏した際、砒素欠陥に起因する界面局在準位は
半導体県制帝中の１ｄｔｉ′ｉｌＣ子帝端から測って０
．５〜０．７ｅＶの位置、すなわち県制帝のほぼ中央に
立直している。従ってｎ型尋電性の砒化ガリウムでは、
ＩＨ図に示すように、高密度の界−１局在準位の位置に
、７工ルミ準位が置屋されてし筐うため表面のバンドは
、上向きに曲がり、第１図に示した表面ポテンシャルを
生じさせる。かかる状態でＭＩ８ダイオードを作製し、
容量対電圧特性を測定すると、第２図に示すように、正
電圧側、すなわち、絶縁膜／半導体界面に電子を蓄積さ
せる領域において著しい周波数依存性を示し、高周波に
なる程、容量の印加電圧に対する変化が小さくなる。こ
の事は、高周波になるほど、第１図に示した底面ポテン
シャルの制御が困難になることを意味し、例えばＭＩ８
ゲート型電界効果トランジスタの特性上好ましくない。When arsenic, a group V element, is selectively depleted on the surface of a gallium arsenide semiconductor, the localized interface level due to arsenic defects will be 0 as measured from the 1dti'ilC end of the semiconductor prefecture.
．． It has been restored to a position of 5 to 0.7 eV, approximately at the center of the prefectural system. Therefore, for n-type gallium arsenide,
As shown in the IH diagram, the 7-luminium level is placed and housed at the position of the high-density field-1 localized level, so the band on the surface curves upward, resulting in the surface shown in Figure 1. Generate potential. An MI8 diode was manufactured in such a state,
When measuring the capacitance versus voltage characteristics, as shown in Figure 2, there is a significant frequency dependence on the positive voltage side, that is, the region where electrons are accumulated at the insulating film/semiconductor interface, and the higher the frequency, the greater the applied voltage of the capacitor. The change in will be smaller. This means that the higher the frequency, the more difficult it becomes to control the bottom potential shown in Figure 1. For example, MI8
This is unfavorable due to the characteristics of gate type field effect transistors.
゛
従うて本発明の目的は、従来、高密度の界面局在準位の
ために、制御できる表面ポテンシャルの範囲が一義的に
定められていたものを改良し、表面ポテンシャルの制御
範囲を拡大するＩ−Ｖ族化合物半導体表面の不活性化法
ｔ−提供することである。Therefore, the purpose of the present invention is to improve the conventional method in which the range of surface potential that can be controlled is uniquely determined due to the high density of interface localized levels, and to expand the control range of surface potential. An object of the present invention is to provide a method for passivating a surface of a group IV compound semiconductor.
本発明は、ｖ族元素としてＶｌから構成されるＡｆｌの
１ｔ−ｖ族化合物半導体上に、ｖＨ元累としてｖｌとは
異なるｖ２から構成される第２の１−Ｖ族化付物半導体
薄膜を成長させた後、第２の半導体表面上に絶縁膜を堆
積することを特徴とする蓋−Ｖ族化合物半導体表面の不
活性化法であり、かつ、第２のＩ−Ｖ族化合物半導体薄
膜の厚さｄがであることを特徴とする。ただし、（１）
式において、εいε８は各々、真空肪電卓、第２の半導
体の相対特電率、ｋはポルツマ／定数、Ｖは絶対ｔＩＡ
度、へ、ｎｉは各々、第２の半導体薄膜のキャリア一度
、ｑは単位電荷である。The present invention provides a second 1-V group compound semiconductor thin film composed of v2, which is different from vl, as a vH element, on an Afl 1t-v group compound semiconductor composed of Vl as a V group element. A method for inactivating a lid-V group compound semiconductor surface, which is characterized by depositing an insulating film on the second semiconductor surface after growth, and inactivating the second I-V group compound semiconductor thin film. It is characterized in that the thickness d is . However, (1)
In the formula, ε8 is the vacuum fat calculator, the relative special electric constant of the second semiconductor, k is Portsma/constant, and V is the absolute tIA.
degree, h, and ni are the carriers of the second semiconductor thin film, respectively, and q is the unit charge.
以下、本発明の詳細な説明する。先にも述べている様に
、不活性化膜／Ｉ−Ｖ鉄半畳体界而に存面する高密度の
界面局在準位は一政に、Ｖ族元素の欠陥に起因している
ため、該ｖ秩冗累に対して例らかの制御ｔ−施こすこと
によって、界面局在準位の制御と同時に、表■ボテン／
ヤルのｉＪｕ御が期待できる。ドウ（１）ａｗ）とスミ
ス（Ｓｍｉ ｔｈ ）は、ジャーナル・オプ・バキュー
ム・サイエンス０アンド・テクノロジー１７巻１０２８
ページ（１９８０年）において、拙々のＩ−Ｖ族化合−
半導体表面のＶ族欠陥のエネルギー位ｔｔ’ｉ計算して
おり、半導体のイオン度と、Ｖ族の種類によってｖ＃ｃ
欠陥エネルギー位置が変化することを指摘している。The present invention will be explained in detail below. As stated earlier, the high density of interfacial localized levels that exist in the passivation film/I-V iron semiconducting world is caused by defects in group V elements. , by applying some kind of control to the v-chip redundancy, at the same time as controlling the interface localized level, the table ■ button /
You can expect a lot of iJu control. Doe (1) aw) and Smith (Smith), Journal of Vacuum Science and Technology, Volume 17, 1028
Page (1980), the unsophisticated group I-V compound -
The energy level tt'i of group V defects on the semiconductor surface is calculated, and v#c depends on the ionicity of the semiconductor and the type of group V.
It is pointed out that the defect energy position changes.
すなわち、本発明は、第１の半導体と不活性化膜の間に
第１の半導体とはＶ族の種類の異なる非常に薄い第２の
半導体を形成することによってみかけ上、半導体表面の
イオン度と■族欠陥エネルギー位置を変化させ、従って
、表向ポテンシャルの制御範囲を改醤することである。That is, the present invention reduces the apparent ionicity of the semiconductor surface by forming a very thin second semiconductor of a group V type different from that of the first semiconductor between the first semiconductor and the passivation film. The purpose is to change the energy position of group Ⅰ defects and, therefore, to change the control range of the surface potential.
そして、ｗＪ２の５−
半導体から成る薄膜の厚さは、ＭＩ８ダイオードを形成
した際に、少なくとも半導体空乏層が第１の半導体へ達
するために、（１）式を満たす必要て゛ある。The thickness of the thin film made of the 5-semiconductor wJ2 needs to satisfy equation (1) in order for at least the semiconductor depletion layer to reach the first semiconductor when forming the MI8 diode.
実施例として、先の従来例との比較のため、砒化ガリウ
ム半纏体について述べるが、他のＩ−Ｖ脹化合物半尋体
についても全＜ＩＷＩ休の効果が得られるのは１うまで
もない。ｎ型纒電性のｌＸｌ０”鋤４キャリア一度の砒
化ガリウム半導体表面を３Ｈｚ ８０＜ ＋ｆＨ２０＋
ずＨ２Ｏ２エツチング液で誂向エツチングを施こした後
、該砒化ガリウム上に、Ｖ族として燐から構成される燐
化インジウムガリウム、化学組成にしてＩｎ ｏ、４ｓ
Ｇａｏ、ａｘｋ’ ｋ（１１式ヲ満たす厚さとして約１
５０Ａ成及した。 しかる後、化学気相堆積法（ＣＶＬ
）法）によって二酸化シリコン膜を３６０℃で、約ｘｏ
ｏｏｉ 堆積した。第３図は、その断面図ｔ−＆わして
おり、図において１は、第１の半導体である砒化ガリウ
ム、２は第２の半導体から成る＃誂である燐化インジウ
ムガリウム、３は二酸化シリコン族である。牌化インジ
６−
ラムの場合、表面のＶ族欠陥によって生ずる界面局在準
位は、砒化ガリウムの場合とは異なり、禁制帯内の伝導
帯領に位置するために、ＭＩＳダイオードを形成した際
に、界面に電子の蓄積を誘起する表向ポテンシャルの形
成が容易に行なわれる。As an example, a gallium arsenide semi-solid body will be described for comparison with the prior art example, but it goes without saying that the effect of total<IWI rest can be obtained with other IV expansion compound semi-solid bodies. n-type conductive lXl0'' plow 4 carriers once gallium arsenide semiconductor surface at 3Hz 80< +fH20+
After performing directed etching with H2O2 etching solution, indium gallium phosphide, which is composed of phosphorus as the V group, and has a chemical composition of Ino, 4S, is applied to the gallium arsenide.
Gao, axk' k (approximately 1 as the thickness that satisfies formula 11)
Achieved 50A. After that, chemical vapor deposition (CVL)
) method) to form a silicon dioxide film at 360°C, approximately xo
ooi deposited. Figure 3 is a cross-sectional view of the same. In the figure, 1 is gallium arsenide which is the first semiconductor, 2 is indium gallium phosphide which is the second semiconductor, and 3 is silicon dioxide. It is a tribe. In the case of indi-6-lambide, the interface localized level caused by group V defects on the surface is located in the conduction band region within the forbidden band, unlike in the case of gallium arsenide. In addition, a surface potential that induces the accumulation of electrons at the interface is easily formed.
第４図は、第３図の？ｌｌｖ″ｌｔｉを用いてＭｉｄダ
イオード金作製した時の、外部印〃口電圧に対する、半
導体のバンド構造の変化金示したものである。第４図に
おいて１１％ １２は各々、第１の半導体である砒化ガ
リウムと第２の半導体である燐化インジウムガリウムの
バンド構造である。砒化ガリウムと燐化インジウムガリ
ウムとは、互いにｖ族元素が異なるために、価電子帯の
バンド不連続の方が伝導帯のバンド不連続より大きいた
めに、第４図のようなバンド構造となっている。第４図
（ａｌは、正電圧を印加した場合で、燐化インジウムガ
リウム半導体表面の■族欠陥が伝導帯辺くに存在するた
めに、容易に電子１４が界面に蓄積される。第４図（ｂ
ｌは、電圧を印加していない状態である。第４図（Ｃ）
は負電圧全印加した場合で、絶縁膜と１２との界面およ
び１２と１１との価電子帯バンド不連続による界面に正
孔１５が誘起される。第５図は、第４図に示した界面電
荷の挙動を谷童−電圧特性にまとめた結果を示している
が、明らかに正電圧側、つまり電子の蓄積領域での周波
数分散が小さくなっており、第２図に示したように、従
来の、碩化ガリウムに直做絶縁膜を形成した場合と比較
して者しく改善された。Is Figure 4 the same as Figure 3? This figure shows the change in the band structure of the semiconductor with respect to the external applied voltage when a Mid diode was fabricated using llv''lti. In Fig. 4, 11% and 12 are the first semiconductor, respectively. This is the band structure of gallium arsenide and indium gallium phosphide, which is the second semiconductor.Since gallium arsenide and indium gallium phosphide contain different group V elements, the band discontinuity in the valence band is closer to the conduction band. Since the band discontinuity is larger than that of the band discontinuity, the band structure is as shown in Figure 4. Since the electrons 14 are located nearby, the electrons 14 are easily accumulated at the interface.
1 is a state in which no voltage is applied. Figure 4 (C)
is the case where the full negative voltage is applied, and holes 15 are induced at the interface between the insulating film and 12 and at the interface between 12 and 11 due to the valence band discontinuity. Figure 5 shows the results of the interfacial charge behavior shown in Figure 4 summarized in terms of Tando-voltage characteristics, and it is clear that the frequency dispersion on the positive voltage side, that is, in the electron accumulation region, is smaller. As shown in FIG. 2, this is a significant improvement compared to the conventional case where a direct insulating film is formed on gallium oxide.
以上のように、本発明のＩ−Ｖ族化合物半導体表面の不
活性化法によれば、界面局在準位のエネルギー位ｔｆｔ
任意に制御することかり詣であるため、表面ポテンシャ
ルの制御範囲を任意に変化させることができるという利
点を有するために、例えばＭＩＤ型電界効果トランジス
タ等の素子に工業的価値が高い。As described above, according to the method for inactivating the surface of a group IV compound semiconductor of the present invention, the energy level tft of the localized interface level
Since it is possible to arbitrarily control the surface potential, it has the advantage of being able to arbitrarily change the control range of the surface potential, and therefore has high industrial value in devices such as MID field effect transistors.
第１図は、絶縁膜と半導体との界面に、界面局在準位の
存在する場合の半導体のバンド図を示している。第２図
は、砒化ガリウム半導体上に不油性化膜を形成したＭＩ
８ダイオードの容量−電圧特性である。第３図は本発明
による表面不活性化法であり、ｌは第１０Ｉ−Ｖ族化合
物半導体基板、２は１とはＶ族元素の異なる第２０厘〜
■族化合物半導体の薄膜、３は絶＆ｔｍである。ｗＪ４
図は、第３図の構成を用いたＭＩＳダイオードに外部電
圧を印加したときの半導体のバンド図を示していて、１
１％ １２は谷々、第ｌの半導体と第２の半導体のバン
ド図、１４．１５は各々、電子と止孔である。第５図は
、第３図のＷ成金用いたＭＩＳダイオードの容菫−電圧
特性である。
１（理人弁理上内原 晋
９−
第１図
８２図
第３図
第４図
手続補正書（自発）
特許庁長官 殿
１、事件の表示 昭和５８年 特許 願第２６８２
号２、発明の名称 １−Ｖ族化合物半導体表面の不
活性化法３、補正をする者
事件との関係 出 願 人東京都港区芝五
丁目３３番１号
４、代理人
〒１０８ 東京都港区芝五丁目３７番８号 住人三田
ビル５、補正の対象
明細書の発明の詳細な説明の楠
６、補正の内容
１）明細書第５頁１行目の「度、８は単位電荷である。
」を「度、真性キャリア濃度＝Ｉ）は単位電荷である。
」と補正する。
２）明細書簡６頁３行目の１必要であ」を脇要があ」と
補正する。
３）明細書簡７頁１行目の「ラムの場合」を「ラムガリ
ウムの場合」と補正する。
４）同１７行目の「欠陥が伝導帯」を「欠陥に起因する
界面局在準位が伝導帯」と補正する。
１８５−FIG. 1 shows a band diagram of a semiconductor when an interface localized level exists at the interface between an insulating film and a semiconductor. Figure 2 shows MI with an oil-resistant film formed on a gallium arsenide semiconductor.
This is the capacitance-voltage characteristic of 8 diodes. FIG. 3 shows the surface passivation method according to the present invention, where l is a 10th IV-V compound semiconductor substrate, 2 is a 20th to
Thin films of group Ⅰ compound semiconductors, 3 is an absolute &tm. wJ4
The figure shows the band diagram of the semiconductor when an external voltage is applied to the MIS diode using the configuration shown in FIG.
1% 12 is a valley, the band diagram of the 1st semiconductor and the 2nd semiconductor, 14.15 is an electron and a hole, respectively. FIG. 5 shows the violet-voltage characteristics of the MIS diode using the W alloy shown in FIG. 1 (Patent Attorney Susumu Kamiuchihara 9- Figure 1, 82, Figure 3, Figure 4, Procedural amendment (spontaneous) Commissioner of the Japan Patent Office 1, Indication of the case 1982 Patent Application No. 2682
No. 2, Title of the invention 1-Method for inactivating the surface of a group V compound semiconductor 3, Relationship to the amended case Applicant: 5-33-1-4 Shiba, Minato-ku, Tokyo, Agent: 108 Tokyo, Japan Resident Mita Building 5, 37-8 Shiba 5-chome, Minato-ku, Kusunoki 6, Detailed description of the invention in the specification subject to amendment, Contents of amendment 1) ``Degree, 8 is unit charge'' on page 5, line 1 of the specification. '' is corrected as ``degree, intrinsic carrier concentration = I) is a unit charge.''. 2) In the third line of page 6 of the letter of specification, amend ``1 is necessary'' to ``There is a side note.'' 3) "In the case of rum" in the first line of page 7 of the letter of specification is amended to "in the case of ram gallium." 4) Correct "the defect is the conduction band" in the 17th line to "the interface localized level caused by the defect is the conduction band". 185-
Claims (1)
体を構成するＶ族元素とは異なる種類のＶ族元素を含ん
で構成されるＩ −Ｖ族化合物半導体薄膜を なる厚さｄで形成した後、この半導体薄膜表面上に絶縁
膜を形成することを特徴とするＩ−Ｖ族化合物半導体表
面の不活性化法。[Claims] A group I-V compound semiconductor thin film containing a group V element different from the group V elements constituting the group 1-V compound semiconductor is formed on the surface of a group 1-V compound semiconductor. 1. A method for inactivating a surface of a group IV compound semiconductor, which comprises forming an insulating film on the surface of a semiconductor thin film after forming the semiconductor thin film to a thickness d.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP268283A JPS59127839A (en) | 1983-01-11 | 1983-01-11 | Inactivation of surface of iv-v group element compound semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP268283A JPS59127839A (en) | 1983-01-11 | 1983-01-11 | Inactivation of surface of iv-v group element compound semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59127839A true JPS59127839A (en) | 1984-07-23 |
Family
ID=11536061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP268283A Pending JPS59127839A (en) | 1983-01-11 | 1983-01-11 | Inactivation of surface of iv-v group element compound semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59127839A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54129886A (en) * | 1978-01-13 | 1979-10-08 | Western Electric Co | Semiconductor |
| JPS5723280A (en) * | 1980-07-18 | 1982-02-06 | Nippon Telegr & Teleph Corp <Ntt> | Field effect type light detector |
| JPS57211238A (en) * | 1981-06-22 | 1982-12-25 | Nec Corp | Semiconductor device |
| JPS59119869A (en) * | 1982-12-27 | 1984-07-11 | Fujitsu Ltd | Semiconductor device |
-
1983
- 1983-01-11 JP JP268283A patent/JPS59127839A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54129886A (en) * | 1978-01-13 | 1979-10-08 | Western Electric Co | Semiconductor |
| JPS5723280A (en) * | 1980-07-18 | 1982-02-06 | Nippon Telegr & Teleph Corp <Ntt> | Field effect type light detector |
| JPS57211238A (en) * | 1981-06-22 | 1982-12-25 | Nec Corp | Semiconductor device |
| JPS59119869A (en) * | 1982-12-27 | 1984-07-11 | Fujitsu Ltd | Semiconductor device |
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