JPS59127160A - Fault detecting system - Google Patents
Fault detecting systemInfo
- Publication number
- JPS59127160A JPS59127160A JP58001864A JP186483A JPS59127160A JP S59127160 A JPS59127160 A JP S59127160A JP 58001864 A JP58001864 A JP 58001864A JP 186483 A JP186483 A JP 186483A JP S59127160 A JPS59127160 A JP S59127160A
- Authority
- JP
- Japan
- Prior art keywords
- information
- fault
- reception
- transmission
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は障害検出方式、特に処理装置の動作を入出力情
報によって監視する障害検出方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fault detection method, and more particularly to a fault detection method for monitoring the operation of a processing device using input/output information.
従来の障害検出方式は、二つの処理装置を相互接続し、
一方が実稼働中は他方を待機させ実稼働中の処理装置か
らの情報を受信監視して異常を検出する。Traditional fault detection methods interconnect two processing units,
When one is in actual operation, the other is placed on standby and receives and monitors information from the processing device in actual operation to detect abnormalities.
従来の障害検出方式の一構成例を機能ブロック図により
第1図に示す、第1図において、実稼働中の処理装置(
μ子CPU)l QAと待機中の処理装置(CPU)I
QBとはそれぞれ情報送信部101A・l01B、情報
受信部102A・102B。An example of the configuration of a conventional failure detection method is shown in FIG. 1 as a functional block diagram.
μ child CPU) l QA and standby processing unit (CPU) I
QB means information transmitting sections 101A and 101B and information receiving sections 102A and 102B, respectively.
障害報告通知部103A・103B、 及び障害報告受
付部104A@104B’t”備え、それぞれの・送信
部は相手装置の受信部に、又通知部は受付部に接続され
る。ここで第1図及び第2図を参照して障害検出手順に
ついて説明する。第2図は第1図における障害検出手順
の一例を示すシーケンス図である。第1図の状態、即ち
CPUl0Aが稼動中のときは%CPUl0Aは送信部
101 Aから一定時間間隔で特定パターン符号PTを
CPUl0Bの受信部102Bに送る。CPUl0Bは
この符号PT受信から時間TMを計り、所定時限までに
前記符号PTが到来しないときは時限超過T。The system includes failure report notifying units 103A and 103B, and a failure report receiving unit 104A@104B't'', each of which has its transmitting unit connected to the receiving unit of the other device, and its notifying unit connected to the receiving unit.Here, FIG. The failure detection procedure will be explained with reference to FIG. 2. FIG. 2 is a sequence diagram showing an example of the failure detection procedure in FIG. CPU10A sends a specific pattern code PT from transmitting unit 101A to receiving unit 102B of CPU10B at fixed time intervals. CPU10B measures time TM from reception of this code PT, and if the code PT does not arrive by a predetermined time limit, the time limit is exceeded. T.
として障害検出する。CPUI OBが障害検出したと
き障害報告信号TRを通知部103BからCPUI O
Aの受付部104 Aに転送し、CPU10Aの状態の
解放・復旧を開始きせると共にCPUI OB自身の状
態を抹消し処理装置(CPU)の処理動作QCPUIO
BCPUl0B自身が通常である。このように所定の条
件により処理装置(CPU)の稼働と待機とが入替わる
ときはCPUl0Bが稼働状態になハCPUI OAが
待機状態になると共にCPU1oB修理後保守者からの
指令により障害検出のためCPUl0Bの送信部101
Bからの特定パターン符号PTの受信監視を開始する。Detect failures as follows. When the CPUI OB detects a failure, the failure report signal TR is sent from the notification unit 103B to the CPUI OB.
Reception unit 104 of A transfers the information to A, starts releasing and restoring the state of the CPU 10A, deletes the state of CPU OB itself, and executes the processing operation of the processing unit (CPU) QCPUIO
BCPU10B itself is normal. In this way, when the processing unit (CPU) is switched between operation and standby due to predetermined conditions, CPUl0B goes into the operating state, CPUIOA goes into the standby state, and at the same time, the CPU1oB is activated for failure detection according to instructions from the maintenance personnel after repair. Transmission unit 101 of CPU10B
Start monitoring reception of the specific pattern code PT from B.
この切替え後においては、第1図における破線の情報線
が使用され、第2図は符号101 Aが102 Aに、
符号104Aが103 Aに、符号102 Bが101
Bに、符号103Bが104BK、又符号PT及び信
号TRの矢印が方向・傾斜共に左右逆転し、時間TM及
び時限超過Toが符号10Aに移動する。After this switching, the broken line information line in FIG. 1 is used, and in FIG. 2, the code 101A becomes 102A,
Code 104A becomes 103 A, code 102 B becomes 101
At B, the arrows 103B and 104BK are reversed, and the directions and inclinations of the arrows PT and TR are reversed, and time TM and time limit To are moved to 10A.
このように、従来の障害検出方式は一つの発信部に対す
る障害検出に二つの処理装置を必要とし不経済であると
いう欠点を持つ。As described above, the conventional fault detection method has the disadvantage that it requires two processing units to detect a fault in one transmitter, which is uneconomical.
本発明の目的は一つの処理装置だけで障害検出するよう
構成することにより上記欠点を除去し設備の経済性の改
善が得られる障害検出方式を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a fault detection method that eliminates the above-mentioned drawbacks and improves the economical efficiency of equipment by configuring fault detection with only one processing device.
本発明による障害検出方式は、データの発信部及び着信
部を備え、所定の手順により該発着信部で授受する情報
により所定の機能動作を実行する被試験処理装置と、前
記発信部及び着信部を接続することにより伝送される情
報を傍受・監視し所定の伝送手順と比較して不一致のと
きは障害として前記被試験処理装置へ出力する障害検出
手段とを備えることを特徴とする。The failure detection method according to the present invention includes a processing device under test that includes a data transmitting section and a data receiving section and executes a predetermined functional operation based on information sent and received by the data transmitting and receiving section according to a predetermined procedure; It is characterized by comprising a failure detection means that intercepts and monitors the information transmitted by connecting the apparatus, compares it with a predetermined transmission procedure, and outputs the information as a failure to the processing apparatus under test when there is a discrepancy.
次に本発明について第3図及び第4図を参照して説明す
る。第3図は本発明の障害検出方式の一実施例を示す機
能ブロック図、又第4図は第3図における障害検出手順
を示すシーケンス図である。Next, the present invention will be explained with reference to FIGS. 3 and 4. FIG. 3 is a functional block diagram showing an embodiment of the fault detection method of the present invention, and FIG. 4 is a sequence diagram showing the fault detection procedure in FIG. 3.
第3図において被試験のための処理装置(以下CPU)
30は情報が授受されるデータの発信部301 及び着
信部302並に障害報告受付部303を含み1発信部3
01,302はそれぞれ情報の送信部301A、302
A及び受信部301B、302Bを備える。発信部30
1と着信部302とは伝送路33で接続され、発信部3
01からみたときは他のCPUに伝送路3ぎで接続し之
ときと同じ条件となり5着信部302も図示されていな
い他のCPUに接続したものと同一条件となる。発信部
301と着信部302との間はそれぞれの送信部301
A、302Aを受信部302B、301Bに対応させて
接続する。又、障害検出装置32け伝送路33を引込み
監視し、障害を検出するときはCPU30の障害報告受
付部303に通知する。In Figure 3, the processing device (hereinafter referred to as CPU) for the test object
Reference numeral 30 includes a data transmitting unit 301 and a receiving unit 302 for transmitting and receiving information, as well as a failure report receiving unit 303.
01 and 302 are information transmitting units 301A and 302, respectively.
A and receiving sections 301B and 302B. Transmission section 30
1 and the receiving section 302 are connected by a transmission path 33, and the transmitting section 3
When viewed from 01, the conditions are the same as when connected to another CPU through the transmission line 3, and the conditions for the 5-terminating section 302 are also the same as when connected to another CPU (not shown). A transmission section 301 is connected between the transmission section 301 and the reception section 302.
A, 302A are connected correspondingly to receiving sections 302B, 301B. Furthermore, the failure detection device 32 monitors the transmission line 33 and notifies the failure report receiving unit 303 of the CPU 30 when a failure is detected.
次に第3図及び第4図により障害検査手順を説明する。Next, the fault testing procedure will be explained with reference to FIGS. 3 and 4.
伝送路33における伝送制御手順はパケット通信による
。発信部301の送信部301Aから発信された発呼信
号CR,は検出装置32に傍受され着信部302の受信
部302 Bに到達する。The transmission control procedure on the transmission path 33 is based on packet communication. The calling signal CR transmitted from the transmitting section 301A of the transmitting section 301 is intercepted by the detection device 32 and reaches the receiving section 302B of the receiving section 302.
着信部302は受信部302Bで発呼信号CRを受付は
送信部302Aから着呼受付信号CA?発5−
信する。発信部301はこの着呼受付信号CAを受信部
301Bで受信し所定のデータI)’I’l’を送信部
301Aから出力する。着信部302の受信部302B
によるデータDTI受付けにより送信部302Aはデー
タ受付信号DAe出力し、この信号DAの受信により発
信部301は所定の第2のデータDT2ft出力する。The receiving unit 302 receives the call signal CR at the receiving unit 302B and receives the call acceptance signal CA? from the transmitting unit 302A. Message 5- Believe. The transmitter 301 receives this incoming call acceptance signal CA at the receiver 301B, and outputs predetermined data I)'I'l' from the transmitter 301A. Receiving unit 302B of incoming call unit 302
Upon reception of the data DTI, the transmitter 302A outputs a data acceptance signal DAe, and upon reception of this signal DA, the transmitter 301 outputs predetermined second data DT2ft.
このような手順に従って信号・データ等の情報が授受さ
れてCPU30の動作が進むっこの間、伝送回線33に
転送されt情報は障害検出装置32で傍受され、所定の
手順に従って出力される期待情報との一致を確認される
。ここで、期待した第2のデータDT2がCPU30の
発信部301から出力されないときは、データ出力を要
求した第1のデータ受付信号DAが転送されtときから
時間TMをはかり時限超過TOで障害検出装置32が障
害と判断して障害表示すると共にCPU30の障害報告
受付部303に障害報告信号TRを発信して報告する。While information such as signals and data is exchanged according to such a procedure and the operation of the CPU 30 progresses, the t information transferred to the transmission line 33 is intercepted by the failure detection device 32, and the expected information and output according to the predetermined procedure are transmitted to the transmission line 33. The match is confirmed. Here, when the expected second data DT2 is not output from the transmitter 301 of the CPU 30, the first data acceptance signal DA that requested data output is transferred, and a time TM is counted from time t, and a failure is detected when the time limit is exceeded TO. The device 32 determines that there is a failure, displays the failure, and sends a failure report signal TR to the failure report reception unit 303 of the CPU 30 to report it.
通常は、CPU30が障害報告を受けると設定した状態
を抹消し進行中の動作手順を最初の発呼か6−
ら再度実行する割込・自動開始動作をする。Normally, when the CPU 30 receives a failure report, it erases the set state and performs an interrupt/automatic start operation to restart the ongoing operation procedure from the first call.
本実施例では処理装置が通信機能を有し、伝送制御手順
を使用した情報の授受を説明したが、情報の送受信部が
データバス、プロセッサバス等のときもそれぞれの動作
手順に合う障害検出装置により同様の機能を発揮できる
つ又、データ無しについてだけを説明したが所足情報と
の照合手段により誤r)f*@’c検出する等の障害検
出も含まれる。In this embodiment, the processing device has a communication function and the transmission and reception of information using the transmission control procedure has been explained. However, when the information transmission/reception unit is a data bus, a processor bus, etc., a failure detection device that is suitable for each operation procedure is also described. In addition, although only the case of no data has been described, it also includes fault detection such as erroneous detection of r)f*@'c by means of comparison with sufficient information.
以上説明したように本発明によれば、一つの被試験処理
挟置を情報の発着信部を接続して動作させると共にこの
転送情報を監視して障害が検出できることにより、設備
の経済性を改善できるという効果が得られる。As explained above, according to the present invention, it is possible to operate a single processing device under test by connecting the information sending/receiving section and to monitor this transferred information to detect failures, thereby improving the economic efficiency of the equipment. You can get the effect that you can.
第1図は従来の障害検出方式の一構成例を示す機能ブロ
ック図、第2図は第1図における障害検出手順のシーケ
ンス図、第3図は本発明の障害検出方式の一実施例を示
す機能ブロック図、又第4図は第3図における障害検出
手順めシーケンス図である。
30・・・・・・処理装置、32・・・・・・障害検出
装置。
33.3ざ・・・・・・伝送路、3o1・・・・・・発
信部、3o2・°°°°°着信部、 301 A、
302A・−−−−・送信部、301B、302B・
・・・・・受信部。Fig. 1 is a functional block diagram showing an example of the configuration of a conventional fault detection method, Fig. 2 is a sequence diagram of the fault detection procedure in Fig. 1, and Fig. 3 shows an embodiment of the fault detection method of the present invention. FIG. 4 is a functional block diagram and a sequence diagram of the failure detection procedure in FIG. 3. 30...Processing device, 32...Fault detection device. 33.3... Transmission path, 3o1... Transmission section, 3o2/°°°°° Receiving section, 301 A.
302A・---・Transmission unit, 301B, 302B・
...Receiving section.
Claims (1)
発着信部で授受する情報により所定の機能動作を実行す
る被試験処理装置と、前記発信部及び着信部を接続する
ことにより伝送される情報を傍受・監視し所定の伝送手
順と比較して不一致のときは障害として前記被試験処理
装置へ出力する障害検出手段とを備えることを特徴とす
る障害検出方式。The data is transmitted by connecting the processing device under test, which is equipped with a data transmission section and a data reception section, and executes a predetermined functional operation based on the information exchanged by the data transmission and reception section according to a predetermined procedure. A failure detection method comprising: a failure detection means that intercepts and monitors information, compares it with a predetermined transmission procedure, and outputs the information to the processing device under test as a failure when there is a discrepancy.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58001864A JPS59127160A (en) | 1983-01-10 | 1983-01-10 | Fault detecting system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58001864A JPS59127160A (en) | 1983-01-10 | 1983-01-10 | Fault detecting system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59127160A true JPS59127160A (en) | 1984-07-21 |
Family
ID=11513408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58001864A Pending JPS59127160A (en) | 1983-01-10 | 1983-01-10 | Fault detecting system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59127160A (en) |
-
1983
- 1983-01-10 JP JP58001864A patent/JPS59127160A/en active Pending
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