JPS59119758A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59119758A JPS59119758A JP57232835A JP23283582A JPS59119758A JP S59119758 A JPS59119758 A JP S59119758A JP 57232835 A JP57232835 A JP 57232835A JP 23283582 A JP23283582 A JP 23283582A JP S59119758 A JPS59119758 A JP S59119758A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- rom
- gate electrode
- electrode wiring
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 13
- 238000005468 ion implantation Methods 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- OWEGMIWEEQEYGQ-UHFFFAOYSA-N 100676-05-9 Natural products OC1C(O)C(O)C(CO)OC1OCC1C(O)C(O)C(O)C(OC2C(OC(O)C(O)C2O)CO)O1 OWEGMIWEEQEYGQ-UHFFFAOYSA-N 0.000 description 1
- ZCLAHGAZPPEVDX-UHFFFAOYSA-N D-panose Natural products OC1C(O)C(O)C(OC(C(O)CO)C(O)C(O)C=O)OC1COC1C(O)C(O)C(O)C(CO)O1 ZCLAHGAZPPEVDX-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- ZCLAHGAZPPEVDX-MQHGYYCBSA-N panose Chemical compound O[C@H]1[C@H](O)[C@@H](O)[C@@H](O[C@H]([C@H](O)CO)[C@H](O)[C@@H](O)C=O)O[C@@H]1CO[C@@H]1[C@H](O)[C@@H](O)[C@H](O)[C@@H](CO)O1 ZCLAHGAZPPEVDX-MQHGYYCBSA-N 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/38—Doping programmed, e.g. mask ROM
- H10B20/383—Channel doping programmed
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置の製造方法に関するもので、特に
ＲＯＭ （読み出し専用メモリ）のビットパターンの鶴
き込み工程を有するシリコンゲート開Ｏ８型ＲＯＭの製
造方法に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a silicon gate open O8 type ROM having a step of cutting in a bit pattern of a ROM (read-only memory). It is about the method.
シリコンゲート開Ｏ８型ＲＯＭではΔ１０ｓトランジス
タのチャネル領域にイオン注入を行いトランジスタの閾
値を変化させて情報の省き込みを行なうが、この書き込
みは次に示すように素子の形成と共に行なわれる。第１
図（ａ）に示すようにＰ型シリコン基板１１上に厚い熱
酸化膜（フィールド酸化膜）１２を形成し、素子領域す
なわちＲＯＭビットと成る部位のフィールド酸化膜１２
を除去して簿いゲート酸化膜１３を形成する。In the silicon gate open O8 type ROM, information is written by implanting ions into the channel region of the Δ10s transistor to change the threshold value of the transistor, but this writing is performed at the same time as the element formation as described below. 1st
As shown in Figure (a), a thick thermal oxide film (field oxide film) 12 is formed on a P-type silicon substrate 11, and the field oxide film 12 is formed in a region that will become an element region, that is, a ROM bit.
is removed to form an unbalanced gate oxide film 13.
続いて、第１図（ｂ）に示すようＶζレジストノ４を塗
布した後このレジスト１４を写真蝕刻し、レジスト１４
のパターンをマスクとして、例えば加速電圧が４０ Ｋ
ｅ Ｖの条件で書き込みを行なうべきＲＯＭビットのチ
ャンネル領域予定部にＮ型不純狗を選択イオン注入し、
イオン注入層１５を形成する。Subsequently, as shown in FIG. 1(b), Vζ resist No. 4 is applied and this resist 14 is photo-etched to form the resist 14.
For example, if the acceleration voltage is 40 K using the pattern of
Selectively implant N-type impurity ions into the planned channel region of the ROM bit to be written under the eV condition,
An ion implantation layer 15 is formed.
次いで、上記レジスト１４を除去した後、通常のシリコ
ンゲートＭＯ８Ｗ トランジスタの形成と同様の手順で
、例えばソース・ドレイン領域予定部のゲート酸化膜１
３を除去し、Ｎ型不純物を選択的に熱拡散させて、第１
図（ｃ）に示すようにデータライン等となるソース・ト
レイン領域１６を形成する。またこの熱拡散工程時に上
記イオン注入層が活性化される。Next, after removing the resist 14, the gate oxide film 1 in the planned source/drain region is removed, for example, in the same manner as in the formation of a normal silicon gate MO8W transistor.
3 is removed, the N-type impurity is selectively thermally diffused, and the first
As shown in Figure (c), a source train region 16 that will become a data line or the like is formed. Further, the ion implantation layer is activated during this thermal diffusion step.
続いて第１図（ｄ）に示すように多結晶シリコン１７を
堆積式せた後写真蝕刻してワードラインとなるゲート電
極配線１２を形成し、さらに保護用酸化膜１８ｆｆ：適
宜形成した後、コンタクトホールを開口し、図示しない
金属配線等を形成する。Subsequently, as shown in FIG. 1(d), polycrystalline silicon 17 is deposited and then photo-etched to form gate electrode wiring 12 which will become a word line, and a protective oxide film 18ff is appropriately formed. A contact hole is opened, and metal wiring (not shown) is formed.
上記のようにＬ７て形成したシリコンゲートＭ ＯＳ型
ＲＯＭでは、ＲＯＭビットへの情報の書き込みを素子形
成の比較的初期の段階すなわちソース・ドレインの形成
や多結晶シリコンのゲート電極配線を形成する以前に行
っている。In the silicon gate MOS type ROM formed by L7 as described above, information is written to the ROM bit at a relatively early stage of element formation, that is, before the formation of the source/drain and the formation of polycrystalline silicon gate electrode wiring. I'm going to
このため製作過程中でのＲＯＭビットパターンへの書き
込み内容の変更等を行ないたい場合の融通性に欠ける。Therefore, there is a lack of flexibility when it is desired to change the contents written to the ROM bit pattern during the manufacturing process.
またユーザー（使用者）よりＲＯＭの書き込むデータが
与えられた場合、ウェハにデータをイオン注入によシ１
き込んでから数多くのデバイス工程を経てＲＯＭのチッ
プが完成するために、ユーザーから書き込み内容が与え
られ完成するまでの製造期間が長く必要であった。In addition, if data to be written in the ROM is given by the user, the data is transferred to the wafer by ion implantation.
Since a ROM chip is completed after it is written and goes through numerous device processes, a long manufacturing period is required from when the user writes the contents to when the ROM is completed.
この発明は上記のような点に鑑みなされたもので、ＲＯ
Ｍへの書き込み内容の変更が容易で製造期間の短縮が図
れる半導体装］Ｓの製造方法を提供しようとするもので
ある。This invention was made in view of the above points, and the RO
It is an object of the present invention to provide a method for manufacturing a semiconductor device S in which it is easy to change the contents written in M and the manufacturing period can be shortened.
すなわちこの発明に係る半導体装置の製造方法では、Ｒ
ＯＭビットとなるＭＯ３Ｉ−ランジスタのゲート酸化膜
を形成した後、ＲＯＭビットへイオン注入による摺き込
み全行なわずに例えば多結晶シリコン等からなるゲート
電極配線を形成し、続いてソース・ドレイン領域を拡散
形成す一〇この後、上記ゲート電極配線およびゲート酸
化膜を通してＲＯＭビットのチャネル領域へイオン注入
してデータの書き込みを行い、その後で適宜探題用酸化
膜や金へ配線層等を形成するものでちる。That is, in the method for manufacturing a semiconductor device according to the present invention, R
After forming the gate oxide film of the MO3I-transistor that will become the OM bit, a gate electrode wiring made of polycrystalline silicon or the like is formed without performing ion implantation into the ROM bit, and then the source/drain regions are formed. Diffusion formation 10 After this, data is written by ion implantation into the channel region of the ROM bit through the gate electrode wiring and gate oxide film, and then a wiring layer, etc. is formed on the probe oxide film and gold as appropriate. Dechiru.
以下図面を参照して、この発明の一実施例について第２
図を用いて説明する。A second embodiment of the present invention will be explained below with reference to the drawings.
This will be explained using figures.
（Ａ）第２図（ａ）に示すようにＰ型シリコン基板１１
の上に厚い酸化膜をフィールド酸化膜１２として形成し
、ソース・ドレイン領域等の素子形成予定部上の！イー
ルド酸化膜１２を除去し薄いゲート酸化ｊｊ〆１３を形
成する０（Ｂ） 続いて第２図（ｂ）に示すように例
えば約４０００Ｘの多結晶シリコン層を被ｘｒｊ７、こ
の多結晶シリコン層をバターニングしてゲート電極配線
１７を形成する。(A) As shown in FIG. 2(a), a P-type silicon substrate 11
A thick oxide film is formed as a field oxide film 12 over the areas where elements such as source/drain regions are to be formed. The yield oxide film 12 is removed and a thin gate oxide film 13 is formed (B). Next, as shown in FIG. A gate electrode wiring 17 is formed by patterning.
Ｃ） 次いて第２図（ｃ）に示すようにグー１酸化膜ノ
３にソースおよびドレイン（ｉｌ：ｊ、板形成用のだめ
の窓を開口し、不純物ビ１度１０１５０３程度のＮ型不
純物を拡散させてソース・ドレイン領域１６を形成する
。C) Next, as shown in FIG. 2(c), a source and drain (il:j) plate-forming window is opened in the goo 1 oxide film No. 3, and an N-type impurity of approximately 101503 degrees is added. Source/drain regions 16 are formed by diffusion.
（２）続いて、第２図（ａ）に示−ｊ゛よりにＰ型シリ
コン基板に多結晶シリコンのゲート電極配線１７および
ゲート酸化ｆｌＯＧ ｌ ３（ｌ−４して１力定のＲＯ
Ｍビットへ選択的に１′■型不純物をｆＢ＋えばおよそ
１６０ ＫｅＶの加速電圧でイオン注入し、不純物濃度
が約２ Ｘ １０”ｃｎｔ″のイオン注入層１９ｆｆ形
成する。その後、図示しないが適宜保ｉ用酸化膜や金犀
配υ等を形成、する。(2) Next, as shown in FIG. 2(a), polycrystalline silicon gate electrode wiring 17 and gate oxidation flOG l3 (l-4 and 1 force constant RO) are applied to the P-type silicon substrate.
A 1' type impurity is selectively implanted into the M bit at an accelerating voltage of fB+, approximately 160 KeV, to form an ion implantation layer 19ff having an impurity concentration of approximately 2.times.10 "cnt". Thereafter, although not shown in the drawings, a protective oxide film, an oxide film, and the like are formed as appropriate.
ここで上記のようにしてＲＯ’／（を製造するものでは
、第２図（ｃ）で示す紋［晶′１″なわちゲート電極配
線）７とソース拳ドレイン領域１６との形成が終了して
からデータの■き込みを行なう０このため、予め、ケー
ト電袷−己ψ１７と゛ノース・トレイン領域１６壕で形
成“ご才また標準化ざｔした多数のＲＯＭビットをつ」
−７１上にノ１ニ成ｔ、−Ｃｉ；−くことができ、ユー
ザーからＲＯＭへの一＝、ｌｊ、 ：、込み内容が供給
された段階で残りの製造エイ’ｉｊ ’（ｒイ〒えは良
い。り１−って、従来のようにテーク力＝ ｏｔ、 ｉ
’；芒れてからデバイスプロセスの初期の段階よフ製造
する必要がないため、ユーザーのＲＯＭの製造要請があ
ってからの製造期間を短縮できる。Here, in the case where RO'/( is manufactured as described above), the formation of the pattern [crystal '1'', that is, the gate electrode wiring) 7 and the source and drain regions 16 shown in FIG. 2(c) is completed. For this reason, in advance, a large number of standardized ROM bits were formed in the Kate line ψ17 and the North train area 16.
-Ci;- can be written on -71, and once the user has supplied the contents to the ROM, the rest of the manufacturing process can be completed. ri1-, take force = ot, i as before.
'; Since there is no need to manufacture the ROM at the initial stage of the device process after it is assembled, the manufacturing period from the time a user requests ROM manufacturing can be shortened.
以上のようにこの発明の半導体装置の製造方法によれば
、ＲＯＭビットへの内容の碧き込むためのイオン注入を
素子形成工程の後期に行なうため、製造工程の煩雑化を
招かずに素子製造過栓におけるＲＯＭへの書き込み内容
の変更が容易となシ、ＲＯＩｔ、＝Ｉへの右き込み内容
が鳥えらり、てから完成するまでのＭ造期間を短縮でき
る０As described above, according to the method of manufacturing a semiconductor device of the present invention, ion implantation for injecting detailed contents into ROM bits is performed in the latter half of the element formation process. It is easy to change the content written to the ROM when overfilling, and the content written to the right side of ROIt, = I can be selected to shorten the M construction period from completion to completion.
第１図は従来の半導体装置の製造過程を説明する断面図
、第２図はこの発明の半導体装１脩の製造方法の一実施
例を説明する断面図である。
１１・・シリコン基板、１３・・・ゲート酸化膜、１６
・パノース・ドレイン領域、１７・・ゲート電律配ｆｍ
ｐ ”・・・イオン注入層。
出願人代理人 弁理士 鈴 江 武 彦第１図
（ａ）
１、事件の表示
特願昭５７−２３２８３５号
２、発明の名称
゛ヒ導体装置の製造方法
３、補正をする者
事件との関係 特許出願人
（３０７）東京芝浦電気株式会社
４、代理人
６、捕型の対象FIG. 1 is a sectional view illustrating a conventional manufacturing process of a semiconductor device, and FIG. 2 is a sectional view illustrating an embodiment of a method for manufacturing one semiconductor device according to the present invention. 11...Silicon substrate, 13...Gate oxide film, 16
・Panose drain region, 17...Gate electrical distribution fm
p ”...Ion-implanted layer. Applicant's agent: Takehiko Suzue, patent attorney Figure 1 (a) 1. Indication of the case: Japanese Patent Application No. 57-232835 2. Name of the invention: Method for manufacturing a conductor device 3 , Relationship with the case of the person making the amendment Patent applicant (307) Tokyo Shibaura Electric Co., Ltd. 4, Agent 6, Subject of arrest
Claims (1)
と、上記ゲート酸化膜上に導電体層を被着した後、パタ
ーニングを行いゲート電極配糺層を形成する工程と、ソ
ース・ドレイジ予定部に不純物を導入しソース・ドレイ
ン領域を形成する工程と、上記ゲート酸化膜およびゲー
ト電＠１．配線層を通してこのゲート酸化膜下に不純物
をイオン注入することによりＲＯＭへの情報の書き込み
を行う工程とを具備することを特徴とする半導体装置の
製造方法。a step of forming a gate oxide film in an element region on a semiconductor substrate; a step of depositing a conductor layer on the gate oxide film and then patterning it to form a gate electrode bonding layer; A step of introducing impurities to form source/drain regions, and a step of introducing impurities into the gate oxide film and the gate electrode @1. 1. A method of manufacturing a semiconductor device, comprising the step of writing information into a ROM by ion-implanting impurities into the gate oxide film through the wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57232835A JPS59119758A (en) | 1982-12-25 | 1982-12-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57232835A JPS59119758A (en) | 1982-12-25 | 1982-12-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59119758A true JPS59119758A (en) | 1984-07-11 |
Family
ID=16945530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57232835A Pending JPS59119758A (en) | 1982-12-25 | 1982-12-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59119758A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014236546A (en) * | 2013-05-31 | 2014-12-15 | 株式会社荏原製作所 | Motor and pump |
| US11981045B2 (en) | 2018-03-05 | 2024-05-14 | Bobst (Shanghai) Ltd | Advance-shaft transition apparatus and hot foil stamping and die-cutting equipment |
-
1982
- 1982-12-25 JP JP57232835A patent/JPS59119758A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014236546A (en) * | 2013-05-31 | 2014-12-15 | 株式会社荏原製作所 | Motor and pump |
| US11981045B2 (en) | 2018-03-05 | 2024-05-14 | Bobst (Shanghai) Ltd | Advance-shaft transition apparatus and hot foil stamping and die-cutting equipment |
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