JPS59118003U - Control signal output circuit - Google Patents

Control signal output circuit

Info

Publication number
JPS59118003U
JPS59118003U JP1214983U JP1214983U JPS59118003U JP S59118003 U JPS59118003 U JP S59118003U JP 1214983 U JP1214983 U JP 1214983U JP 1214983 U JP1214983 U JP 1214983U JP S59118003 U JPS59118003 U JP S59118003U
Authority
JP
Japan
Prior art keywords
control signal
signal output
output circuit
output
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1214983U
Other languages
Japanese (ja)
Inventor
石井　孝寿
菊川　利男
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP1214983U priority Critical patent/JPS59118003U/en
Publication of JPS59118003U publication Critical patent/JPS59118003U/en
Pending legal-status Critical Current

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Landscapes

  • Safety Devices In Control Systems (AREA)
  • Power Sources (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来例を示す回路構成図、第２図は上記従来例
の動作を説明するためのタイミングチャート、第３図は
本考案の一実施例を示す回路構成図、第４図は上記実施
例の動作を説明するためのタイミングチャート、第５図
は本考案の他の実施例を示す回路構成図、第６図は上記
能の実施例の動作を説明するためのタイミングチャート
である。 １・・・制御装置、２１・・・レベルシフト回路、２２
・・・ナントゲート、２３．３３・・・制御信号出力回
路、３２・・・アンドゲート。 第３図 ３“）ｉ　■　１　″“１ ｔｌｂ　　　４３（ｔ）Fig. 1 is a circuit configuration diagram showing a conventional example, Fig. 2 is a timing chart for explaining the operation of the above conventional example, Fig. 3 is a circuit configuration diagram showing an embodiment of the present invention, and Fig. 4 is the above FIG. 5 is a circuit diagram showing another embodiment of the present invention, and FIG. 6 is a timing chart for explaining the operation of the embodiment described above. 1... Control device, 21... Level shift circuit, 22
... Nantes gate, 23.33... Control signal output circuit, 32... AND gate. Figure 3 3")i ■ 1""1 tlb 43(t)

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電源電圧を一定の電圧だけレベルシフトするレベルシフ
ト回路と、上記電源電圧が供給される制御装置で発生さ
れる制御信号の出力を上記レベルシフト回路の出力に応
じて制御する出力ゲートとを具備することを特徴とする
制御信号出力回路。A level shift circuit that level-shifts the power supply voltage by a certain voltage; and an output gate that controls the output of a control signal generated by a control device supplied with the power supply voltage in accordance with the output of the level shift circuit. A control signal output circuit characterized by:
JP1214983U 1983-01-31 1983-01-31 Control signal output circuit Pending JPS59118003U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1214983U JPS59118003U (en) 1983-01-31 1983-01-31 Control signal output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1214983U JPS59118003U (en) 1983-01-31 1983-01-31 Control signal output circuit

Publications (1)

Publication Number Publication Date
JPS59118003U true JPS59118003U (en) 1984-08-09

Family

ID=30143554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1214983U Pending JPS59118003U (en) 1983-01-31 1983-01-31 Control signal output circuit

Country Status (1)

Country Link
JP (1) JPS59118003U (en)

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