JPS5911699A - Method of soldering printed board - Google Patents

Method of soldering printed board

Info

Publication number
JPS5911699A
JPS5911699A JP12163282A JP12163282A JPS5911699A JP S5911699 A JPS5911699 A JP S5911699A JP 12163282 A JP12163282 A JP 12163282A JP 12163282 A JP12163282 A JP 12163282A JP S5911699 A JPS5911699 A JP S5911699A
Authority
JP
Japan
Prior art keywords
soldering
solder
hole
parts
printed board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12163282A
Other languages
Japanese (ja)
Inventor
実 幸裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12163282A priority Critical patent/JPS5911699A/en
Publication of JPS5911699A publication Critical patent/JPS5911699A/en
Pending legal-status Critical Current

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (イ)分野 本発明はプリント板の半田付方法に係9、特に実装され
た部品をプリント基板に半田句し、あるいは層間配線用
のスルーホールを半田うめする半田あげ工程において希
望しない部分をマスクして選択的に半田あげを行う方法
に関するO(ロ)従来技術 便来よりプリント配線基板上に各株部品を笑装いhd半
田槽にディップするあるいはりフロー面に接触通過させ
て半田あげを行う自動半田付は行われているがプリント
板完成体を製造する過程において製造工程上の組立順序
の都合によシ、すなわちプリント板の特定の部分に装着
する部品あるいは部品ユニットが変わることにより、そ
の前工程までは共通で以後は別仕様のものになるとか、
一部最終的には改版される部分があるとか、自動半田付
された後で取付けねばならない部品があるとか、部分的
に半田あげをしたくない部分が発生することがままある
。こうした場合とにかく全面に半田あげして、あとで部
分的に半田とてと牛用吸堆工具で半田をとる作業はいか
にも非能率で、よりたくみな方法として半田おばを8i
望しない部分に片面に釉層J−を壱する側熱シートをマ
スキング用に接着して半田あげをする方法が却られてい
る。これらを第1図と兜2図でボす。第1図と第2図は
従来例の説明図で、第1図は平面図、第2図は断面図。
DETAILED DESCRIPTION OF THE INVENTION (A) Field The present invention relates to a method for soldering printed circuit boards, and in particular to a soldering method for soldering mounted components to a printed circuit board or for filling through holes for interlayer wiring with solder. O (b) Regarding a method of selectively applying solder by masking undesired parts in the process (b) From the conventional technology, each component is placed on a printed wiring board and dipped in an HD solder bath or brought into contact with the flow surface. Although automatic soldering is practiced, in which parts are passed through and soldered, due to the assembly order in the manufacturing process, in the process of manufacturing a finished printed board, parts or parts that are attached to a specific part of the printed board are By changing the unit, the previous process may be the same, but the subsequent processes may have different specifications.
Sometimes there are parts that will be revised in the final version, parts that need to be installed after being automatically soldered, or parts that you don't want to solder. In such a case, it is very inefficient to apply solder to the entire surface and then remove the solder partially using a solder tip and a cow suction tool.
The method of adhering a side heating sheet having a glaze layer J- on one side to the undesired part for masking and soldering is rejected. These are illustrated in Figures 1 and 2. 1 and 2 are explanatory diagrams of a conventional example, where FIG. 1 is a plan view and FIG. 2 is a sectional view.

図中1はプリント基板、2は部品、3はマスキングチー
ブ1aは半田と接触させる側を示すまた、AVi半田あ
けする部分Bは半田あげを希望しない部分を示す。こう
して半田めげを希望しない部分にマスキングチーブをは
りつけ、ld側から浴融半田に接触きせゐとマスキング
チーブのある部分たけ半田あげが防止出来るが、マスキ
ングチーブを必要な部分をおおう形状に切り出すこと、
帖9句けること、あとではがさすことが必要であり、テ
ープの成形費材料費のみならず作業的シ(も今一つ不都
合があった。また粘着ノーの烈震質とはがれ本発明はこ
うした背景のもとに成され、目的とするのVi部分的に
半田あげを防止する作業を効率化することであシ、本発
す」の物欲は上記目的を達成する+段としてプリント配
線基板に部品を装着したもの(+−浴−手田に接触式せ
て半田付を行う工性において、グリ/ト配線基板の上記
接触によって半田めげを化菫しない貫通孔に線孔と略l
!′iJ径のテフロン線を負虐させて半田付けを行うこ
とである。
In the figure, 1 is a printed circuit board, 2 is a component, 3 is a masking chip 1a, which is the side to be brought into contact with solder, and a part B to be subjected to AVi soldering is a part where no soldering is desired. In this way, you can attach a masking chip to the part where you do not want solder burnout, and contact the bath melted solder from the LD side, and prevent the solder from rising in the part where the masking chip is located.
It is difficult to peel off the tape and it is necessary to peel it off afterwards, which is not only inconvenient in terms of molding cost and material cost but also in terms of work efficiency.In addition, the present invention is designed to solve the problem of adhesiveness and peeling. Originally, the purpose was to partially prevent solder build-up and make the work more efficient, and the purpose of this article is to achieve the above objectives by attaching components to printed wiring boards. (In the process of performing contact soldering on a +-bath-te solder, a wire hole is used in a through-hole that does not cause solder smear due to the contact of the grid/grid wiring board.
! 'iJ diameter Teflon wire is used for soldering.

−Iなμちマスキングは本鋤の必要部分プリントもので
ある。
-I μchi masking is a printed part of the main plow.

に)実施例 第3図と第4図は本発明の一人jd ’+りJの勝、四
国で、夫々平面図と断回路1を示す。
B) Embodiment FIGS. 3 and 4 show a plan view and a disconnection circuit 1, respectively, in Shikoku, Shikoku, one of the inventors of the present invention.

第1図、第2図の匠来例と異るところは部分Bをマスク
するマスキングチーブ3のbりに部分Bに存在するプリ
ント基板の貫通孔1b、  IC,ld。
The difference from the conventional work shown in FIGS. 1 and 2 is that the through-holes 1b, IC, and ld of the printed circuit board exist in the part B in contrast to the masking chip 3 that masks the part B.

・・・・・・に貫通孔とほぼ同径のテフロン線4をさし
通しである点である。
. . . A Teflon wire 4 having approximately the same diameter as the through hole is inserted through the hole.

なお、さし通し方は図の様に睨をつないで通しても切断
して1本1本辿してもか1わないがある程度つながって
いる方があとで線を覗り外す時に作業がしやすい。
Note that there are two ways to thread the wires, as shown in the diagram, by connecting the wires and passing them through, or by cutting them and tracing each wire one by one, but it is better to connect the wires to some extent so that it will be easier to remove the wires later. It's easy to do.

なお半田あげ工程として実施例の構成の様に半田あげを
希望しない貫通孔にテフロン線をさし通したものを自動
半田あげ格でプリント基板の1a面をとけた半田と接触
させた後テフロン線を引きぬくと半田おげを希望しない
貫通孔だけ半田でうめられずに残るので、あとの工程で
部品の不足等を袋層するための孔が必要な分だけ確保m
×るわけである。
In addition, in the soldering process, as in the configuration of the embodiment, a Teflon wire is inserted into the through-hole where soldering is not desired, and after contacting surface 1a of the printed circuit board with the melted solder using an automatic soldering machine, the Teflon wire is inserted into the through hole where soldering is not desired. If you pull it out, only the through-holes that do not require soldering will remain without being filled with solder, so make sure to have as many holes as you need to cover up missing parts in the later process.
That's why.

(ホ)効果 以上説明した僚に、+発明によればプリント板に自動半
田あげを行う工程において半田めげを希望しない部分を
きわめて効率よくマスクすることが出来るものである。
(e) Effects To the above-mentioned colleagues, + according to the invention, it is possible to very efficiently mask parts where solder burnout is not desired in the process of automatically applying solder to a printed circuit board.

なをテフロン線は表面がテフロンであれば良く芯に銅線
等の入った電線の方が孔にさし通すときの作業性が良い
As long as the surface of the Teflon wire is Teflon, it is fine, and wires with copper wire or the like in the core are easier to work with when inserted into holes.

【図面の簡単な説明】[Brief explanation of drawings]

第1図と第2図は従来例の説明1弟3図と第4図は本発
明の一実施例の説明図。 図中、lはプリント基板、2Vi部品、3はマスキング
チーブ、4はテフロンa、1aはプリント板の半田と接
触させる側、lb、  lc・・・・・・は半田あけを
希望しない′A、通孔。
1 and 2 are explanatory diagrams of a conventional example. FIGS. 1 and 4 are explanatory diagrams of an embodiment of the present invention. In the figure, l is a printed circuit board, 2Vi parts, 3 is a masking chip, 4 is Teflon a, 1a is the side of the printed board that will be in contact with the solder, lb, lc... are 'A' where no soldering is desired, Through hole.

Claims (1)

【特許請求の範囲】[Claims] プリント配rd34基板に部品を装着したものを浴−半
田に接触させて半田付を行う工程において、プリント配
線基板の上記接触によって半田あげを希望しない貫通孔
に該孔と略同径のテフロン線を貫通させて半田付けを行
うことを特徴とするプリント板の半田付方法。
In the process of soldering a printed wiring board with components mounted on it by bringing it into contact with a solder bath, a Teflon wire with approximately the same diameter as the hole is inserted into the through hole of the printed wiring board where soldering is not desired due to the above contact. A method of soldering a printed circuit board, which is characterized by performing soldering through the soldering.
JP12163282A 1982-07-13 1982-07-13 Method of soldering printed board Pending JPS5911699A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12163282A JPS5911699A (en) 1982-07-13 1982-07-13 Method of soldering printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12163282A JPS5911699A (en) 1982-07-13 1982-07-13 Method of soldering printed board

Publications (1)

Publication Number Publication Date
JPS5911699A true JPS5911699A (en) 1984-01-21

Family

ID=14816065

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12163282A Pending JPS5911699A (en) 1982-07-13 1982-07-13 Method of soldering printed board

Country Status (1)

Country Link
JP (1) JPS5911699A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63153890A (en) * 1986-12-17 1988-06-27 株式会社 鈴木測器製作所 Member for masking holes to be drilled during dip soldering
JPS63153891A (en) * 1986-12-17 1988-06-27 株式会社 鈴木測器製作所 Member for masking holes to be drilled during dip soldering

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5486757A (en) * 1977-12-23 1979-07-10 Fujitsu Ltd Method of soldering electronic components

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5486757A (en) * 1977-12-23 1979-07-10 Fujitsu Ltd Method of soldering electronic components

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63153890A (en) * 1986-12-17 1988-06-27 株式会社 鈴木測器製作所 Member for masking holes to be drilled during dip soldering
JPS63153891A (en) * 1986-12-17 1988-06-27 株式会社 鈴木測器製作所 Member for masking holes to be drilled during dip soldering

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