JPS59115641U - Circuit board mold flow prevention structure - Google Patents

Circuit board mold flow prevention structure

Info

Publication number
JPS59115641U
JPS59115641U JP1983009214U JP921483U JPS59115641U JP S59115641 U JPS59115641 U JP S59115641U JP 1983009214 U JP1983009214 U JP 1983009214U JP 921483 U JP921483 U JP 921483U JP S59115641 U JPS59115641 U JP S59115641U
Authority
JP
Japan
Prior art keywords
circuit board
prevention structure
flow prevention
mold flow
board mold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983009214U
Other languages
Japanese (ja)
Inventor
「峰」山　靖
Original Assignee
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by セイコーエプソン株式会社 filed Critical セイコーエプソン株式会社
Priority to JP1983009214U priority Critical patent/JPS59115641U/en
Publication of JPS59115641U publication Critical patent/JPS59115641U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の実施例を示す平面図、第２図は第１の
断面図である。 １・・・・・・ＩＣチップ、２．３・・・・・・レジス
ト、４゜４′・・・・・・基板面゛、７・・・・・・モ
ールド、６・・・・・・回路基板。FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is a first sectional view. 1...IC chip, 2.3...Resist, 4゜4'...Substrate surface, 7...Mold, 6...・Circuit board.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＩＣチップを有する回路基板において、該ＩＣチップの
外周に、複数のレジスト壁を設けた事を特徴とする、回
路基板のモールド流れ防止構造。A mold flow prevention structure for a circuit board, characterized in that a plurality of resist walls are provided around the outer periphery of the IC chip in the circuit board.
JP1983009214U 1983-01-26 1983-01-26 Circuit board mold flow prevention structure Pending JPS59115641U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983009214U JPS59115641U (en) 1983-01-26 1983-01-26 Circuit board mold flow prevention structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983009214U JPS59115641U (en) 1983-01-26 1983-01-26 Circuit board mold flow prevention structure

Publications (1)

Publication Number Publication Date
JPS59115641U true JPS59115641U (en) 1984-08-04

Family

ID=30140682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983009214U Pending JPS59115641U (en) 1983-01-26 1983-01-26 Circuit board mold flow prevention structure

Country Status (1)

Country Link
JP (1) JPS59115641U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01114494A (en) * 1987-10-29 1989-05-08 Dainippon Printing Co Ltd Ic card and ic module for ic card

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01114494A (en) * 1987-10-29 1989-05-08 Dainippon Printing Co Ltd Ic card and ic module for ic card

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