JPS59114485A - Pace adjusting apparatus - Google Patents

Abstract

PURPOSE:To perform pace adjustment within a short time, by calculating the state number of a logical pace adjusting amount from a cycle wherein logical time correction is not performed. CONSTITUTION:The pace adjustment of IC for a wristwatch is performed by using a pace adjusting apparatus consisting of a power source circuit 231, a frequency reference source 232, a counter 233, an operation circuit part 234, a control circuit 235 and a display apparatus 236. The external signal from a terminal 237 or the internal signal from the frequency reference source 232 is supplied to the counter 233 as a clock signal while the cycle data of the output 7 of IC 23 for the wristwatch is operated in the operation circuit part 234 and the result is displayed by the display apparatus 236. The control circuit 235 supplies a system reset signal R to IC23 for the wristwatch in synchronous relation to measuring timing. When the reset signal R is an H-level, logical gentle operation is not performed and, when L-level, time correction is performed.

Description

【発明の詳細な説明】 本発明は水晶腕時計の歩度を測定しさらに調整會短時間
で能率良く行なうための歩度ｔＡ整装匝に関すゐ。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a rate adjustment tool for measuring the rate of a quartz wristwatch and for efficiently performing adjustment in a short time.

不発明の目的に、歩度の論理回路的調整手段（以後量率
のために論理緩急ンとトリマコンデンサ等のアナログ的
微調手段を兼ねそなえた水晶腕時計の製造時に於ける歩
度調奎會短時間で能率良く行ない製造コス）ｌｆ−低減
することにある。以下、ノーを追って本発明の内容を詳
述する。For the non-inventive purpose, the rate adjustment process is carried out in a short period of time during the manufacture of a crystal wristwatch which is equipped with a logic circuit type adjustment means for the rate (hereinafter, a logical adjustment circuit for the rate and an analog fine adjustment means such as a trimmer capacitor). The aim is to reduce manufacturing costs (lf) through efficient production. Hereinafter, the contents of the present invention will be explained in detail following No.

従来、水晶腕時計の時間精度、即ち歩度を測足し調査す
る一般的方法に水晶腕時計のＩＣ’ｉＸ笑装した回路ブ
ロックに於てステップモータの駆動出力端子より２秒毎
に出力されるパルス信号を測定し歩度修正用素子會可変
することにより行なわれて米た。第１図に該方法を実施
する構成を示す。Conventionally, the general method of measuring and investigating the time accuracy of a quartz wristwatch, that is, the rate, is to use a pulse signal output every two seconds from the drive output terminal of a step motor in a circuit block disguised as an IC'iX of a quartz wristwatch. This was done by measuring and varying the rate correction elements. FIG. 1 shows a configuration for implementing the method.

図中谷部位の名称に、１−０・・・腕時計用工０，１１
・・・カウンタ当の周波数９周期計−ｊ器、１２・・・
水晶振動子、１３・・・トリマコンデンサ、１４・・・
水晶発振器ドレイン端子、１５・・・水晶発振器ゲイト
端子１／）、１７・・・モータ駆動出力端子、１８・・
・システムリセット端子、１９・・・論理緩急端子であ
る。The name of the Nakatani part in the diagram is 1-0... Wristwatch work 0,11
...Frequency 9 period meter-j unit for counter, 12...
Crystal oscillator, 13... Trimmer capacitor, 14...
Crystal oscillator drain terminal, 15... Crystal oscillator gate terminal 1/), 17... Motor drive output terminal, 18...
- System reset terminal, 19...Logic adjustment terminal.

１３のトリマコンデンサに水晶振動子の負荷谷盪を可変
することにエフ腕時計の時間憚準となっていろ水晶発振
器の周波数、即ち時間間隔を調理することができる。又
１９の調理緩急端子Ａ１のデータに基づく論理操作によ
ｐ歩度修正も行なわれる。この歩度修正は例えば第５図
に示す調理緩急回路で夾現できるが、その原理に周期的
に計時分局器のカウンタ状態を遷移させる時刻修正であ
り結果としてこの手段による歩度は論理緩急動作周期で
平均化しｆｃ値で与えられる、征ってこの場合に於ける
腕時計歩度のカウンタでの天測ｒ、ｒ、破低幽埋緩急周
期のゲイト時間を必要とし腕時計の製造に際し多大の調
整時間を安している。第３図（ａ）に第１図構成の腕時
計のモータ出力ＯＵ　Ｔ　１　、０ＵＴ２、リセット端
子Ｒの信号状態のタイムチャートを示した。図中の３０
１ｒｃモータ駆動パルス、３０２で示される時刻で前述
の論理緩急動作が行なわれたことケ示す。この場合の１
理緩急周期に１０式である。もちろん０ＵＴ１，０ＵＴ
２の信号によりステップモータは１秒毎に運針される。The frequency of the crystal oscillator, that is, the time interval, can be adjusted by changing the load level of the crystal oscillator on the 13 trimmer capacitors, which is the time standard of the F watch. Further, the p rate is also corrected by logical operation based on the data of the cooking speed/speed terminal A1 of 19. This rate correction can be realized, for example, by the cooking speed and speed circuit shown in Fig. 5, but the principle is that the time adjustment is performed by periodically transitioning the counter state of the timer, and as a result, the rate by this means is based on the logical speed and speed operation cycle. In this case, the averaged fc value is given by the celestial measurement r, r, which is given by the counter of the watch rate, and requires gate time for the break-low-burial slow-fast cycle, which saves a lot of adjustment time when manufacturing the watch. ing. FIG. 3(a) shows a time chart of the signal states of the motor outputs OUT 1 and 0UT2 and the reset terminal R of the wristwatch having the configuration shown in FIG. 30 in the diagram
1rc motor drive pulse, which indicates that the above-mentioned logical speed and speed operation was performed at the time indicated by 302. 1 in this case
There are 10 formulas in the period of rationality, slowness, and suddenness. Of course 0UT1,0UT
The step motor is moved every second by the signal No.2.

デジタル時計の場合には０ＵＴ１，０１ｌＴ２のかわり
に他に同様な時間信号を出力することに上記アナログ時
計と同一な時間調量がｉｑ龍なことｒＸ、言うまでもな
い。以上に従来の腕時計の場合であるが最近になって特
にアナログ時計の場合に於いてステップモータの負荷が
日送り車の送！１１時とそうでない場合等で変動するこ
とに適応してモータトルクｔモータ駆動のパルス巾を増
菖して制御する方式が使用され始めている。この方式に
一般にはパルス巾制御方式と呼ばれてい心。この方式ｒ
採用した腕時計のモータ出力信号のタイムチャートは第
６図（ａ）の場合と異なりモータの非回転時の補正パル
ス等も出力されるため４１図の１１で示されるカウンタ
でに単純には計測不可能となる。第３図（ｂ）に当該腕
時計の０ＵＴＩ、０ＵＴ２出力信号のタイムチャート上
水す。３０１が第３図（ａ）の３０１と同等な役割ｔに
た丁駆動パルス、３０３μ前記モ一タ非回転時の補正パ
ルスである。この場合にも＠理緩急に３０２の時刻に１
０ｓｅｃ周期で行なわれていることｔ示す。本発明は以
上説明したパルス巾制御【採用した腕時計にも通用でき
る新しい歩度の測定と調量方法ｔ４えゐ装置を提供すゐ
ものである。次に不発明になる歩度調整信号の概要を説
明する。第２図に該装置を用いて腕時計の歩匪、ｉｉ１
壷を行なう際の構成ｒ示す。図中谷部位の名称に、１２
・・・水晶振動子、１３・・・トリマコンデンサ、２３
・・・腕時計用工Ｃ１１４・・・水晶発振器ドレイン端
子、１５・・・水晶発振器ゲイト端子。Needless to say, in the case of a digital clock, the same time adjustment as the analog clock is achieved by outputting other similar time signals instead of 0UT1, 01lT2. The above is the case with conventional wristwatches, but recently, especially in the case of analog watches, the load on the step motor is the same as that of the date wheel. A control method has begun to be used in which the motor torque t is controlled by increasing the pulse width of the motor drive in response to variations such as when the time is 11 o'clock and when it is not. This method is generally called the pulse width control method. This method r
The time chart of the motor output signal of the adopted wristwatch differs from the case shown in Fig. 6(a) because correction pulses etc. are also output when the motor is not rotating, so it cannot be simply measured by the counter shown at 11 in Fig. 41. It becomes possible. FIG. 3(b) shows a time chart of the 0UTI and 0UT2 output signals of the wristwatch. 301 is a driving pulse having the same role as 301 in FIG. 3(a), and 303μ is a correction pulse when the motor is not rotating. In this case as well, 1 at the time of 302 in @Rikukyu
t indicates that the process is performed at a period of 0 sec. The present invention provides a new rate measurement and metering method (t4) which can be applied to wristwatches employing the pulse width control described above. Next, an outline of the inventive rate adjustment signal will be explained. Figure 2 shows the accuracy of a wristwatch using this device, ii1
The configuration when making a pot is shown. In the name of the Nakatani part in the figure, 12
...Crystal resonator, 13...Trimmer capacitor, 23
...Wristwatch C114...Crystal oscillator drain terminal, 15...Crystal oscillator gate terminal.

１６．１７・・・モータ駆動出力端子、１Ｂ・・・シス
テムリセット端子、１９・・・１埋緩急設定端子、２０
・・・歩度調整信号出力端子、２１・・・十寛源端子。16.17...Motor drive output terminal, 1B...System reset terminal, 19...1 buried slow/sudden setting terminal, 20
...Rate adjustment signal output terminal, 21...Jukangen terminal.

２２・・・電源端子、２３ｏ・・・本発明になる歩度調
整装置、２３０中の２６１・・・電源回路部、２３２・
・・周波数基準源、２３５・・・周期カウンタ、２３４
・・・演算回路部、２３５・・・制御回路、２３６・・
・表示回路、２６７・・・外部標準周波数信号入力端子
である。22... Power supply terminal, 23o... Rate adjusting device according to the present invention, 261 in 230... Power supply circuit section, 232...
... Frequency reference source, 235 ... Period counter, 234
...Arithmetic circuit section, 235...Control circuit, 236...
-Display circuit, 267...External standard frequency signal input terminal.

電源回路８１１１２３１より歩度調整装置の谷部と腕時
計ＩＣＶＣ電圧が供給さｎる。２３７の外部信号か２３
２の内部基準信号のどちらか一万がカウンタ２３３のク
ロックとして供給され勾。カウンタ２３３で得られたＴ
の周期データは２３４の演算回路部で付定の計算式に錬
って計昇嘔れ結果ｔ２３６の表示装置で表示する。２５
５の制御回路に少度、ｓ１整装置２３１Ｊから腕時計Ｉ
Ｃへ測定のタイミングに合わせてシステムリセット信号
２出力する。該リセット信号の出力は歩度測定時間盆著
しく短縮させる目的で使用する。従来の第１図の構成で
腕時計の歩度を年間時間精度にして１０秒／年以内の誤
差におさめるためには１／１００〜２／１ｏ。A power supply circuit 8111231 supplies the trough of the rate adjustment device and the ICVC voltage of the wristwatch. 237 external signal or 23
Either one of the two internal reference signals is supplied as a clock to the counter 233. T obtained by counter 233
The cycle data is processed by an attached calculation formula in the arithmetic circuit unit 234 and displayed on the display device of the total elevation/lowering result t236. 25
5 control circuit, from s1 adjustment device 231J to wristwatch I
2 system reset signals are output to C in accordance with the measurement timing. The output of the reset signal is used for the purpose of significantly shortening the rate measurement time interval. With the conventional configuration shown in Figure 1, in order to keep the accuracy of the wristwatch within 10 seconds/year, the rate must be 1/100 to 2/1o.

秒／日の精度の歩度に合わせ込む心安がある。こＡ葡行
なうににトリマコンデンサの修正を数回性なう必安があ
り結果として論理緩急周期１８秒では数十秒の調整時間
を要して極めて能率的でない。There is peace of mind knowing that the rate is accurate to seconds/day. It is necessary to correct the trimmer capacitor several times in order to carry out this process, and as a result, the adjustment time of several tens of seconds is required for a logical adjustment period of 18 seconds, which is extremely inefficient.

第４図は第２図に於いて調整の対象となる腕時計のＩＣ
の歩度調整信号Ｔのもつタイムチャートの一実施例であ
る。信号Ｔｒｃ例えばデユティ５０％の１６Ｈ２の万形
仮である。リセット信号Ｒが論理レベルのＨ状態の区間
ＡとＢでは調理緩急動作は行なわれない。図中の５０２
の矢印は論理緩急動作の起きる時刻を示している。仮っ
てｔｌの周期中には時刻修正が鰭こなゎれず、ｔ２）Ｉ
！ｄ期中には時刻修正が起われる。第４図のタイムチャ
ートにもとづき腕時計の歩度ａ４整は以下のｆｉ９行な
われる。Figure 4 shows the IC of the wristwatch that is subject to adjustment in Figure 2.
This is an example of a time chart of the rate adjustment signal T of . The signal Trc is, for example, 16H2 with a duty of 50%. In sections A and B where the reset signal R is in the logic level H state, the cooking speed and speed operation is not performed. 502 in the diagram
The arrows in the figure indicate the times at which logical slowing and slowing operations occur. Suppose that the time adjustment is not completed during the period of tl, and t2)I
! Time adjustment occurs during period d. Based on the time chart of FIG. 4, the rate a4 of the wristwatch is adjusted as follows fi9.

ｖ＠螢工程のステップ？表わすと第６図の様にな／）。v@Firefly process steps? It is expressed as shown in Figure 6/).

ＭＯＤＥＩの操作で対象となる腕時計ＩＯの論理緩急状
態数、Ｍ　ｆ　１つのｔ、とｔＲＬり真出す／）（状態
数Ｍについてに後述するン。By operating MODEI, the number of logical fast/fast states of the target wristwatch IO, M f 1 t, and tRL are calculated. (The number of states M will be described later.)

しかる後リセット信号Ｒｔ論理レベルのＨとし次の歩１
ｆｆＡ整モードであるＭＯＤＥＩへ移行する。After that, set the reset signal Rt logic level to H and take the next step 1.
Transition to MODEI, which is the ffA adjustment mode.

このモードに於ては歩度調整装置は継杭して時刻修正の
行なわ几ていない周期Ｔ１１　Ｔｔ　＊　ＴＢ　　（第
４図参照）會計廁しすでに求めた状態数Ｍより実際の腕
時計歩度會演算し表示する。ＭＯＤＥ…状態では作業者
又ｒＣ調歴システムは第２図１３のトリマコンデンサ會
断続的に回転し前記表示１１１が目標の規格内にはいっ
たことｔ判定して歩度の調整作業を修了する。第４図刀
為ら推測できる様に調整に要する時間は１個当９　（１
／１６）Ｘ　４〜６秒程度で極めて短時間で終了する。In this mode, the rate adjustment device continues to adjust the time.The period T11 Tt * TB (see Figure 4) is used to calculate and display the actual wristwatch rate from the number of states M that has already been calculated. do. In the MODE state, the operator or the rC adjustment history system intermittently rotates the trimmer capacitor shown in FIG. 2 and determines that the display 111 falls within the target specification, completing the rate adjustment work. As can be estimated from Figure 4, the time required for adjustment is 9 (1
/16)X It finishes in an extremely short time, about 4 to 6 seconds.

最恢に前述の状態数Ｍと本発明になる歩度調整装置の少
裳算出式について説明する。　Ｍｋ求めるに当り調理緩
、私の原理について第５図を参照しながら説明すゐ。Finally, the number of states M mentioned above and the formula for calculating the rate adjustment device according to the present invention will be explained. When determining Mk, I will explain my principle of slow cooking with reference to Figure 5.

第５図の谷部位の名称ｒｃ５００・・・水晶発振器。The name of the valley part in Fig. 5 is rc500...Crystal oscillator.

５０１〜５０３・・・容性の分周器、５２１〜５２５・
・・ＯＲゲイ）、５３１〜５３５・・・データ横出用プ
ルダウントランジスタ、Ａ１〜Ａ５・・・−理緩急状態
の設定スイッチ、５１ｕ・・・バツファインノく一タ５
４０．５５０・・・＃ａ埋緩ａ、ａ作制御領号である。501-503... Capacitive frequency divider, 521-525.
...OR gay), 531-535...pull-down transistor for data output, A1-A5...-setting switch for rational, slow, and rapid states, 51u...buff fine notch 5
40.550...#a is a filling/relaxing a, a operation control area.

第５図の回路動作は医の様に行なわれる。クロック信号
ψｔカウントする竹分周益ｙｙｔ〜ＦＦ４の状態Ｑが論
理レベルの０でかつＦＦ５が１に遷移した直後にデータ
Ａ１〜Ａ５の論理状態を絖与込ように制＃信号ｓａｏ、
５ｓｏ２動作させる、抗み込１れたデータは、ＦＦ１〜
ＦＦａ葡Ａ１（、＝１〜４）の状態δ１が１の時セット
してＱ＝１とする。又Ａ５の状態δ５が１の場合にはＦ
Ｆ！Ｍ！”リセットする。この動作により得られる時刻
修正鴛ΔＴは （゛ΔＴン０は進み論理緩急を意味する）但し、ｆＣは
クロックφの周談畝である、当時側修正が論理緩急の動
作が行なわれる周期Ｔｃ毎に行なわれた場付の鋼埋緩急
重ηはｔｌ）よりで得られる。ここでＭｒ浦埋緩急の状
態数と短銃する。このＭ（整数）上第４図の周期１．　
、１．　　より求める方法を次に説明する。歩度、１１
長信号Ｔの公称周期’Ｔ：　Ｔ’　＋論理緩急の動作周
期（公称）會Ｔｃとして比、Ｎ＝Ｔｃ／Ｔｅ’ｚ用いれ
ば状態数Ｍに次の様に導びける。The circuit operation of FIG. 5 is performed in a medical manner. Immediately after the state Q of the clock division gain yyt to FF4 counted by the clock signal ψt is at logic level 0 and FF5 transitions to 1, the control # signal sao is applied so as to input the logic state of the data A1 to A5.
5so2 is operated, the data that has been pushed back is FF1~
When the state δ1 of FFa A1 (,=1 to 4) is 1, it is set and Q=1. Also, if the state δ5 of A5 is 1, F
F! M! ”Reset. The time correction value ΔT obtained by this operation is (ΔT 0 means advance logical adjustment). However, fC is the clock φ round trip, and the time correction is performed by logical adjustment. The steel embedding, loosening, and quickening η performed in each period Tc is obtained from tl).Here, it is expressed as the number of states of Mr.
, 1. A method for determining this will be explained next. rate, 11
If the ratio N=Tc/Te'z is used as the nominal period 'T' of the long signal T: T' + the operating period (nominal) of the logical speed and speed Tc, the number of states M can be derived as follows.

より（２）式？用いて 但し記号〔〕は四捨五入による整数化記号である。Ｍの
、Ｊ！出棺度μｔ、＝ｔ、＝ｏ、ｓ秒、Ｔｃ＝１０秒の
場合につき試作装置で確認しｆｃ紹釆１０−１と充分な
Ｎ度が得られている。さらに、このＭと第４図の測足周
期’ｒ、　ｌ　’ｒ、　ｔ・・・Ｔｉ・・・盆用いて腕
時計の歩度Ｈに で与えら几ることに容易にわかる。不発明になる方法に
よる前述の試作装置の場合の歩１ｉ　Ｈの測定積度ホ±
Ｉｘ　Ｉ　Ｑ−”　Ｓ／Ｄ　（約±ＩＸＩＱ−’）が得
られてお９通常の年産時計と呼ば扛ている超尚梢度の歩
度調整に対しても光分な舖度である。以上詳細に説明し
７’Ｃ通９本発明になる歩度調整装置は極めて短時間に
棺肛良く腕時計の歩度調整が可能であり腕時計コストの
低減に薔与できるものであり、今後多大のメリットが期
待できる。Equation (2)? However, the symbol [ ] is a symbol for rounding off to an integer. M's, J! When the unloading degree μt, = t, = o, s seconds, Tc = 10 seconds was confirmed using a prototype device, a sufficient N degree of 10-1 fc was obtained. Furthermore, it is easy to see that the rate H of the wristwatch is given by using this M and the foot measurement periods 'r, l'r, t... Ti... in Figure 4. The measured integral value of step 1i H in the case of the above-mentioned prototype device according to the non-inventive method
Ix I Q-'' S/D (approx. The rate adjustment device according to the present invention, which will be explained in detail in Section 7'C 9, is capable of adjusting the rate of a wristwatch in a very short time and with good precision, and can help reduce the cost of wristwatches, and is expected to have great benefits in the future. can.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図に従来の腕時計の′）ｊｆ一度調螢時の構成ケボ
す図。第２図μ本発明になゐ夛＃：、調整装置の１構成
図と誤シ髪調整装置ケ用いた新しい少髪調整の俳成奮示
す図であり。第３図（ａ）　（ｂ）は従来及び耕しい調
螢方法に於るモータ駆動出力タイミングと調理緩急ｇＪ
作タイミングを示すタイミングチャートである。第４図
ｔｌ新しい方法に用いゐ腕時計工Ｃの歩度調坐１ｄ号Ｔ
とリセットミニ号Ｈのタイムチャートであめ。第５図は
論理緩急回路の一般的構成を示す回路図である。第６図
は本発明にな／）第２図歩度調整装置の勧ｒ「勿示すフ
ローチャート図である。 １２・・・水晶振動子 １３・・・トリマコンデンサ １０．２３・・・腕時計工Ｃ ２３０・・・歩［調整装置 ２０・・・歩度調整信号端子 １９・・・論理緩急設定端子 以　　　上 第２図 第３図 第４図 ｃ＋２ 第５図 でΔθ図 ４８５−Figure 1 shows the structure of a conventional wristwatch that is wrinkled once it is adjusted. Figure 2 is a diagram illustrating the construction of an adjustment device and the success of a new method of adjusting short hair using the hair adjustment device. Figures 3(a) and 3(b) show the motor drive output timing and cooking speed gJ in the conventional and detailed firefighting methods.
3 is a timing chart showing operation timing. Figure 4 tl Watchmaker C's rate control seat No. 1d T used for new method
And the time chart of Reset Mini H. FIG. 5 is a circuit diagram showing a general configuration of a logic adjustment circuit. Figure 6 is a flowchart of the present invention/) Figure 2 is a flowchart of the rate adjustment device. ...Step [adjustment device 20...Rate adjustment signal terminal 19...Logical slow/sudden setting terminal or higher Fig. 2 Fig. 4 Fig. 4 c+2 In Fig. 5, Δθ diagram 485-

Claims (1)

【特許請求の範囲】[Claims] 歩度の調整手段として論理回路による粗調整とトリマコ
ンデンサ等のアナログ的な微調螢手Ｅｋ並設している水
晶腕時計の歩度測定装置に於いて、＃Ｎ埋的時刻修正を
行った時刻を含む腕時計の出力する時間周期と論理的時
刻修正の行なわれていない時間周期よＶ論理的夛度詞整
量の状態数ケ算出した後、前記歩度のアナログ的微調螢
素子を可変した後の論理的時刻修正の行なわれていない
周期を測定して、前記状態ａｋ用いて歩舵を算出し表示
することケ％徴とする歩度ｔＡ姫装置。In the rate measuring device of a quartz wristwatch, which has coarse adjustment using a logic circuit and analog fine adjustment such as a trimmer capacitor as a rate adjustment means, a wristwatch that includes the time when #N implicit time correction has been performed. After calculating the number of states of the logical exponent variable from the output time period and the time period without logical time correction, the logical time after varying the analog fine adjustment element of the rate is calculated. The rate tA princess device measures the uncorrected period and calculates and displays the gait using the state ak.