JPS59110376A - Switching regulator - Google Patents
Switching regulatorInfo
- Publication number
- JPS59110376A JPS59110376A JP21680482A JP21680482A JPS59110376A JP S59110376 A JPS59110376 A JP S59110376A JP 21680482 A JP21680482 A JP 21680482A JP 21680482 A JP21680482 A JP 21680482A JP S59110376 A JPS59110376 A JP S59110376A
- Authority
- JP
- Japan
- Prior art keywords
- waveform
- output
- main switch
- voltage
- period
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は多出力のスイッチングレギュレータに係り、特
にスイッチングの損失を軽減したスイッチングレギュレ
ータに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multi-output switching regulator, and particularly to a switching regulator with reduced switching loss.
スイッチングレギュレータは、直流電圧をオンオフスイ
ッチにより交流に変換し、変圧器で変圧して再び整流し
、所望の電圧の直流を発生するものである。A switching regulator converts DC voltage into AC using an on/off switch, transforms the voltage using a transformer, and rectifies it again to generate DC at a desired voltage.
第１図は、フォワード方式の多出力スイッチングレギュ
レータの例を示すもので、入力電圧Ｅは主スィッチ１に
よりオンオフされて交流に変換され、主トランス２で変
圧されたのち整流ダイオード６、転流ダイオード４．チ
ョークトランス５．及びコンデンサ６で整流され、出力
Ｖｌが生滅される。パルス幅変調回路７は、主スィッチ
１のオンオフ比を制御して、出力電圧■１を調整する。Figure 1 shows an example of a forward type multi-output switching regulator, where the input voltage E is turned on and off by a main switch 1 and converted to AC, transformed by a main transformer 2, and then passed through a rectifier diode 6 and a commutator diode. 4. Choke transformer 5. It is rectified by the capacitor 6, and the output Vl is generated or depleted. The pulse width modulation circuit 7 controls the on/off ratio of the main switch 1 to adjust the output voltage (1).
出力電圧■２は、出力電圧■ｌを入力として、降圧型チ
ョツノ（方式のスイッチングレギュレータにより生成さ
れる。即ち、）くパルス幅変調回路６０により制御され
るスイッチ８で出力■１をオンオフし、これを転流ダイ
オード９．チョークトランス１０．及びコンデンサ６１
で平滑する。The output voltage (2) is generated by a step-down switching regulator using the output voltage (1) as an input. In other words, the output (1) is turned on and off by a switch 8 controlled by a pulse width modulation circuit 60. Connect this to a commutating diode 9. Choke transformer 10. and capacitor 61
Smooth with .
このスイッチングレギュレータに於る、主スイツチ１の
コレクタ・エミッタ間電圧波形ＶＣＥコレクタ電流波形
ｒｃ ｌ及びこれらの波形から導出されるスイッチ損失
Ｐｃを第６Ａ図に示す。In this switching regulator, the collector-emitter voltage waveform VCE collector current waveform rcl of the main switch 1 and the switch loss Pc derived from these waveforms are shown in FIG. 6A.
同図から明らかなように、主スィッチ１のターンオン、
ターンオフ時の過渡期の損失が太きい、このような主ス
ィッチの過渡期の損失を減じ効率をあげる一方法として
スイッチがバイポーラトランジスタの場合、適当な逆ベ
ース電流、を流せるドライブ回路を付加する方法がある
。もちろんＭＯ８Ｉ−ランジスタの場合も必要ならばド
ライブ回路を付加する。しかし、このドライブ回路は構
成が複雑で、高価となる欠点があった。As is clear from the figure, when main switch 1 is turned on,
If the switch is a bipolar transistor, one way to reduce the loss during the transition period and increase the efficiency of such a main switch, where the loss during the transition period at turn-off is large, is to add a drive circuit that can flow an appropriate reverse base current. There is. Of course, in the case of MO8I-transistor, a drive circuit is added if necessary. However, this drive circuit has the drawback of being complex and expensive.
第２図は別の従来例を示すもので、出力■１は第１図の
ものと同じフォワード方式スイッチングレギュレータで
生成している。一方、出力■２は、主トランス１２を多
巻線にし、クロスレギユレーションにより生成する。こ
のクロスレギユレーションの誤差の補償はスイッチ１８
にて行う。FIG. 2 shows another conventional example, in which the output (1) is generated by the same forward switching regulator as in FIG. On the other hand, output (2) is generated by making the main transformer 12 have multiple windings and performing cross regulation. This cross regulation error is compensated for by the switch 18.
It will be held at
即ち、主スィッチ１１のオン期間内にスイッチ１８主ス
イツチ１１はオフとなる。この回路の主スィッチ１１の
コレクタ・エミッタ間電圧波形ＶＣＥ＋コレクタ電流波
形Ｉｃ、及びこれらの波形から導出されるスイッチ損失
ｐｃを第３Ｂ図に示す。同図にみられるように、主スィ
ッチ１１のターンオン時にはスイッチ１８オフで負荷が
軽減されているから、ターンオン時の損失は低減される
が、ターンオフ時は第１図の回路の場合よりいくぶん多
く、主スィッチ１１の損失低減効果はほとんど得られな
い。That is, the switch 18 and the main switch 11 are turned off during the on period of the main switch 11. FIG. 3B shows the collector-emitter voltage waveform VCE+collector current waveform Ic of the main switch 11 of this circuit and the switch loss pc derived from these waveforms. As shown in the figure, when the main switch 11 is turned on, the load is reduced by turning off the switch 18, so the loss at the time of turn-on is reduced, but at the time of turn-off, the loss is somewhat higher than in the case of the circuit shown in Figure 1. The loss reduction effect of the main switch 11 is hardly achieved.
このように第２図にあげた従来例も、第１図の場合と同
様、高効率を得ようとすると主スィッチに複雑なドライ
ブ回路が必要となり、高価となる欠点がある。As described above, the conventional example shown in FIG. 2 also has the drawback that, in order to obtain high efficiency, a complicated drive circuit is required for the main switch, making it expensive.
本発明の目的は、上述した従来技術の欠点をなくし、簡
単で安価な構成で、かつ主スィッチの過渡期の損失を低
減した、多出力のスイッチングレギュレータを提供する
にある。SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-output switching regulator that eliminates the drawbacks of the prior art described above, has a simple and inexpensive configuration, and reduces loss during the transition period of the main switch.
本発明は、クロスレギユレーション方式に於て、クロス
レギユレーション補償用スイッチを主スイツチ転流時に
常にオフとなるように制御することによって、主スイツ
チ転流時の負荷電流を減じるように構成したことを特徴
とするものである。In the cross regulation system, the present invention is configured to reduce the load current during main switch commutation by controlling the cross regulation compensation switch so that it is always turned off during main switch commutation. It is characterized by the fact that
以下、本発明の一実施例を２出力フワオ一ド方式スイッ
チングレギュレータで説明する。捷ず通常用いられる第
２図の基本パルス幅変調回路１７の構成および動作は第
４Ａ図、第４１（図に示すようなものである。鋸歯状波
発生回路１７１（第２図では省略している）からの鋸歯
状波ａと、出力電圧Ｖ、を適当に分圧しだ直流電圧すを
コンパレータ１７２で比較しａ＞ｂとなるＴｏｎ期間、
ドライバ１７シのベースをハイレベルにスル。An embodiment of the present invention will be described below using a two-output floating type switching regulator. The configuration and operation of the basic pulse width modulation circuit 17 shown in FIG. 2, which is normally used without changing the structure, are as shown in FIGS. 4A and 41. The sawtooth wave a from the output voltage V is compared with the DC voltage S by the comparator 172, and the Ton period is such that a>b.
Driving the bass of driver 17 to a high level.
このＴｏｎ 期間主スィッチ１゛１はオンとなる。これ
によって出力電圧が上昇（下降）したらノ＜１１１幅Ｔ
ｏｎを狭める（広げる）ように動作するから出力電圧Ｖ
ｌが一定に制御される。このパルス幅変調回路１７は従
来と同じ構成であるが、本実施例では、パルス幅変調回
路２２の構成が上記の回路１７とは異っている所に特徴
があり、全体の回路構成は第２図と同じである。。During this Ton period, the main switch 1'1 is turned on. If the output voltage rises (falls) as a result of this, then the width T
Since it operates to narrow (widen) on, the output voltage V
l is controlled to be constant. This pulse width modulation circuit 17 has the same configuration as the conventional one, but the present embodiment is characterized in that the configuration of the pulse width modulation circuit 22 is different from the above circuit 17, and the overall circuit configuration is the same as that of the conventional one. It is the same as Figure 2. .
第５Ａ図は本実施例におけるパルス幅変調回路１７と２
２の詳細結線、第５Ｂ図は各部波形ケ示す図である。パ
ルス幅変調回路１７は、前述したように鋸歯状波ａを一
方の入力、出力電圧Ｖｌを分圧した直流′電圧すを他方
の入力とし、その出力は主巧イツチ１１に接続される、
パルス幅変調回路２２は、基本パルス幅変調回路１７と
同構成の回路１７を基本とするが、その入力は鋸歯状波
ａでなく、同図に示したような電圧波形ａ１である。FIG. 5A shows pulse width modulation circuits 17 and 2 in this embodiment.
FIG. 5B is a diagram showing the waveforms of each part. As mentioned above, the pulse width modulation circuit 17 has one input of the sawtooth wave a and the other input of the DC' voltage obtained by dividing the output voltage Vl, and its output is connected to the main switch 11.
The pulse width modulation circuit 22 is basically a circuit 17 having the same configuration as the basic pulse width modulation circuit 17, but its input is not a sawtooth wave a but a voltage waveform a1 as shown in the figure.
この波形ａ１は次のようにして生成される。ｆａｌｌち
第５Ａ図のワンショットマルチバイブレータ２２１は、
波形ａの立ち下がりエツジでトリガがかかり、その出力
が波形ａの周期よりも少し短い時間だけローレベルにな
り、その抜法の立下り迄の時間τだけハイレベルとなる
ようなパルスを出力する。従って、この時間τの間はト
ランジスタ２２２がオンし、バッファアンプ２２６がら
出力された波形ａをこのオン期間中接地して波形ａｌが
生成される。そしてこのような波形ａ１と、出力電圧■
２を適当に分圧した直流ｂ＋とを、変調回路２２内のコ
ンパレータで比較して出力ｃｌ（第５１１図）を得、こ
れによってスイッチ１８を制御する。従って、クロスレ
ギユレーション誤差補償用のスイッチ１８は、主スィッ
チ１１のオン時間内に、オフ、オンの動作を行い、主ス
イツチ１１０オンへの転流時のみでなく、オフへの転流
時にもスイッチ１Ｂはオフして、主スィッチ１１の負荷
電流を軽減させるので、この時の主スィッチ１１の損失
Ｐｃは、第６Ｃ図に示すよう罠大幅に低減される。This waveform a1 is generated as follows. The one-shot multivibrator 221 shown in FIG. 5A falls below.
A trigger is applied at the falling edge of waveform a, and the output is low level for a period slightly shorter than the period of waveform a, and outputs a pulse that remains high level for the time τ until the falling edge of waveform a. . Therefore, during this time τ, the transistor 222 is turned on, and the waveform a output from the buffer amplifier 226 is grounded during this on period to generate the waveform al. Then, such a waveform a1 and the output voltage ■
A comparator in the modulation circuit 22 compares the DC voltage b+ obtained by appropriately dividing the voltage of 2 to obtain an output cl (FIG. 511), which controls the switch 18. Therefore, the switch 18 for cross regulation error compensation performs off and on operations during the on time of the main switch 11, and not only when the main switch 110 is commutated to on but also when commutated to off. Since the switch 1B is also turned off to reduce the load current of the main switch 11, the loss Pc of the main switch 11 at this time is significantly reduced as shown in FIG. 6C.
なお、以上の実施例とは異る方法として、パルス幅変調
回路１７．２２はともに第４Ｂ図の特性とし、その代り
に、パルス幅変調回路２２０入力すについて、ターンオ
フ直前のある期間、外部より強制的にそのミグレベルを
鋸歯状波の最大値よりも大きくするような構成にしても
、同じ効果を得ることができる。In addition, as a method different from the above embodiment, the pulse width modulation circuits 17 and 22 both have the characteristics shown in FIG. The same effect can be obtained by forcibly setting the MIG level higher than the maximum value of the sawtooth wave.
本発明の他の実施例を第６Ａ図に示す。本実施例は第２
図のパルス幅変調回路１７の構成を、第４Ａ図で説明し
た基本パルス幅７１！、７４１１．１回路１７に代って
第６Ａ図の回路１７ａでおきかえ、パルス幅変調回路２
２は第４Ａ図の基本パルス幅変調回路１７と同じとした
場合である。波形を第６Ｂ図に示す。パルス幅変調回路
２２は鋸歯状波ａを一方の入力、出力電圧■２を分圧し
た直流電圧ｂ１を他方の入力とし、補助スイッチ１８に
接続される。Another embodiment of the invention is shown in FIG. 6A. This example is the second
The configuration of the pulse width modulation circuit 17 shown in the figure is the basic pulse width 71! explained in FIG. 4A! , 7411.1 The circuit 17 is replaced with the circuit 17a shown in FIG. 6A, and the pulse width modulation circuit 2
2 is a case where the circuit is the same as the basic pulse width modulation circuit 17 of FIG. 4A. The waveform is shown in Figure 6B. The pulse width modulation circuit 22 is connected to the auxiliary switch 18, with the sawtooth wave a as one input and the DC voltage b1 obtained by dividing the output voltage (2) as the other input.
パルス幅変調回路１７ａでは、鋸歯状波ａを一方の入力
とし、出力電圧Ｖ＋を分圧した直流′電圧すを他方の入
力とする基本パルス幅変調回路１７の出力ｄを得、ワン
ショットマルチハイブレーク１７４は、この波形ｄの立
下りエツジをト１１ガとして時間τ】だけハイレベルと
なる出力ｅを生成する。従って波形ｄとｅのＮＯＲをノ
ア回路１７５でとり、ドライバ用のトランジスタ１７６
から反転して出力すると、主スイツチ１１ヲオンさせる
信号Ｃは、回路１７の出力ｄの後縁をτｌだけ延長させ
た波形となり、主スィッチ１１のターンオフ時にもクロ
スレギユレーション誤差補償用のスイッチ１８は確実に
オフしており（同図は波形ｃ＋ｆｉ−照）、主スィッチ
１１のターンオン、オフ時点ともにその９荷が軽減され
る。In the pulse width modulation circuit 17a, the output d of the basic pulse width modulation circuit 17, which has the sawtooth wave a as one input and the DC' voltage S obtained by dividing the output voltage V+ as the other input, is obtained. The break 174 generates an output e that becomes high level for a time τ] using the falling edge of the waveform d as a trigger. Therefore, the NOR circuit 175 takes the NOR of waveforms d and e, and the driver transistor 176
When the main switch 11 is inverted and output, the signal C that turns on the main switch 11 has a waveform that extends the trailing edge of the output d of the circuit 17 by τl, and even when the main switch 11 is turned off, the signal C that turns on the main switch 11 has a waveform that is extended by τl. is reliably turned off (waveform c+fi- in the figure), and the load is reduced both when the main switch 11 is turned on and off.
本発明のもう一つの他の実施例を第７Ａ川に示す。その
各部波形を第７Ｂ図に示す。本実施例は全体の回路構成
およびパルス幅変調回路１７゜２２は、全て第２図およ
び基本パルス幅変調回路１７と同じである。異なるのは
第７Ａ図に示すように、発振器が鋸歯状波発生回路１７
１に代って二角波発生回路１７１ａが用いられている点
である。この実施例の場合、出力電圧Ｖ、を分圧しだｉ
ｈ流霜、圧すと出力電圧■２を分圧した直流■−圧ｂｌ
の関係がｂ＜ｂ＋であるように設定しておけば、１６１
図から明らかなように必ずクロスレギユレーション誤差
補償用のスイッチ１８は主スィッチ１１のターンオン及
びオフ時には必ず万フとなっており、所要の効果が容易
に得られる。Another embodiment of the invention is shown in River 7A. The waveforms of each part are shown in FIG. 7B. In this embodiment, the overall circuit configuration and the pulse width modulation circuits 17 and 22 are all the same as those in FIG. 2 and the basic pulse width modulation circuit 17. The difference is that the oscillator is a sawtooth wave generating circuit 17 as shown in FIG. 7A.
1 is replaced by a square wave generating circuit 171a. In this embodiment, the output voltage V is divided into i
When h current frost is applied, the output voltage ■2 is divided into direct current ■-pressure bl
If the relationship is set so that b<b+, then 161
As is clear from the figure, the switch 18 for cross regulation error compensation is always in the OFF state when the main switch 11 is turned on and off, and the desired effect can be easily obtained.
なお、以上の実施例では、２出カスイツチングレギユレ
ータについて説明したが、一般の多出力スイッチングレ
ギュし／−夕の場合にも適用可能なことは明らかである
。In the above embodiments, a two-output switching regulator has been described, but it is clear that the present invention can also be applied to a general multi-output switching regulator.
以上の説明から明らかなように、本発明によれば、多出
力スイッチングレギュレータの１次側（入力側）のＤＣ
−ＡＣ変換を行う王スイッチの過渡期の損失を簡単で安
価なドライブ回路により低減できるという効果があり、
経済的。As is clear from the above description, according to the present invention, the DC on the primary side (input side) of the multi-output switching regulator
- It has the effect of reducing the loss during the transition period of the main switch that performs AC conversion with a simple and inexpensive drive circuit.
Economic.
熱効率的、信頼性的に優れた構成を得ることができる。A configuration with excellent thermal efficiency and reliability can be obtained.
。.
第１図は従来のフォワード方式炙出カスイツチングレギ
ュレータの一回路例を示す図、第２図は他の従来例と本
発明の説明に用いた回路図第６Ａ図、第３Ｂ図及び第３
Ｃ図は従来回路と本発明の主スィッチのコレクタ・エミ
ッタ間電圧波形、コレクタ電流波形、及びスイッチ損失
を示す図、＊４Ａ図はパルス幅変調回路の説、明図、第
４Ｂ図は波形図、第５Ａ図は本発明の一実施例を示す図
、第５Ｂ図は波形図、第６Ａ図及び第７Ａ図は夫々本発
明の別の実施例を示す図、％６Ｂ図、第７Ｂ図は波形図
である。
１１・・・主スィッチ １２・・・主トランス１５
・・・整流ダイオード
１７、１７ａ・・・パルス幅変調回路
１８・・・クロスレギユレーション誤差補ｆａｔ 用ス
イッチ
２２・・・パルス幅変調回路
２３・τ・整流ダイオード
３２・・・鋸歯状波発生回路
３６・・・コンパレータ
１７１ ・・・鋸歯状波発生回路
１７１ａ・・・三角波発生回路
凰 １ 国
０
嵐 ２ 図FIG. 1 is a diagram showing an example of a circuit of a conventional forward type grilling switching regulator, and FIG. 2 is a circuit diagram of another conventional example and circuit diagrams used for explaining the present invention.
Figure C is a diagram showing the collector-emitter voltage waveform, collector current waveform, and switch loss of the main switch of the conventional circuit and the present invention, *Figure 4A is an explanation of the pulse width modulation circuit, and Figure 4B is a waveform diagram. , FIG. 5A is a diagram showing one embodiment of the present invention, FIG. 5B is a waveform diagram, FIGS. 6A and 7A are diagrams each showing another embodiment of the present invention, and FIGS. FIG. 11... Main switch 12... Main transformer 15
... Rectifier diodes 17, 17a... Pulse width modulation circuit 18... Cross regulation error compensation fat switch 22... Pulse width modulation circuit 23, τ, Rectifier diode 32... Sawtooth wave generation Circuit 36... Comparator 171... Sawtooth wave generation circuit 171a... Triangular wave generation circuit 凰 1 国 0 ARASHI 2 fig.
Claims (1)
流に変換したのち、複数の二次巻線を有するトランスの
一次巻線へ入力し、上記二次巻線の各出力を再び整流し
て複数の出力直流電圧を生成するように構成したスイッ
チングレギュレータに於て、上記出力直流電圧を調整し
安定化させるために上記二次巻線出力に挿入された第２
のトランジスタスイッチを、上記第１のトランジスタス
イッチの転流時に常にオフとなるように制御する制御手
段を設けたことを特徴とするスイッチングレギュレータ
。After the input DC voltage is converted into AC by a first transistor switch, it is input to the primary winding of a transformer having multiple secondary windings, and each output of the secondary windings is rectified again to generate multiple output DC voltages. In the switching regulator configured to generate a voltage, a second winding is inserted into the secondary winding output in order to adjust and stabilize the output DC voltage.
A switching regulator comprising a control means for controlling the transistor switch such that the first transistor switch is always turned off during commutation of the first transistor switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21680482A JPS59110376A (en) | 1982-12-13 | 1982-12-13 | Switching regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21680482A JPS59110376A (en) | 1982-12-13 | 1982-12-13 | Switching regulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59110376A true JPS59110376A (en) | 1984-06-26 |
Family
ID=16694145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21680482A Pending JPS59110376A (en) | 1982-12-13 | 1982-12-13 | Switching regulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59110376A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6158469A (en) * | 1984-08-29 | 1986-03-25 | Canon Inc | Power supply circuit and image-forming apparatus provided with same |
| JPH02228258A (en) * | 1989-02-27 | 1990-09-11 | Origin Electric Co Ltd | Control of multi-output switching regulator |
| JPH068457U (en) * | 1992-01-14 | 1994-02-04 | 株式会社オオタ | Manhole cover |
| WO2001054257A1 (en) * | 2000-01-21 | 2001-07-26 | Matsushita Electric Industrial Co., Ltd. | Power supply and electronic device using power supply |
-
1982
- 1982-12-13 JP JP21680482A patent/JPS59110376A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6158469A (en) * | 1984-08-29 | 1986-03-25 | Canon Inc | Power supply circuit and image-forming apparatus provided with same |
| JPH071375B2 (en) * | 1984-08-29 | 1995-01-11 | キヤノン株式会社 | Power supply circuit and image forming apparatus provided with this power supply circuit |
| JPH02228258A (en) * | 1989-02-27 | 1990-09-11 | Origin Electric Co Ltd | Control of multi-output switching regulator |
| JPH068457U (en) * | 1992-01-14 | 1994-02-04 | 株式会社オオタ | Manhole cover |
| WO2001054257A1 (en) * | 2000-01-21 | 2001-07-26 | Matsushita Electric Industrial Co., Ltd. | Power supply and electronic device using power supply |
| US6498734B1 (en) | 2000-01-21 | 2002-12-24 | Matsushita Electric Industrial Co., Ltd. | Power supply unit having reduced size and weight and an electronic apparatus using the same |
| KR100427099B1 (en) * | 2000-01-21 | 2004-04-17 | 마쯔시다덴기산교 가부시키가이샤 | Power supply and electronic device using power supply |
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