JPS59110115A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59110115A JPS59110115A JP22058882A JP22058882A JPS59110115A JP S59110115 A JPS59110115 A JP S59110115A JP 22058882 A JP22058882 A JP 22058882A JP 22058882 A JP22058882 A JP 22058882A JP S59110115 A JPS59110115 A JP S59110115A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- melting point
- high melting
- point metal
- silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 44
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 238000002844 melting Methods 0.000 claims abstract description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 26
- 239000010703 silicon Substances 0.000 claims abstract description 26
- 230000008018 melting Effects 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 150000002500 ions Chemical class 0.000 claims abstract description 14
- 239000002019 doping agent Substances 0.000 claims abstract description 12
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 9
- 238000010894 electron beam technology Methods 0.000 claims abstract description 6
- 239000013078 crystal Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 description 15
- 238000006243 chemical reaction Methods 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 239000012535 impurity Substances 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 5
- 239000003870 refractory metal Substances 0.000 description 5
- -1 phosphorus ions Chemical class 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 238000005275 alloying Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005755 formation reaction Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はシリコン半導体装置の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a silicon semiconductor device.
ＭＯＳ、ＩＣやバイポーラＩＣで代表されるシリコン半
導体装置においては最大動作周波数や集積度の向上を図
るため素子寸法の３次元的縮少が重要な課題となってい
る。特に、ＭＯ８ＩＣにおいてはチャネル長を１〜１．
５μｍ 程度以下にまで短縮するといわゆる短チヤネル
効果として癩られる閾値電圧のチャネル長依存性や、ソ
ース・ドレイン耐圧の低下等の重要な問題点が生じる。In silicon semiconductor devices represented by MOS, IC, and bipolar IC, three-dimensional reduction of element dimensions has become an important issue in order to improve maximum operating frequency and degree of integration. In particular, in MO8IC, the channel length is 1 to 1.
When the length is reduced to about 5 μm or less, important problems arise such as the dependence of the threshold voltage on the channel length, which is caused by the so-called short channel effect, and a decrease in source/drain breakdown voltage.
これらの問題は主として、ソースとドレイン間の距離が
ドレイン領域による空乏層の延びの程度あるいはそれ以
下にまで短かくなったためによるものである。These problems are mainly due to the fact that the distance between the source and drain has become as short as or less than the extension of the depletion layer by the drain region.
この問題、即ち、ドレイン空乏層の延びの影響を軽減す
るためには、ソース及びドレイン領域の深さ、即ち、ソ
ース及びドレイン領域の接合深さを浅くすることが有効
であることが知られている。In order to reduce this problem, that is, the influence of the extension of the drain depletion layer, it is known that it is effective to reduce the depth of the source and drain regions, that is, the junction depth of the source and drain regions. There is.
現在、接合深さが０．３μｍ 程度の比較的浅いｎ型ソ
ース・ドレイン層は砒素イオン注入によって形成するこ
とができる。しかし、こｐ程度の浅さのソース及びドレ
イン領域においても、その層抵抗は３０〜５０Ω／口と
いう比較的大きな値となる。また、ｐ型のソース・ドレ
イン層はボロンのイオン注入によって形成されるのが一
般的であるが、砒素イオン注入によるｎ型の場合ｌこ比
較して低抵抗でしかも浅い接合を形成することはさらに
難しく例えば接合深さ０．４μｍ程度の深さで、その層
抵抗は１００Ω／口程度以上の値となる。この様な高い
抵抗のソースあるいはドレイン層は、集積回路への応用
の場合の様にソースあるいはドレイン領域の延長がその
まま素子間の相互接続配線としても使用される場合には
その抵抗が無視し得ない値になってしまい信号の伝播遅
延や電圧低下の原因となる。チャネル長が１μｍ以下に
まで短縮された場合には、更に浅い接合深さが必要とな
り、従って層抵抗は益々大きくなりその層抵抗によるト
ランジスタや集積回路の性能の低下は一層深刻なものと
なる。Currently, relatively shallow n-type source/drain layers with a junction depth of about 0.3 μm can be formed by arsenic ion implantation. However, even in the source and drain regions having a shallow depth of about 100 nm, the layer resistance thereof is a relatively large value of 30 to 50 Ω/hole. Furthermore, while p-type source/drain layers are generally formed by boron ion implantation, it is difficult to form low-resistance and shallow junctions compared to n-type by arsenic ion implantation. Even more difficult, for example, at a junction depth of about 0.4 μm, the layer resistance reaches a value of about 100Ω/hole or more. The resistance of such a high-resistance source or drain layer can be ignored if the extension of the source or drain region is also used as interconnection wiring between devices, as in integrated circuit applications. This results in a signal propagation delay and voltage drop. When the channel length is reduced to 1 μm or less, an even shallower junction depth is required, and therefore the layer resistance becomes larger and the deterioration of the performance of transistors and integrated circuits due to the layer resistance becomes even more serious.
また、０．１〜０．２μｍ程度の浅い接合領域へのアル
ミニウム系金属によるオーミックコンタクトにおいては
いわゆるアロイスパイクと称される局部的拡散・合金化
反応が生じ基板との電気的短絡を引起し易いことが予想
される。この様に、単に不純物イオン注入で０．１〜０
．２μｍ程度の浅いソース・ドレイン層を形成すること
は電気抵抗やオーミックコンタクト等の点から好ましく
ないことが判る。In addition, in ohmic contact using aluminum-based metal to a shallow junction region of about 0.1 to 0.2 μm, a local diffusion/alloying reaction called an alloy spike occurs, which tends to cause an electrical short circuit with the substrate. It is expected that. In this way, by simply implanting impurity ions, 0.1 to 0
．． It can be seen that forming a shallow source/drain layer of about 2 μm is not preferable from the viewpoint of electrical resistance, ohmic contact, etc.
この問題を解決するためには金属硅化物層をソース・ド
レイン領域の表面に形成することが考えられる。しかし
、白金、パラジウム等の貴金属の硅化物を形成した場合
には、これらの貴金属の硅化物の熱安定性が十分でない
ために８５０℃以上のアニールを行えない欠点や、アル
ミニウム系金属と３５０℃程度の比較的低温で合金化反
応を生ずる欠点があり実用に供し難い。一方、モリブデ
ン、タングステン、タンタ／Ｌｚチタン等のいわゆる高
融点金属の硅化物の場合にはそれらの材料自身の耐熱性
という点においては問題はない。そこで、従来の技術を
用いてこれらの高融点金属の硅化物をソース・ドレイン
領域上に形成して低抵抗化を図るという目的のために応
用しようとすると次の３つの方法が従来考えられていた
。In order to solve this problem, it is conceivable to form a metal silicide layer on the surface of the source/drain region. However, when silicides of noble metals such as platinum and palladium are formed, there are drawbacks such as the inability to anneal at 850°C or higher due to insufficient thermal stability of these noble metal silicides, and the possibility of annealing at 350°C with aluminum-based metals. It has the disadvantage that alloying reactions occur at relatively low temperatures, which makes it difficult to put it into practical use. On the other hand, in the case of silicides of so-called high melting point metals such as molybdenum, tungsten, and tanta/Lz titanium, there is no problem in terms of the heat resistance of these materials themselves. Therefore, when trying to apply conventional techniques to form silicides of these high-melting point metals on the source/drain regions for the purpose of lowering the resistance, the following three methods have been conventionally considered. Ta.
第１の方法は所望の組成比の高融点金属の硅化物膜その
ものをスパッタリングや真空蒸着等の方法を用いて堆積
する方法である。しかし、この方法ではソース・ドレイ
ン領域以外の部分にも膜形成が行われてしまうために、
ソース・ドレイン領域等の所望の領域のみに自己整合的
に形成することは容易でない欠点がある。また、この方
法で形成した硅化物／Ｓｉオーミック接触は８００℃程
度以上のアニールによって特性が劣化し、その結果、ソ
ース・ドレイン領域の実質的な直列抵抗の増加を引き起
す欠点がある。The first method is to deposit a high melting point metal silicide film itself with a desired composition ratio using a method such as sputtering or vacuum evaporation. However, with this method, the film is formed in areas other than the source and drain regions, so
It has a drawback that it is not easy to form it in a self-aligned manner only in desired regions such as source/drain regions. Further, the characteristics of the silicide/Si ohmic contact formed by this method are deteriorated by annealing at a temperature of about 800° C. or higher, resulting in a disadvantage that the series resistance of the source/drain region increases substantially.
第２の方法は、高融点金属の硅化物そのもの堆積するの
ではなく、ソース・ドレイン領域等の所望の領域のシリ
コン表面を露出せしめてから、高融点金属膜の堆積を行
った後、アニールによって高融点金属とシリコンとを反
応させて硅化物を形成し、この後、未反応な高融点金属
をエツチングすることにより硅化物を選択的に残す方法
である。The second method is not to deposit the refractory metal silicide itself, but to expose the silicon surface in desired areas such as source/drain regions, deposit a refractory metal film, and then anneal it. This is a method in which a high melting point metal and silicon are reacted to form a silicide, and then the unreacted high melting point metal is etched to selectively leave the silicide.
しかし、この方法を実際に試みると高融点金属と高濃度
に不純物をドープしたシリコンとの反応の再現性や一様
性が著しく悪いことが判った。即ち、高融点金属とシリ
コンとの硅化物反応が殆ど生じない場合や、激しい反応
が生じる場合が試料間において生じた。また、硅化物反
応が進行した場合には、硅化物の均一性は良好でなく硅
化物／８ｉ界面の平担性は悪い等々の問題点がある外に
、硅化物形成は、シリコン露出部の端部から未露出部（
高融点金属膜が絶縁膜上にある領域）ヘハミ６出して生
じるために、自己整合的に高融点金属の硅化物を所望領
域番このみ形成するという点においても問題があること
が判明した。However, when this method was actually tried, it was found that the reproducibility and uniformity of the reaction between the high melting point metal and highly doped silicon were extremely poor. That is, there were cases in which the silicide reaction between the high melting point metal and silicon did not occur, and cases in which a severe reaction occurred among the samples. In addition, when the silicide reaction progresses, there are problems such as poor uniformity of the silicide and poor flatness of the silicide/8i interface. From the end to the unexposed part (
It has also been found that there is a problem in forming silicide of a high melting point metal only in a desired area in a self-aligned manner since the high melting point metal film protrudes from the area (region) on the insulating film.
第３の方法は、上記の第２のアニールによる方法に代っ
て、高融点金属／シリコン界面を混合する条件でイオン
注入を行いその後アニールを行う方法によって硅化物を
形成する方法である。ニス・ダブりｍ−・チー２７ （
Ｓ ａＷａ Ｃｈｉａｎｇ ） 氏等は、ジャーナル
・オフ・アプライド・フィジックス（Ｊｏｕｒｎａｌ
ｏｆ Ａｐｐｌｉｅｄ Ｐｈｙｓｉｃｓ ）誌、第５２
巻、第６号第４０２７〜４０３２頁（１９８１年６月）
に於いて、リンをモリブデン／シリコン構造にイオン注
入することを利用したモリフデン硅化物の形成技術につ
いて報告しており、硅化物反応の再現性が向上すること
や８５０℃までのアニール後では硅化物の均一性が維持
されることを報告している。しかしながら、この文献を
詳細に検討すると、８５０°Ｃ以上例えば１０００℃で
のアニールでは前記硅化物の均一性は著しく劣化してい
る。この様な不均一な硅化物層は前記第２の方法即ちア
ニールのみによって得られた硅化物層と大差がない。ま
た、１０００℃でのアニールは電気炉中で行われており
、シリコン中へ注入されたリンイオンは十分深く拡散し
ているものと考えられ、浅い接合の形成は実現されてい
ない。以上の如く、第１から第３の従来方法はいずれも
、０．１μｍ程度以下の浅い接合深さを持ち、かつこの
接合の表面が耐熱性のある低抵抗かつ均一な高融点金属
硅化物層で被われた構造を形成するには適さないことは
明白である。A third method is to form a silicide by performing ion implantation under conditions that mix the high-melting point metal/silicon interface, followed by annealing, instead of the second annealing method described above. Varnish double m-chi 27 (
S aWa Chiang et al.
of Applied Physics), No. 52
Volume, No. 6, pp. 4027-4032 (June 1981)
reported on a technology for forming molybdenum silicide using ion implantation of phosphorus into a molybdenum/silicon structure, and found that the reproducibility of the silicide reaction was improved and that the silicide formed after annealing at up to 850°C. It has been reported that the uniformity of the results is maintained. However, when this document is examined in detail, the uniformity of the silicide is significantly deteriorated when annealing is performed at 850° C. or higher, for example, at 1000° C. Such a non-uniform silicide layer is not significantly different from the silicide layer obtained by the second method, ie, by annealing alone. Furthermore, the annealing at 1000° C. is performed in an electric furnace, and it is thought that the phosphorus ions implanted into the silicon are sufficiently deeply diffused, so that the formation of a shallow junction has not been realized. As described above, all of the first to third conventional methods have a shallow junction depth of about 0.1 μm or less, and the surface of this junction is made of a heat-resistant, low-resistance, uniform high-melting point metal silicide layer. It is obvious that it is not suitable for forming a structure covered with.
本発明の目的は、シリコン基板の一主面に形成されたシ
リコン露出シリコン基板域に自己整合的に均一かつ平滑
な高融点金属の硅化物層を形成し、かつ該硅化物層下に
その接合深さが０．１μｍ以下以下上十分に浅い接合を
形成しつる製造方法を提供することである。An object of the present invention is to form a uniform and smooth silicide layer of a refractory metal in a self-aligned manner on an exposed silicon substrate area formed on one principal surface of a silicon substrate, and to bond the silicide layer under the silicide layer. It is an object of the present invention to provide a method for manufacturing a vine by forming a sufficiently shallow junction having a depth of 0.1 μm or less.
本発明によれば、少なくとも表面に単結晶シリコン層を
備えた基板の前記単結晶シリコン層上に絶縁膜を形成す
る工程と、該絶縁膜に開口部を設けた後前記基板上に高
融点金属層を堆積する工程と、■族又はＶ族のドーパン
トイオンを注入するか、もしくは該ドーパントイオンと
シリコン結晶中においてｐ型あるいはｎ型を示さない非
ドーパントイオンとを重ねて注入することによって前記
開口部で接する前記高融点金属層と前記単結晶シリコン
層の界面を混合する工程と、レーザービームまたは電子
ビームを照射することにより前記開口部に自己整合的に
高融点金属シリサイド層を形成する工程と、未反応で残
留する高融点金属膜をエツチングする工程と、を含むこ
とを特徴とする半導体装置の製造方法が得られる。According to the present invention, the steps of forming an insulating film on the single crystal silicon layer of a substrate having a single crystal silicon layer on at least the surface thereof, and forming an opening with a high melting point metal on the substrate after providing an opening in the insulating film. The openings are formed by depositing a layer and implanting group I or V dopant ions, or by superimposing the dopant ions and non-dopant ions not exhibiting p-type or n-type in the silicon crystal. a step of mixing an interface between the high melting point metal layer and the single crystal silicon layer that are in contact with each other at a portion thereof; and a step of forming a high melting point metal silicide layer in a self-aligned manner in the opening by irradiating a laser beam or an electron beam. There is obtained a method for manufacturing a semiconductor device, which is characterized in that it includes the steps of: etching a refractory metal film that remains unreacted.
本発明による製造方法では、シリコン基板上に設けられ
た所定の開口部に自己整合的に均一かつ平滑な高融点金
属シリサイド層を形成しつるのと同時に該シリザ−ｒ
ト層下部に浅いドープ層が形成される。本発明で得られ
た高融点金属シリサイド層はイ万ン注入による高融点金
属とシリコンとの界面の混合効果によっており、従来方
法によって形成した高融点金属シリサイド層に比較して
著しく優れた平滑性、均質性、熱的安定性及び合金化反
応に対する障壁性を有する。これらの特徴はＭＯ３ＬＣ
やバイポーラＩＣで代表されるシリコン半導体装置の機
箱な配線を構成する浅い不純物層を低抵抗化する目的で
該不純物層の表面を被う高融点金属シリサイドとして適
している。すなわち、高融点金属シリサイド形成後９０
０’Ｃ程度のアニールを行°うことができかつ高信頓性
のあるアルミニウム系オーミックコンタクトを形成し得
た。更に、本発明の製造方法では、イシ】−ン注入によ
ってドープした不純物をほとんど拡散せしめることなく
注入層の活性化を行えるために、活大層の活性化を行っ
た後にも接合深さ０，１μｍ程度の浅い不純物ドープ層
を形成しえた。以下、本発明の製造方法の実施例を図を
用いて説明する。In the manufacturing method according to the present invention, a uniform and smooth refractory metal silicide layer is formed in a self-aligned manner in a predetermined opening provided on a silicon substrate, and at the same time, the silicide layer is
A shallow doped layer is formed below the doped layer. The high melting point metal silicide layer obtained by the present invention is due to the mixing effect of the interface between the high melting point metal and silicon by ion implantation, and has significantly superior smoothness compared to the high melting point metal silicide layer formed by conventional methods. , homogeneity, thermal stability and barrier properties against alloying reactions. These characteristics are MO3LC
It is suitable as a high-melting point metal silicide to cover the surface of a shallow impurity layer constituting the circuit wiring of silicon semiconductor devices such as bipolar ICs and bipolar ICs for the purpose of lowering the resistance of the impurity layer. That is, after forming the high melting point metal silicide,
It was possible to perform annealing at about 0'C and form a highly reliable aluminum-based ohmic contact. Furthermore, in the manufacturing method of the present invention, since the implanted layer can be activated with almost no diffusion of impurities doped by ion implantation, the junction depth remains 0.1 μm even after activation of the active layer. A shallow impurity doped layer could be formed. Examples of the manufacturing method of the present invention will be described below with reference to the drawings.
第１図（ａ） 、 （ｂ） 、 （Ｃ）は本発明の詳細
な説明するための主要工程における概略断面図を示した
ものである。FIGS. 1(a), 1(b), and 1(C) show schematic cross-sectional views of main steps for detailed explanation of the present invention.
先ず、ｎ型シリコン基板を用意し、熱酸化法により厚さ
３０００ Ａの８ ｉｏ、膜を形成する。次に、周知の
ホトエツチング法により、所定の位置に開口を設けた後
、全面に膜厚４００ Ａ（７） Ｔｉ膜を堆積し、第１
図（ａ）の構造を得た。次に上部よりＳｉイオンを加速
電圧１８０ ｋｅＶ、ドーズ量５刈０１５ｃ１ｒＬ−２
だけ注入した後、ボロンイオンを２０ｋｅ■で５Ｘ１０
１′の−２だけ注入する。このとき、開口部のみにＴ１
とシリコンとの混合層が形成され、かつ該混合層下にボ
ロンがドープされたｐ型不純物層が形成された第１図（
ｂ）の構造が得られる。次に、走査型電子ビームアニー
ル装置を用いて、電力密度９Ｑ ＫＷ／ｃＴＬ−走査速
度１．９ｃｍ／ｓｅｃ の条件でアニールを行い、Ｔｉ
とシリコンとの混合層においてシリサイド反応を生じせ
しめる。次に、ＳｉＯ２膜上の未反応なＴｉを選択的に
エツチングすることにより、第１図（Ｃ）に示した如く
開口部のみに均一なＴｉシリサイド膜が形成された構造
が得られた。このように自己整合的に形成できる理由と
しては、電子ビームアニールにおいては加熱時間が極め
て短いので開口部以外の部分ではシリサイド形成反応が
生じないためと考えられる。本実施例において、Ｔｉシ
リサイド膜表面から接合までの深さ匂、１μｍに対して
シート抵抗５Ω／口の値が得られた。従来、ｐ型の不純
物層はボロンイオンをシリコン基板へ直接注入する方法
によって形成されているが、接合深さＸ１〜０．１μｍ
程度に形成しようとすると、そのシート抵抗は数百Ω／
口程度と著しく増大し、もはや、半導体集積回路の配線
等としての使用には供しえない。また、上記実施例では
、高融点金属としてＴｉを用い、イオン注入としてシリ
コンとボロンとの２重注入を実施した場合を示したが、
ＭＣ，、Ｗ’、 Ｔ３等の高融点金属と、Ａｓ等の■族
のドーパントイオン又はシリコンやアルゴン等の非ドー
パントイオンと■族やＩ族のドーパントイオンとの組合
せを用いた場合にも卓効があった。さらに、本実施例で
は走査型電子ビームアニール装置を用０てアニールを行
った場合を示したが、侃レーザー等のアニール装置を用
いても用いても効果のある事は明らかである。First, an n-type silicon substrate is prepared, and an 8 IO film with a thickness of 3000 A is formed by thermal oxidation. Next, after forming an opening at a predetermined position using a well-known photoetching method, a Ti film with a thickness of 400 A(7) is deposited on the entire surface, and the first
The structure shown in Figure (a) was obtained. Next, Si ions were accelerated from the top at a voltage of 180 keV and a dose of 5015c1rL-2.
After implanting 5x10 boron ions at 20ke■
Inject only -2 of 1'. At this time, T1 is applied only to the opening.
FIG.
The structure b) is obtained. Next, using a scanning electron beam annealing device, annealing was performed under the conditions of a power density of 9Q KW/cTL and a scanning speed of 1.9 cm/sec.
This causes a silicide reaction in the mixed layer of silicon and silicon. Next, by selectively etching the unreacted Ti on the SiO2 film, a structure was obtained in which a uniform Ti silicide film was formed only in the openings, as shown in FIG. 1(C). The reason why it can be formed in such a self-aligned manner is thought to be that the heating time in electron beam annealing is extremely short, so that no silicide formation reaction occurs in areas other than the openings. In this example, a sheet resistance value of 5 Ω/hole was obtained for a depth of 1 μm from the surface of the Ti silicide film to the junction. Conventionally, the p-type impurity layer is formed by directly implanting boron ions into the silicon substrate, but the junction depth is from X1 to 0.1 μm.
If an attempt is made to form a sheet with a resistance of several hundred Ω/
It has increased significantly to the extent that it can no longer be used as wiring for semiconductor integrated circuits, etc. Further, in the above embodiment, a case was shown in which Ti was used as the high melting point metal and double implantation of silicon and boron was performed as ion implantation.
It is also possible to use a combination of a high melting point metal such as MC, W', T3, etc., and a group II dopant ion such as As, or a non-dopant ion such as silicon or argon, and a group II or group I dopant ion. It worked. Furthermore, although the present embodiment shows the case where the annealing was performed using a scanning electron beam annealing device, it is clear that annealing devices such as a laser beam or the like can also be effective.
また、前記実施例においてはシリコン基板表面にシリサ
イド膜を形成する場合について述べたが、絶縁体上に辷
チョウ膜が形成されている場合にも本発明が適用できる
ことは明らかである。Further, in the above embodiments, a case was described in which a silicide film was formed on the surface of a silicon substrate, but it is clear that the present invention can also be applied to a case where a silicide film is formed on an insulator.
第１図は本発明の製造方法を説明するため主要工程の概
略断面図である。
１１はｎ型シリコン基板、１２は８ｉ０２膜、１３はＴ
ｉ膜、１４はＴｉとシリコンとの混合層、１５はボロン
がドープされたｐ型不純物層、１６はＴｉシリサイド層
をそれぞれ示す。
代理人弁理士内 原 晋
才 １
ノ
「コ−，−７寸
／／３
７FIG. 1 is a schematic sectional view of the main steps for explaining the manufacturing method of the present invention. 11 is an n-type silicon substrate, 12 is an 8i02 film, and 13 is T.
14 is a mixed layer of Ti and silicon, 15 is a p-type impurity layer doped with boron, and 16 is a Ti silicide layer. Representative patent attorney Shinsai Hara 1 ノ ``ko, -7 sun // 3 7
Claims (1)
単結晶シリコン層上に絶縁膜を形成する工程と、該絶縁
膜に開口部を設けた後前記基板上に高融点金属層を堆積
する工程と、■族又は■族のドーパントイオンを注入す
るか、もしくは該ドーパントイオンとシリコン結晶中に
おいてｐ型あるいはｎ型を示さない非ドーパントイオン
とを重ねて注入することによって前記開口部で接する前
記高融点金属層と前記単結晶シリコン層の界面を混合す
る工程と、レーザービームまたは電子ビームを照射する
ことにより前記開口部に自己整合的に高融点金属シリサ
イド層を形成する工程と、未反応で残留する高融点金属
膜をエツチングする工程と、を含むことを特徴とする半
導体装置の製造方法。forming an insulating film on the single-crystal silicon layer of a substrate having a single-crystal silicon layer on at least the surface; and depositing a high-melting point metal layer on the substrate after forming an opening in the insulating film. , by implanting group Ⅰ or group Ⅰ dopant ions, or by superimposing the dopant ions and non-dopant ions that do not exhibit p-type or n-type in the silicon crystal, the high melting point is in contact with the opening. A step of mixing the interface between the metal layer and the single crystal silicon layer, a step of forming a high melting point metal silicide layer in the opening in a self-aligned manner by irradiating with a laser beam or an electron beam, and a step of forming a high melting point metal silicide layer in the opening portion by irradiating the metal layer with the single crystal silicon layer; A method for manufacturing a semiconductor device, comprising the step of etching a high melting point metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22058882A JPS59110115A (en) | 1982-12-16 | 1982-12-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22058882A JPS59110115A (en) | 1982-12-16 | 1982-12-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59110115A true JPS59110115A (en) | 1984-06-26 |
Family
ID=16753323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22058882A Pending JPS59110115A (en) | 1982-12-16 | 1982-12-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59110115A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02170528A (en) * | 1988-12-23 | 1990-07-02 | Toshiba Corp | Manufacture of semiconductor device |
| US6649976B2 (en) | 1994-01-28 | 2003-11-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having metal silicide film and manufacturing method thereof |
| US6790749B2 (en) | 1992-10-09 | 2004-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US6939749B2 (en) | 1993-03-12 | 2005-09-06 | Semiconductor Energy Laboratory Co., Ltd | Method of manufacturing a semiconductor device that includes heating the gate insulating film |
-
1982
- 1982-12-16 JP JP22058882A patent/JPS59110115A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02170528A (en) * | 1988-12-23 | 1990-07-02 | Toshiba Corp | Manufacture of semiconductor device |
| US5654241A (en) * | 1988-12-23 | 1997-08-05 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device having reduced resistance of diffusion layers and gate electrodes |
| US6790749B2 (en) | 1992-10-09 | 2004-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US7109108B2 (en) | 1992-10-09 | 2006-09-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device having metal silicide |
| US7602020B2 (en) | 1992-10-09 | 2009-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US7723788B2 (en) | 1992-10-09 | 2010-05-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US8017506B2 (en) | 1992-10-09 | 2011-09-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6939749B2 (en) | 1993-03-12 | 2005-09-06 | Semiconductor Energy Laboratory Co., Ltd | Method of manufacturing a semiconductor device that includes heating the gate insulating film |
| US6649976B2 (en) | 1994-01-28 | 2003-11-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having metal silicide film and manufacturing method thereof |
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