JPS59108322A - Semiconductor wafer - Google Patents
Semiconductor waferInfo
- Publication number
- JPS59108322A JPS59108322A JP21901482A JP21901482A JPS59108322A JP S59108322 A JPS59108322 A JP S59108322A JP 21901482 A JP21901482 A JP 21901482A JP 21901482 A JP21901482 A JP 21901482A JP S59108322 A JPS59108322 A JP S59108322A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- holes
- melted
- spottily
- energy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 235000012431 wafers Nutrition 0.000 abstract description 25
- 230000007547 defect Effects 0.000 abstract description 14
- 239000013078 crystal Substances 0.000 abstract description 6
- 238000005247 gettering Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052786 argon Inorganic materials 0.000 abstract description 2
- 239000011159 matrix material Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
（ａｌ 発明の技術分野
本発明は半導体素子を形成する半導体ウェハーに関し、
特に結晶欠陥を少なくして電気的特性を向上するための
処置がなされた半導体ウェハーに関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor wafer on which semiconductor elements are formed;
In particular, the present invention relates to semiconductor wafers treated to reduce crystal defects and improve electrical characteristics.
山）従来技術と問題点
近年、半導体集積回路（ＩＣ）などの半導体装置の高集
積化、高密度化に伴なって、半導体ウェハーの結晶欠陥
が益々問題視され、従来より半導体ウェハー表面の結晶
欠陥をできる限り少なくする処置がとられている。(Mountain) Conventional technology and problems In recent years, with the increasing integration and density of semiconductor devices such as semiconductor integrated circuits (ICs), crystal defects in semiconductor wafers have become increasingly problematic. Measures are taken to minimize defects.
その最も汎用されている方法は半導体ウェハーの裏面に
高濃度不純物層（燐拡散層）を形成したり、または窒化
シリコン膜を被着したりして、欠陥層を裏面に形成し、
故意に半導体ウェハー表面の欠陥を裏面に吸収する所謂
欠陥ゲッタリング方法である。The most commonly used method is to form a high concentration impurity layer (phosphorus diffusion layer) on the back side of a semiconductor wafer or to deposit a silicon nitride film to form a defect layer on the back side.
This is a so-called defect gettering method in which defects on the front surface of a semiconductor wafer are intentionally absorbed onto the back surface.
このようなゲッタリング方法において、最近はレーザ光
などのエネルギー線を半導体ウェハーの裏面に照射し溶
融させて、熱歪欠陥層を裏面に形成する方法が用いられ
ており、この方法は上記の不純物拡散法や被膜形成法に
比べて処理が簡単で、同様のゲッタリング作用によ・つ
て表面の微少欠陥を裏面に吸収することができる方法で
ある。In such gettering methods, a method has recently been used in which the back surface of a semiconductor wafer is irradiated with energy rays such as laser light and melted to form a thermally strained defect layer on the back surface. This method is easier to process than the diffusion method or film formation method, and allows minute defects on the surface to be absorbed into the back surface using the same gettering effect.
ところが、従来のこのようなエネルギー照射法はエネル
ギービームを連続してスキャンニング（走査）する方法
で、照射部分は溶融して例えば深さ２μｍ程度の溝形の
ビ部を生じる。第１図はその一実施例の半導体ウェハー
裏面図を示しており、レーザ光を線状に走査した例で、
線状溝１の部分がビ状になっている。その他にも例えば
渦状に走査して渦状の熔融溝を形成する方法がある。However, in the conventional energy irradiation method, the energy beam is continuously scanned, and the irradiated portion is melted to form a groove-shaped groove having a depth of, for example, about 2 μm. FIG. 1 shows a back view of a semiconductor wafer in one embodiment, and is an example in which laser light is scanned linearly.
The portion of the linear groove 1 is shaped like a vi. There is also a method of forming a spiral melt groove by scanning in a spiral, for example.
しかしながら、裏面にかような溝形の凹部を形成すると
、半導体ウェハーに素子を形成するためのウェハープロ
セスにおいては、半導体ウェハーを真空チャックに吸着
する場合に真空漏れを起こし、ハンドリング作業が大変
難しくなる。最近のウェハープロセスは自動化処理であ
り・真空チャック吸着が困難になると半導体ウェハーを
破壊しやすくて歩留や品質に非常に悪影響をあたえる。However, if such a groove-shaped recess is formed on the back surface, vacuum leakage will occur when the semiconductor wafer is sucked into a vacuum chuck during the wafer process for forming elements on the semiconductor wafer, making handling work extremely difficult. . Recent wafer processes are automated processes, and if vacuum chuck suction becomes difficult, semiconductor wafers are likely to be destroyed, which has a very negative impact on yield and quality.
（Ｃ） 発明の目的
本発明はこのような問題点を除去したゲッタリング作用
をもった半導体ウェハーを提案するものである。(C) Object of the Invention The present invention proposes a semiconductor wafer having a gettering function that eliminates the above-mentioned problems.
＋ｄｌ 発明の構成
その目的は、裏面にエネルギー照射によって複数個のス
ポット状熔融孔が設けられた半導体ウェハーによって達
成される。+dl Structure of the Invention The object is achieved by a semiconductor wafer whose back surface is provided with a plurality of spot-shaped melt holes by energy irradiation.
（ｅｌ 発明の実施例 以下３図面を参照して実施例によって詳細に説明する。(el Embodiments of the invention Examples will be described in detail below with reference to three drawings.
第２図は本発明による一実施例の半導体ウェハーの裏面
（背面）図で、２が熔融孔である。FIG. 2 is a backside (back) view of a semiconductor wafer according to an embodiment of the present invention, and numeral 2 indicates a melting hole.
例えば、孔の直径を４μｍ、深さを２μｍとしたスポッ
ト孔を５００μｍの間隔でマトリックス状に形成する。For example, spot holes having a diameter of 4 μm and a depth of 2 μm are formed in a matrix at intervals of 500 μm.
そうすると、このような熔融孔は半径８００μｍの領域
の欠陥をゲッタリングして、半導体ウェハー表面の結晶
欠陥を吸収することができる。Then, such melt holes can getter defects in an area with a radius of 800 μm and absorb crystal defects on the surface of the semiconductor wafer.
照射エネルギーとしてはアルゴン（Ａｒ）レーザを用い
、出力を１０〜２０ワツトにする。また、照射エネルギ
ーは出来るだけ大きなエネルギーを、出来るだけ短時間
与える処理法がよくて、電子ビームとレーザ光との複合
エネルギーを使用すれば一層効果が大きい。且つ、半導
体ウェハー裏面にスポット孔を設けたマスクを被覆して
、その上から連続走査すると所定位置にスポット孔を形
成することが出来る。あるいは、ビームを一定速度で走
査して間欠的に照射する方法を用いてもよい。An argon (Ar) laser is used as the irradiation energy, with an output of 10 to 20 watts. Furthermore, it is best to use a processing method that applies as much energy as possible for as short a time as possible, and the effect is even greater if combined energy of an electron beam and a laser beam is used. In addition, by covering the back surface of the semiconductor wafer with a mask having spot holes and performing continuous scanning from above, spot holes can be formed at predetermined positions. Alternatively, a method may be used in which the beam is scanned at a constant speed and irradiated intermittently.
このようにすれば、連続した溝状の凹部ではなくなるか
ら真空チャックで吸着しても半導体ウェハーが脱落する
ことがなくなり、しがもゲッタリング効果は従来と変わ
りがない。If this is done, the semiconductor wafer will not fall off even if it is picked up by a vacuum chuck since it will no longer be a continuous groove-like recess, and the gettering effect will remain the same as in the past.
（ｆｌ 発明の効果
以上の説明から判るように、本発明は結晶欠陥が少なく
てハンドリングの容易な半導体ウェハーであり、半導体
装置の歩留１品質の向上に極めて貢献するものである。(fl) Effects of the Invention As can be seen from the above explanation, the present invention provides a semiconductor wafer that has few crystal defects and is easy to handle, and greatly contributes to improving the yield and quality of semiconductor devices.
第１図は従来の半導体ウェハー裏面図、第２図は本発明
にかかる半導体ウェハー裏面図である。
第１図
第２図FIG. 1 is a back view of a conventional semiconductor wafer, and FIG. 2 is a back view of a semiconductor wafer according to the present invention. Figure 1 Figure 2
Claims (1)
融孔が設けられたことを特徴とする半導体ウェハー。A semiconductor wafer characterized in that a plurality of spot-shaped molten holes are provided on a whole surface by energy irradiation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21901482A JPS59108322A (en) | 1982-12-13 | 1982-12-13 | Semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21901482A JPS59108322A (en) | 1982-12-13 | 1982-12-13 | Semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59108322A true JPS59108322A (en) | 1984-06-22 |
Family
ID=16728900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21901482A Pending JPS59108322A (en) | 1982-12-13 | 1982-12-13 | Semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59108322A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6427231A (en) * | 1986-06-30 | 1989-01-30 | Nec Corp | Manufacture of semiconductor device |
| US20200203177A1 (en) * | 2018-12-20 | 2020-06-25 | Rahul Agarwal | Semiconductor chip gettering |
-
1982
- 1982-12-13 JP JP21901482A patent/JPS59108322A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6427231A (en) * | 1986-06-30 | 1989-01-30 | Nec Corp | Manufacture of semiconductor device |
| US20200203177A1 (en) * | 2018-12-20 | 2020-06-25 | Rahul Agarwal | Semiconductor chip gettering |
| US10825692B2 (en) * | 2018-12-20 | 2020-11-03 | Advanced Micro Devices, Inc. | Semiconductor chip gettering |
| US11393697B2 (en) | 2018-12-20 | 2022-07-19 | Advanced Micro Devices, Inc | Semiconductor chip gettering |
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