JPS59106176A - Printed board - Google Patents
Printed boardInfo
- Publication number
- JPS59106176A JPS59106176A JP21753882A JP21753882A JPS59106176A JP S59106176 A JPS59106176 A JP S59106176A JP 21753882 A JP21753882 A JP 21753882A JP 21753882 A JP21753882 A JP 21753882A JP S59106176 A JPS59106176 A JP S59106176A
- Authority
- JP
- Japan
- Prior art keywords
- foil
- printed circuit
- circuit board
- parts
- land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
この発明は一面に電子部品を存置させ、他面においては
導電体箔を利用して回路相互を接続するようにしである
プリント基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a printed circuit board in which electronic components are placed on one side and circuits are connected to each other using conductive foil on the other side.
従来のプリント基板にあっては、次の様な製造手順でプ
リント基板が製造されている。即ち銅張積層板の一面に
シルク印刷を行ない、一方他面における銅張面（導電体
箔の面）においては予め設計基準によって形成されたラ
ンド部が描かれている基本図に従って光学的、化学的に
銅張面に保護膜を被せ付け、次に上記銅張部分における
一部の銅部材を溶かすエツチング作業に入る。次に必要
に応じては、半田が耐着しては困る部分には印刷手段に
よって半田の耐着防止用の被Ｍ（ソルダーレジスト）を
施す。次にプリント基板の必要箇所にパンチングを施し
、更に必要な電子部品をそのパンチされた対応孔部に挿
入する。次にランド部において上記電子部品との接合を
図る。これはディッピングと称されておシ半田槽の中に
上記導電体箔を漬けて銅箔を半田溶融温度に１で熱し、
ランド部に突出している部品のリード線を半田付けする
ものである。この過程において銅箔が伸張し、次に次工
程へ移す過程において収縮し、そのときに基板が反るこ
とが多い。従って、第７図の如く基板が反った場合は次
のリード・カット、即ちリード線な切断する作業でその
切断作業能率が落ちる欠点がある。In the case of conventional printed circuit boards, printed circuit boards are manufactured using the following manufacturing procedure. That is, silk printing is performed on one side of the copper-clad laminate, while optical and chemical printing is performed on the other side of the copper-clad laminate (conductor foil side) according to a basic diagram in which land portions formed in advance according to design standards are drawn. First, a protective film is applied to the copper-clad surface, and then an etching process is started to melt some of the copper members in the copper-clad area. Next, if necessary, a coating M (solder resist) for preventing solder adhesion is applied by printing means to areas where it is difficult for the solder to adhere. Next, the printed circuit board is punched at the required locations, and the required electronic components are inserted into the punched corresponding holes. Next, the land portion is bonded to the electronic component. This is called dipping, and the conductor foil is immersed in a solder bath and the copper foil is heated to the solder melting temperature at 1.
This is to solder the lead wires of the components protruding from the land portions. During this process, the copper foil expands and then contracts during the next process, often causing the board to warp. Therefore, if the board is warped as shown in FIG. 7, there is a drawback that the efficiency of the next lead cutting operation, that is, cutting the lead wires, is reduced.
この発明は上記問題点を解決しようとするものでディフ
ビング作業終了後においても第３図に示す如く基板が平
担なままに維持できるようにしであるプリント基板を提
供しようとするものである。The present invention attempts to solve the above-mentioned problems and provides a printed circuit board that allows the board to remain flat as shown in FIG. 3 even after the diffusing operation is completed.
以下本願の実施例を示す図面について説明する。The drawings showing the embodiments of the present application will be described below.
１ｔま周知のプリント基板を示し、この表面２は絶縁体
の基板で、その反対面３は導電体箔であり、夫々周知の
如く形成されている。４は回路構成用のランド部を示し
、５はその周囲に設けられた絶縁体露出部を示す。６は
アース用の導電体箔残存部を示す。７は通常知られてい
る任意の電子部品を示し、８はそのリード線を示す。こ
のリード線は導電体箔の面にあるランド部４に位置させ
、これとは半田によって電気的及び機械的に接続されて
いる。９，１０は給電線接続用の金具を示す（この金具
は３θ０Ω又は７ｊΩ等任意の給電線を接続する為の金
具であればよい）。１１け切欠部を示し、電子部品のリ
ード線８を差し通す孔と共にパンチング工程において切
欠されたものである。以上説明した符号１〜１１で示さ
れる構造は周知の構造を示し、その形状構成等は周知の
任意のものと互換想起して理解してもよい。1t shows a well-known printed circuit board, the surface 2 of which is an insulating substrate, and the opposite surface 3 of which is a conductive foil, each formed in a well-known manner. Reference numeral 4 indicates a land portion for circuit configuration, and reference numeral 5 indicates an exposed insulator portion provided around the land portion. 6 shows the remaining part of the conductor foil for grounding. 7 indicates any commonly known electronic component, and 8 indicates its lead wire. This lead wire is located on the land portion 4 on the surface of the conductive foil, and is electrically and mechanically connected to the land portion 4 by solder. Reference numerals 9 and 10 indicate metal fittings for connecting the power supply line (these metal fittings may be metal fittings for connecting any power supply line such as 3θ0Ω or 7jΩ). 11 notches are shown, which were cut out during the punching process along with holes through which lead wires 8 of electronic components were inserted. The structures indicated by reference numerals 1 to 11 described above are well-known structures, and their shapes and configurations may be understood by being interchangeable with any well-known structure.
次に枝はアース部６に散設した絶縁体露出部を示し、ラ
ンド部以外のアース用鋼箔残存部に適宜散設したもので
ある。又その大きさは第２図に示すように丸形形状の小
さなもの１２′、或いは大きな丸形形状し′のもの、な
いしは第６図に示すような角型のもの１２″′等任意の
大きさ形状であればよい。次にその配設状態は銅箔の残
存部（銅箔面においてランド部を除いた残部）が大きい
面積の１１二
場合は網目状に規則正しく配設をして回路基板の反りが
防止できるようにすると共にアース回路として残存部の
役割も十分果たし高周波特性を劣化させないように配置
すればよい。さらにその配設状況はランド部が多数あっ
てそれらの間に設ける場合はやや不規則になるが、でき
るだけ上記高周波特性の劣化をさせないような位置及び
大きさにして配設すればよい。Next, the branches represent the exposed portions of the insulator scattered in the ground portion 6, and are appropriately scattered in the remaining portion of the grounding steel foil other than the land portion. The size can be any size, such as a small round shape 12' as shown in Figure 2, a large round shape 12'', or a square shape 12'' as shown in Figure 6. If the remaining part of the copper foil (the remaining part of the copper foil surface excluding the land part) has a large area, it should be arranged regularly in a mesh pattern to form a circuit board. It should be arranged in such a way that it can prevent the warping of the land, and also play the role of the remaining part as a grounding circuit without deteriorating the high frequency characteristics.Furthermore, the arrangement should be such that there are many land parts and if it is installed between them. Although they are somewhat irregular, they should be arranged in positions and sizes that do not degrade the high frequency characteristics as much as possible.
上記したように（第２図乃至第６図から明らかなように
）導電体箔面におけるランド部を除いた残存部に多数の
小さな絶縁体露出部を散設することによシ前記したディ
ッピング工程においての収縮による基板１の反りは防止
できる。しかもそれらの絶縁体露出部】２は小さなもの
を多数数投しだ状態であるからアース導体として上記導
電体箔面３をみた場合高周波的なアースの役割を十分に
果たすことができ、優れた高周波特性を残すことができ
る。また上記の第２図乃至第６図に示すように露出部し
を散設したものは第３図の如くディッピング終了後にお
いても基板がフラットな為、リード・カット工程が基板
面に添う直線の切断線】３で可能となり、例えば機械化
により極めて速い切断作業ができる。勿論手作業で切断
する場合も第３図と第７図の比較から明らかなように、
第３図のようにフラットな基板のリード・カット作業は
容易となる。As mentioned above (as is clear from FIGS. 2 to 6), the dipping process is carried out by scattering a large number of small exposed insulator parts in the remaining part of the conductor foil surface excluding the land part. Warping of the substrate 1 due to shrinkage can be prevented. Furthermore, since the insulator exposed portions 2 are in a state where many small objects are thrown out, when the above-mentioned conductor foil surface 3 is viewed as a ground conductor, it can sufficiently fulfill the role of high frequency ground, making it an excellent ground conductor. High frequency characteristics can be preserved. In addition, in the case where the exposed parts are scattered as shown in Fig. 2 to Fig. 6 above, the board is flat even after dipping as shown in Fig. 3, so the lead cutting process is performed in a straight line along the board surface. [Cutting line] 3, and extremely fast cutting work can be achieved by mechanization, for example. Of course, even when cutting by hand, as is clear from the comparison between Figures 3 and 7,
As shown in Figure 3, the lead cutting work on a flat board becomes easy.
この発明にあっては回路基板における導電体箔（アース
面）に多数の小さな絶縁体露出部しを散設してその散設
部分の周囲の銅箔の伸び縮みの力を分割して減らしてい
るのでプリント基板１０部分的な反りを防止することが
でき、これによって第７′図に示すような従来の曲りの
欠点を解決するに役立つ効果がある。In this invention, a large number of small insulator exposed parts are scattered on the conductive foil (ground plane) of the circuit board, and the expansion and contraction force of the copper foil around the scattered parts is divided and reduced. As a result, partial warping of the printed circuit board 10 can be prevented, and this has the effect of helping to overcome the drawbacks of conventional warping as shown in FIG. 7'.
図面は本願の実施例を示すもので、第１図は平面図、第
２図は底面図、第３図は正面図、第を図は左側面図、第
５図はＶ−Ｖ線端面図、第４図は異なる絶縁体露出部の
形状配置を示す底面図、第７図は従来例を示す正面図。
２・・・絶縁体の基板、３・・・導電体箔、７・・・電
子部品、４・・・ランド部、６・・・導電体箔残存部、
和・・・小さな絶縁体露出部。The drawings show an embodiment of the present application, and Fig. 1 is a plan view, Fig. 2 is a bottom view, Fig. 3 is a front view, Fig. 5 is a left side view, and Fig. 5 is an end view taken along the line V-V. , FIG. 4 is a bottom view showing different shapes and arrangements of exposed insulator parts, and FIG. 7 is a front view showing a conventional example. 2... Insulator substrate, 3... Conductor foil, 7... Electronic component, 4... Land portion, 6... Conductor foil remaining portion,
Japanese: Small exposed insulator.
Claims (1)
ンド部を配設する一方、上記ランド部を除く他の導電体
箔の部分においては多数の小さな絶縁体露出部を散設し
であることを特徴とするプリント基板。While a plurality of circuit lands are arranged on the conductor foil of the printed circuit board, many small exposed insulator parts are scattered in other parts of the conductor foil other than the above-mentioned land parts. Characteristic printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21753882A JPS59106176A (en) | 1982-12-10 | 1982-12-10 | Printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21753882A JPS59106176A (en) | 1982-12-10 | 1982-12-10 | Printed board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59106176A true JPS59106176A (en) | 1984-06-19 |
Family
ID=16705818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21753882A Pending JPS59106176A (en) | 1982-12-10 | 1982-12-10 | Printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59106176A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4755716A (en) * | 1986-07-21 | 1988-07-05 | Mitsui Toatsu Chemicals, Inc. | Filter for CRT screen |
| US4839736A (en) * | 1987-07-06 | 1989-06-13 | Mitsui Toatsu Chemicals, Inc. | Filter for CRT screen |
| JP2013207228A (en) * | 2012-03-29 | 2013-10-07 | Denso Wave Inc | Circuit board for high power monitoring device of plant equipment |
-
1982
- 1982-12-10 JP JP21753882A patent/JPS59106176A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4755716A (en) * | 1986-07-21 | 1988-07-05 | Mitsui Toatsu Chemicals, Inc. | Filter for CRT screen |
| US4839736A (en) * | 1987-07-06 | 1989-06-13 | Mitsui Toatsu Chemicals, Inc. | Filter for CRT screen |
| JP2013207228A (en) * | 2012-03-29 | 2013-10-07 | Denso Wave Inc | Circuit board for high power monitoring device of plant equipment |
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