JPS5910240A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5910240A
JPS5910240A JP57119306A JP11930682A JPS5910240A JP S5910240 A JPS5910240 A JP S5910240A JP 57119306 A JP57119306 A JP 57119306A JP 11930682 A JP11930682 A JP 11930682A JP S5910240 A JPS5910240 A JP S5910240A
Authority
JP
Japan
Prior art keywords
bonding pads
electrodes
external lead
metal wiring
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57119306A
Other languages
Japanese (ja)
Other versions
JPS6322614B2 (en
Inventor
Takashi Miyamoto
隆 宮本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57119306A priority Critical patent/JPS5910240A/en
Priority to US06/511,935 priority patent/US4608592A/en
Publication of JPS5910240A publication Critical patent/JPS5910240A/en
Publication of JPS6322614B2 publication Critical patent/JPS6322614B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the number of external lead pins employed for a power source and grounding and to increase relatively the number of pins for input and output, by forming a circular metal wiring outside bonding pads on a ceramic substrate, and by connecting one of the bonding pads electrically to the circular metal wiring through a through hole or a side metallized member. CONSTITUTION:Bonding pads 4b and 4d connected to electrodes 10b and 10d for power supply by fine metal wires are connected to external lead pins 9b and 9d respectively, while bonding pads 4a and 4c connected to electrodes 10a and 10c are not connected to external lead pins. In order to supply these two electrodes with power supply, the bonding pads 4a-4d are connected to a circular metal wiring 11 by fine metal wires. By this constitution, the power supplied from the external lead pins 9b and 9d is passed through the circular metal wiring 11 via the bonding pads 4b and 4c to the bonding pads 4a and 4c, and is supplied from the electrodes 10a and 10c to the internal circuit of a semicondutor element.

Description

【発明の詳細な説明】 本発明は、セラミック・パッケージ型の半導体装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ceramic package type semiconductor device.

セラミック・パッケージ型半導体装置は、通常は第１図
に示すように、セラミック基板１に設けられたキャビテ
ィと称する凹部２の底面に、半導体素子３を固着し、そ
の周囲を取り囲むボンディング会パッド４と半導体素子
の電極（図示せず）とを金（Ａ　ｕ　）やアルミニウム
（ＡＩりを主成分とする直径２０〜３０μｍの金属紙１
Ｍ５で接続し２、更にセラミック基板の表面に固着され
たシール・リング６に金属キャップ７をシールして作ら
れる。ボンティング・パッド４は、内部配線８を経由し
て外部リードビン９に接続されておシ、これをプリント
基板の穴やソケットに挿入して実装される。As shown in FIG. 1, a ceramic package type semiconductor device usually has a semiconductor element 3 fixed to the bottom of a recess 2 called a cavity provided in a ceramic substrate 1, and a bonding pad 4 surrounding the semiconductor element 3. A metal paper 1 with a diameter of 20 to 30 μm mainly composed of gold (A u ) or aluminum (AI) is connected to the electrodes (not shown) of the semiconductor element.
It is made by connecting with M5 2 and sealing a metal cap 7 to a seal ring 6 fixed to the surface of the ceramic substrate. The bonding pad 4 is connected to an external lead bin 9 via an internal wiring 8, and is mounted by inserting it into a hole or socket of a printed circuit board.

近年の半導体装置、特に論理や記憶全機能とする集積回
路装置は、よシ高速に動作させる為に論理振幅を小さく
する傾向にある。しかし、この傾向は、ノイズ等による
誤動作の機会も多くなるこ影響は甚大となる。この電位
シフトは、半導体素子内部の金属配線が細く、薄くでき
ているので導通抵抗が大きくなるために生ずるものであ
る。この電位シフトラできるだけ防ぐために、半導体素
子内の電源や接地は、分散化させることが必要となって
きた。即ち、従来のように電源や接地をそれぞれ１つの
電極から取るのではなく、例えば矩形の半導体素子の４
辺からそれぞれ１つずつ取ることにより、半導体素子内
で電位シフトの緩和を計ることが必要となってきた。こ
の効果は集積度が向上し配線バタンか微細化される程、
また、半導体素子の寸法が大きくなる程、大きなものと
なり、それに従って電源や接地用の電極もよシ多く取る
必要が生じてくる。In recent years, semiconductor devices, especially integrated circuit devices that have all logic and memory functions, tend to have smaller logic amplitudes in order to operate at higher speeds. However, this trend has a significant impact as there are more opportunities for malfunctions due to noise and the like. This potential shift occurs because the metal wiring inside the semiconductor element is thin and has a large conduction resistance. In order to prevent this potential shift as much as possible, it has become necessary to decentralize the power supply and grounding within the semiconductor device. That is, instead of taking power and grounding from one electrode as in the past, for example, four electrodes of a rectangular semiconductor element
It has become necessary to measure potential shift relaxation within a semiconductor element by taking one from each side. This effect increases as the degree of integration improves and the wiring pattern becomes finer.
Furthermore, as the size of a semiconductor element increases, it becomes larger, and accordingly, it becomes necessary to provide more electrodes for power supply and grounding.

しかし、この電源や接地の分散化はその一方で、限られ
た外部リードビン数の中で電源や接地用の外部リードビ
ンの数が増大することになり、相対的に信号の入出力用
ビンは減少することになる。However, on the other hand, this decentralization of power supply and grounding means that the number of external lead bins for power supply and grounding increases within the limited number of external lead bins, and the number of bins for signal input/output decreases relatively. I will do it.

半導体素子の集積度を上げても、入出力ビン数が少なく
なったら高集積化の意味が失われてし筐９゜本発明は、
以上の障害を解消する為になされたもので、セラミック
基板上のボンディング・パッドの外側に、それを囲むよ
うに環状の金属配線を形成することを特徴とし、更には
、ボンディング・パッドのうちの少なくとも１つは、前
記環状の金属配線とスルーホールまたは側面メタライズ
により電気的に接続されていることを特徴とするもので
あり、その目的とするところは、以上の構造を有するこ
とによハ電源や接地に用いられる外部リードビンの数を
少なくし、相対的に入出力用のビン数を増大しようとす
るものである。Even if the degree of integration of semiconductor elements is increased, if the number of input/output bins decreases, the meaning of high degree of integration is lost.
This method was developed to eliminate the above-mentioned problems, and is characterized by forming a ring-shaped metal wiring on the outside of the bonding pad on the ceramic substrate so as to surround it. At least one is characterized in that it is electrically connected to the annular metal wiring by a through hole or side metallization, and its purpose is to provide a power supply by having the above structure. This aims to reduce the number of external lead bins used for grounding and grounding, and relatively increase the number of input/output bins.

以下に、本発明の実施例を図面を用いて詳細に説明する
。ＤＩＰ（Ｄｕａｌ　　Ｉｎ１ｉｎｅ　Ｐａｃｋａｇｅ
）型の半導体装置に本発明を適用した例を第２図（ａ）
。Embodiments of the present invention will be described in detail below with reference to the drawings. DIP (Dual In1ine Package)
) type semiconductor device to which the present invention is applied is shown in FIG. 2(a).
.

（ｂ）に示した。第２図（ａ）は平面図で、Ａ−Ａ’に
おける断面図を第２図（ｂ）に示した。セラミック基板
１に設けたキャビティ２の底面に固層された半導体素子
３には電＆１０が計４４ケ配列されている。Shown in (b). FIG. 2(a) is a plan view, and FIG. 2(b) is a cross-sectional view taken along line AA'. A total of 44 electrodes are arranged on a semiconductor element 3 fixedly layered on the bottom surface of a cavity 2 provided in a ceramic substrate 1.

このうち各辺のほぼ中央部に存在する電極１０ａ〜ｄが
分散化された電源である。従来の半導体装置では、２つ
以上の電極から１つのボンディング−パッドに細線を１
本ずつ接続することがない限り、電極が４４ケある場合
は、外部リードビンを４４本備えたセラミック基板に搭
載しなければならなかった（ＤＩＰ形のセラミック基板
では、ビン数が４４ビンというものは一般的ではなく、
本例の場合、通常は４８ビンのセラミック基板に搭載さ
れる）。本発明では、電源用電極１０ｂ、　１０ｄと金
属細線で接続されたボンディング・パッド４ｂ、４ｄが
第２図（ｂ）かられかるように、それぞれ外部リードビ
ン９ｂ、９ｄにつながっておシ、電極１０ａ＋１０ｃと
接続されたボンディング・パッド４ａ、４ｃは、外部リ
ードビンに接続されていない。Among these, electrodes 10a to 10d located approximately at the center of each side are a distributed power source. In conventional semiconductor devices, one thin wire is connected to one bonding pad from two or more electrodes.
Unless the electrodes are connected one by one, if there are 44 electrodes, they must be mounted on a ceramic board with 44 external lead bins (for a DIP type ceramic board, the number of external lead bins is 44). Not common,
In this example, it is normally mounted on a 48-bin ceramic substrate). In the present invention, bonding pads 4b and 4d connected to power supply electrodes 10b and 10d by thin metal wires are connected to external lead bins 9b and 9d, respectively, as shown in FIG. 2(b). The bonding pads 4a, 4c connected to the external lead bin are not connected to the external lead bin.

この２つの電極に電源を供給するために、ボンディング
・パッド４ａ〜ｄと、本発明である環状の金属配＃５！
１１との間を金属細線で接続しておく。これにより、外
部リードビン９ｂ、９ｄから供給された電源は、ボンテ
ィング・パッド４ｂ、４Ｃ全経由して環状の金躯配Ｗｊ
ｌｌを通ってボンディング・パッド４ａ＋４ｃに至り、
半導体素子の内部回路に電極１０ａ、１０ｃから供給さ
れることになる。この構造を有することによシ、本実施
例の場合、外部リード・ビンの数が４２ビンのセラミッ
ク基板を使用できる。この環状の金属配勝１１は、通常
のセラミック基板のメタライズ−プロセスと同じ方法で
形成できる。即ち、未焼成のセラミック響シートにタン
グステン（Ｗ）の粒子を分散させたインクでスクリーン
印刷し、セラミック・シートを焼成した後、ニッケル（
Ｎｉ）や金（Ａｕ）めっきをする。このめっきの導通を
とるには、例えば第３図のように環状金属配線１１にヌ
ル−ホール１２を設け、ここから１層下のボンディング
・パッドの配列しである面と同一の面に形成した内部配
？ｆＭ１３を通してセラミック基板の側面に出せはよい
Ｏボンディング・パッド４ａ、４ｃのめっきも、外部リ
ードビンにつながずに、直接セラミック基板の側面に内
部配ｌ１Ｉｉ！を通じて出せばよい。第２図の実施例で
は電極１０ａ、１０ｃへの電源供給は、１１Ｌ極とボン
ティング・パッド間及びボンディング・パッドと環状金
属層との間にそれぞれ金属＃ｌｌ１ｓを接続して行なわ
れるが、セラミック基板の設計の余裕度の関係から、ボ
ンディング・パッド４ａ、４ｂを設けることができない
場合は、第４図のように、電極１０ａから直接に環状金
属配線１１に金属細線５で接続してもよい。この場合は
、ボンディング・パッド４ａを介して２段の接続を行な
うよりも導通抵抗は小さくできる。また、更に導通抵抗
を小さくしまたい場合は、金属細線を２本以上接続して
もよい。In order to supply power to these two electrodes, bonding pads 4a-d and the annular metal trace #5! of the present invention are provided.
11 with a thin metal wire. As a result, the power supplied from the external lead bins 9b and 9d is routed through the bonding pads 4b and 4C to the annular metal wiring Wj.
ll to bonding pads 4a+4c,
The internal circuit of the semiconductor element is supplied from the electrodes 10a and 10c. By having this structure, in the case of this embodiment, a ceramic substrate having 42 external lead bins can be used. This annular metal guide 11 can be formed by the same method as the metallization process for ordinary ceramic substrates. That is, an unfired ceramic acoustic sheet is screen printed with ink in which tungsten (W) particles are dispersed, and after the ceramic sheet is fired, nickel (nickel (W)) is applied.
(Ni) or gold (Au) plating. To make this plating conductive, for example, as shown in Fig. 3, a null hole 12 is provided in the annular metal wiring 11, and a null hole 12 is formed on the same surface as that on which the bonding pads one layer below are arranged. Internal arrangement? The plating of O bonding pads 4a and 4c, which can be exposed to the side surface of the ceramic substrate through fM13, is also internally arranged directly on the side surface of the ceramic substrate without being connected to an external lead bin! You can send it through. In the embodiment shown in FIG. 2, power is supplied to the electrodes 10a and 10c by connecting metal #ll1s between the 11L pole and the bonding pad and between the bonding pad and the annular metal layer, respectively. If the bonding pads 4a and 4b cannot be provided due to the design margin of the board, the electrode 10a may be connected directly to the annular metal wiring 11 using a thin metal wire 5, as shown in FIG. . In this case, the conduction resistance can be made smaller than when a two-stage connection is made via the bonding pad 4a. Furthermore, if it is desired to further reduce the conduction resistance, two or more thin metal wires may be connected.

以上のようにして、全金属細線の接続が終了したら、シ
ール・リング６にキャップ（図示せず）をかぶせ、通常
のシーム・ウェルド法により封止すれば半導体装置が完
成する。After all the metal wires have been connected in the manner described above, the seal ring 6 is covered with a cap (not shown) and sealed by the usual seam welding method to complete the semiconductor device.

第一の実施例では、ボンティング・パッドの面と環状金
属配線の面とは段差があるので、金属細線を接続する装
置の性能によっては、この接続ができない場合がある。In the first embodiment, since there is a level difference between the surface of the bonding pad and the surface of the annular metal wiring, this connection may not be possible depending on the performance of the device for connecting the thin metal wires.

第二の実施例は、第一の実施例の上記の欠点を補うべく
行なわれたもので、その実施例を第５図に示す。第５図
（ａ）はその平面図、第５図（ｂ）は第５図（ａ）にお
けるＢ−Ｂ’の断面図である。The second embodiment was designed to compensate for the above-mentioned drawbacks of the first embodiment, and is shown in FIG. FIG. 5(a) is a plan view thereof, and FIG. 5(b) is a sectional view taken along line BB' in FIG. 5(a).

半導体装置は、その回路機能によっては、２系統の電源
を必要とする場合がある。第５図はこの場合の実施例を
示したもので、互いに絶縁された２重の環状金属配線１
１ａ、ｌｌｂを設け、それぞれ電源■、電源Ｈに対応さ
せて使用するものである。A semiconductor device may require two power sources depending on its circuit function. FIG. 5 shows an example of this case, in which double ring-shaped metal wiring 1 is insulated from each other.
1a and llb are provided, and are used in correspondence with power supply (2) and power supply H, respectively.

電源■の電極は１０ｇ、　ｈ、　Ｊであシ、電源■の電
極は１０ｅ、　ｆ、　ｉである。各電源電極は、それぞ
れボンディング・パッド４ｇ、　ｈ、　ｊと４ｅ、　ｆ
、　ｉに金属細線で接続されておシ、更に、スルーホー
ル１２ｇ。The electrodes of the power supply ■ are 10g, h, and J, and the electrodes of the power supply ■ are 10e, f, and i. Each power supply electrode has a bonding pad 4g, h, j and 4e, f, respectively.
, I is connected to I with a thin metal wire, and there is also a through hole 12g.

ｈ、ｊと１２ｅ、ｆ、ｉを介して環状金属配線１１ａ　
　と１１ｂに接続されている。このうち、ボンティング
・パッド４ｈと４ｅは内部配線８ｈ及び８ｅｉ通じて、
それぞれ外部リードビン９ｈ　９ｅ　につながっている
ので、ここにそれぞれ電源■及びｌｌ’を供給すれば、
半導体素子の電極Ｌｏｇ、　ｈ、　ｊに電源■が、電極
１０ｅ、ｆ、ｉには電源■が与えられる。Annular metal wiring 11a via h, j and 12e, f, i
and 11b. Of these, bonding pads 4h and 4e are connected to internal wirings 8h and 8ei,
Since they are connected to the external lead bins 9h and 9e, if you supply the power supplies ■ and ll' to these, respectively,
A power supply ■ is applied to the electrodes Log, h, and j of the semiconductor element, and a power supply ■ is applied to the electrodes 10e, f, and i.

壌状金輌配線のめっきは、それぞれ外部リードビンに接
続されているので、外部リードビンのめっきと同時に行
なえる。Since the metal wires are each connected to an external lead bin, plating can be performed simultaneously with the plating of the external lead bins.

この実施例では、２重の環状金属層を平面的に置いたが
、第６図のように、２層に分けて立体的に置けば、面積
を縮小できる利点がある。第６図（ａ）は、上の環状金
属層１１Ｃから側面メタライズ１５を介してボンディン
グ・パッド４とつないだ例、第６図（ｂ）はスルーホー
ル１２を介してポンディングパッド４とつないだ例で、
これらと同じことは、下層の金属配線層ｌｉｄについて
も同様のことができることは言うまでもない。In this embodiment, the double annular metal layer is placed two-dimensionally, but if it is divided into two layers and placed three-dimensionally as shown in FIG. 6, there is an advantage that the area can be reduced. FIG. 6(a) shows an example in which the upper annular metal layer 11C is connected to the bonding pad 4 via the side metallization 15, and FIG. 6(b) shows an example in which the upper annular metal layer 11C is connected to the bonding pad 4 via the through hole 12. For example,
It goes without saying that the same thing can be done for the lower metal wiring layer lid as well.

以上のようにして、全ての金属細線の接続が終了したら
、シールメタライズ１４上に金（Ａｕ　）と錫（Ｓｎ）
の合金板を挾んで金めつきしたコノく−ル　　（（Ｋｖ
）キャップ（図示せず）を載置し、加熱して合金板を融
かすことにより、シールが完了する。After all the thin metal wires are connected as described above, gold (Au) and tin (Sn) are placed on the seal metallization 14.
Gold-plated gold-plated metal alloy plate ((Kv
) The sealing is completed by placing a cap (not shown) and heating to melt the alloy plate.

以上の実施例は、いずれもＤＩＰ（Ｄｕａｌ　Ｉｎｌｉ
ｎｅＰａｃｋａｇｅ）形の半導体装置で説明したが、Ｐ
ＩＰ（Ｐｌｕｇ　Ｉｎ　Ｐａｃｋａｇｅ）形やチップキ
ャリア形、あるいはＱＩＰ（Ｑｕａｄｌｅ　Ｉｎ１ｉｎ
ｅ　Ｐａｃｋａｇｅ）形・Ｓ　Ｉ　Ｐ　（Ｓｉｎｇｌｅ
　Ｉｎ１ｉｎｅ　Ｐａｃｋａｇｅ）形などでも適用可能
であり、その形態を問わない。また、組立法も、ワイヤ
ボッディング法で説明したが、ＴＡＢ法やこれらの組み
立わせた方法でもよく、封止法も、上記の実施例に限ら
ない。The above embodiments all use DIP (Dual Inli
nePackage) type semiconductor device, but P
IP (Plug In Package) type, chip carrier type, or QIP (Quadle in 1in1)
ePackage) type/SIP (Single
It is also applicable to the In1ine Package) format, and the format is not limited. Furthermore, although the wire bodding method has been described as an assembly method, it may be a TAB method or a method combining these methods, and the sealing method is not limited to the above-mentioned embodiments.

更に、使用材料も以上の実施例に挙げたものには限らな
いことは勿論である。Furthermore, it goes without saying that the materials used are not limited to those listed in the above embodiments.

以上、詳細に説明したように、本発明によればセラミッ
ク基板の外部リードピン数を増やさずに半導体素子の電
源や接地の電極数を増やすことができ、品質の安定した
半導体装置を作ることができる。As described above in detail, according to the present invention, the number of power and ground electrodes of a semiconductor element can be increased without increasing the number of external lead pins of a ceramic substrate, and a semiconductor device with stable quality can be manufactured. .

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体装置を説明する断面図、第２図（
ａ）　、　（ｂ）は各々本発明の詳細な説明する平面図
と断面図、第３図は本発明の詳細な説明する平面図、第
４図は本発明の他の実施例を説明する平面図、第５図（
ａ）　、　（ｂ）は各々本発明の一実施例を説明する平
面図と断面図、第６図（ａ）　、　（ｂ）は各々本発明
のさらに他の実施例を説明する断面図であるＯ なお図において、１・・・・・・セラミック基板、２・
・・・・キャビティ、３・・・・・牛専体素子、４・・
・・・ポンディングパッド、５・　・金属細線、６・・
・・・・シール・リング、７・・・・・キャップ、８・
・・・・内部配線、９・・・・外部リードビン、１０・
・・・・・電極、１１・・・・・・環状金Ｘ配線、１２
・・・・・・スルーホール、１３・・・・・・側面メタ
ライズ、１４・・・・・シールメタライズ、１５・・・
・・・内部配線、である。 第１　図 １Ｉ　　４昆　　１θ　　３２ （ｇ　　　４Ｃ 第２図 第３図 １０記 第４図 （０−） 第５図 第６図Figure 1 is a cross-sectional view explaining a conventional semiconductor device, and Figure 2 (
a) and (b) are respectively a plan view and a sectional view explaining the present invention in detail, FIG. 3 is a plan view explaining the present invention in detail, and FIG. 4 is a plan view explaining another embodiment of the present invention. Figure, Figure 5 (
a) and (b) are a plan view and a cross-sectional view each illustrating one embodiment of the present invention, and FIGS. O In the figure, 1...ceramic substrate, 2...
...Cavity, 3...Cow exclusive element, 4...
・・・Ponding pad, 5・・Fine metal wire, 6・・
... Seal ring, 7 ... Cap, 8.
...Internal wiring, 9...External lead bin, 10.
...Electrode, 11...Annular gold X wiring, 12
...Through hole, 13...Side metalization, 14...Seal metalization, 15...
...Internal wiring. 1 Fig. 1I 4K 1θ 32 (g 4C Fig. 2 Fig. 3 Fig. 10 Fig. 4 (0-) Fig. 5 Fig. 6

Claims (2)

【特許請求の範囲】[Claims] （１）半導体素子と、その半導体素子を搭載するセラミ
ック基板と、その半導体素子を取り囲むように前記セラ
ミック基板の表面に形成したボンティング・パッドと、
前記半導体素子の電極と前記ポンプイングツくラドとを
結ぶ金属細線とを備えた半導体装置において、前記ボン
ティング・パッドの外周にはそれを取り囲むように環状
の金属細線が設けられていることを特徴とする半導体装
置。(1) a semiconductor element, a ceramic substrate on which the semiconductor element is mounted, and bonding pads formed on the surface of the ceramic substrate to surround the semiconductor element;
A semiconductor device comprising a thin metal wire connecting the electrode of the semiconductor element and the pumping pad, characterized in that a ring-shaped thin metal wire is provided around the outer periphery of the bonding pad so as to surround it. semiconductor devices. （２）ボンディング・ノくラドのうちの少なくとも１つ
は、そのボンディング・ノくット°ヲ取９囲む環状金属
細線とスルーホールまたは側面メタライズにより電気的
に導通していることを特徴とす(2) At least one of the bonding holes is characterized in that it is electrically connected to the annular thin metal wire surrounding the bonding hole through a through hole or side metallization.
JP57119306A 1982-07-09 1982-07-09 Semiconductor device Granted JPS5910240A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP57119306A JPS5910240A (en) 1982-07-09 1982-07-09 Semiconductor device
US06/511,935 US4608592A (en) 1982-07-09 1983-07-08 Semiconductor device provided with a package for a semiconductor element having a plurality of electrodes to be applied with substantially same voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57119306A JPS5910240A (en) 1982-07-09 1982-07-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5910240A true JPS5910240A (en) 1984-01-19
JPS6322614B2 JPS6322614B2 (en) 1988-05-12

Family

ID=14758154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57119306A Granted JPS5910240A (en) 1982-07-09 1982-07-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5910240A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5972749A (en) * 1982-10-19 1984-04-24 Nec Corp Semiconductor device
JPS59171152A (en) * 1983-03-17 1984-09-27 Nec Corp Semiconductor device
JPS62112354A (en) * 1985-11-12 1987-05-23 Nippon Telegr & Teleph Corp <Ntt> Integrated circuit package
JPS63500692A (en) * 1985-08-27 1988-03-10 ヒユ−ズ・エアクラフト・カンパニ− Ultra-small electronic package
JPH0497548A (en) * 1990-08-14 1992-03-30 Matsushita Electric Works Ltd Semiconductor chip carrier

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57211754A (en) * 1981-06-24 1982-12-25 Fujitsu Ltd Package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57211754A (en) * 1981-06-24 1982-12-25 Fujitsu Ltd Package

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5972749A (en) * 1982-10-19 1984-04-24 Nec Corp Semiconductor device
JPS6322615B2 (en) * 1982-10-19 1988-05-12 Nippon Electric Co
JPS59171152A (en) * 1983-03-17 1984-09-27 Nec Corp Semiconductor device
JPH0234458B2 (en) * 1983-03-17 1990-08-03 Nippon Electric Co
JPS63500692A (en) * 1985-08-27 1988-03-10 ヒユ−ズ・エアクラフト・カンパニ− Ultra-small electronic package
JPH0324067B2 (en) * 1985-08-27 1991-04-02 Hughes Aircraft Co
JPS62112354A (en) * 1985-11-12 1987-05-23 Nippon Telegr & Teleph Corp <Ntt> Integrated circuit package
JPH0497548A (en) * 1990-08-14 1992-03-30 Matsushita Electric Works Ltd Semiconductor chip carrier

Also Published As

Publication number Publication date
JPS6322614B2 (en) 1988-05-12

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