JPS5899843U - hybrid integrated circuit - Google Patents

hybrid integrated circuit

Info

Publication number
JPS5899843U
JPS5899843U JP19517981U JP19517981U JPS5899843U JP S5899843 U JPS5899843 U JP S5899843U JP 19517981 U JP19517981 U JP 19517981U JP 19517981 U JP19517981 U JP 19517981U JP S5899843 U JPS5899843 U JP S5899843U
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
substrate
circuit components
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19517981U
Other languages
Japanese (ja)
Inventor
忠義 高橋
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP19517981U priority Critical patent/JPS5899843U/en
Publication of JPS5899843U publication Critical patent/JPS5899843U/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は混成集積回路の従来例で、第1図aはその樹脂
竺覆前の斜視図、第1図すは樹脂被覆径樹脂の一部を除
去して示す正面−、第2図は本考案の一実施例で、第2
図aはその樹脂被覆前の斜視図、第2図すは樹脂被覆径
樹脂の一部を除去し     ゛て示す正面図、第3図
は別の実施例で、第3図aはその轡脂被覆前の斜視図、
第3図すは同じく側面図、第3図Cは樹脂被覆後の断面
図である。 2:回路部品チップ、4:被覆樹脂、5.6二基板、7
:回路部品個別素子。
Figure 1 shows a conventional example of a hybrid integrated circuit. Figure 1a is a perspective view of the circuit before it is covered with resin, Figure 1 is a front view with part of the resin coating removed, and Figure 2 is a In one embodiment of the present invention, the second
Figure a is a perspective view before the resin coating, Figure 2 is a front view with part of the resin coating removed, Figure 3 is another embodiment, and Figure 3a is the resin coating. Perspective view before coating,
FIG. 3 is a side view, and FIG. 3C is a sectional view after resin coating. 2: Circuit component chip, 4: Coating resin, 5.6 Two substrates, 7
: Circuit component individual element.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 配線導体を備えた基板上に回路部品を装着し、基板およ
び回路部品が樹脂によって被覆されるものにおいて、基
板が角を落した形状を有することを特徴とする混成集積
回路。
1. A hybrid integrated circuit in which circuit components are mounted on a substrate provided with wiring conductors, and the substrate and circuit components are covered with resin, wherein the substrate has a rounded corner shape.
JP19517981U 1981-12-26 1981-12-26 hybrid integrated circuit Pending JPS5899843U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19517981U JPS5899843U (en) 1981-12-26 1981-12-26 hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19517981U JPS5899843U (en) 1981-12-26 1981-12-26 hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS5899843U true JPS5899843U (en) 1983-07-07

Family

ID=30108462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19517981U Pending JPS5899843U (en) 1981-12-26 1981-12-26 hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5899843U (en)

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