JPS5898921A - Formation of wiring electrode - Google Patents

Formation of wiring electrode

Info

Publication number
JPS5898921A
JPS5898921A JP19680581A JP19680581A JPS5898921A JP S5898921 A JPS5898921 A JP S5898921A JP 19680581 A JP19680581 A JP 19680581A JP 19680581 A JP19680581 A JP 19680581A JP S5898921 A JPS5898921 A JP S5898921A
Authority
JP
Japan
Prior art keywords
film
thickness
polycrystalline silicon
molybdenum
wiring electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19680581A
Other languages
Japanese (ja)
Inventor
Nobuyoshi Kobayashi
伸好 小林
Seiichi Iwata
誠一 岩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19680581A priority Critical patent/JPS5898921A/en
Publication of JPS5898921A publication Critical patent/JPS5898921A/en
Pending legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers

Abstract

PURPOSE:To provide a method of forming a stable wiring electrode free from the problem of peeling off of the reaction product, wherein a siicon oxide film, polycrystalline silicon and a molybdenum film are formed successively formed on a substrate such that the molybdenum film has a thickness smaller than a half of the polycrystalline silicon film. CONSTITUTION:A thermal oxidation film 2 is formed on an Si substrate (100) 1 to have a thickness of 1,000Angstrom . Then, the film 2 is coated with a polycrystalline silicon film 3 which is formed by evaporation to have a thickness of 2,000Angstrom by low-voltage CVD. The polycrystalline silicon film 3 is then coated with an Mo film formed by an electron beam evaporation. When the thickness d1 of the Mo film 4 is made respectively 500, 550, 700 or 900Angstrom , the peeling of the films is prevented and MoSi2 5 is produced to form a stable wiring electrode, by a subsequent heating at 700 deg.C for 10min.

Description

【発明の詳細な説明】 本発明は、配線電極形成方法に関し、詳しくはシリサイ
ドを用いた配線電極の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming wiring electrodes, and more particularly to a method for forming wiring electrodes using silicide.

ＭＯ／　ｐｏｔｙｓｔ／ｓ　ｔｏ、という電極配線構造
は加熱に伴いモリブデンシリサイド／ｓｔｏ、という構
造を形成するために作られるが、反応生成物が３ｉへ膜
外面で剥離するため、得られる素子の信頼性が低いとい
う欠点があった。また％　Ｍｏ５ｉ。The electrode wiring structure MO/potyst/sto is created to form a molybdenum silicide/sto structure upon heating, but the reaction products peel off to 3i on the outer surface of the film, which reduces the reliability of the resulting device. It had the disadvantage of being low. Also %Mo5i.

を５ｉｌｌるいはｐｏｌｙＳｉ上に蒸着する方法もある
が、この場合には、蒸着膜にＯのような不純物が混入す
る可能性が大きく、電気抵抗が高くなつたり、蒸着の再
現性が！！がつ九というような欠点があった。There is also a method of vapor-depositing it on 5ill or polySi, but in this case, there is a high possibility that impurities such as O will be mixed into the vapor-deposited film, resulting in high electrical resistance and poor reproducibility of vapor deposition. ! There were some drawbacks.

本発明の目的は、上記従来の問題を解決し、モリブデン
シリサイドを用いた安定な配線電極を提供することにあ
る。An object of the present invention is to solve the above conventional problems and provide a stable wiring electrode using molybdenum silicide.

モリブデンと多結晶シリコンは、加熱すると反応してモ
リブデンシリサイドＭｎＳ輸を形成する。When heated, molybdenum and polycrystalline silicon react to form molybdenum silicide MnS.

一方、反応により形成されたシリサイドと酸化シリコン
との接着性は良くないので、酸化シリコ／膜と接触する
部分は多結晶シリコンの方が良い。On the other hand, since the adhesion between the silicide formed by the reaction and silicon oxide is not good, it is better to use polycrystalline silicon for the portion that contacts the silicon oxide/film.

本発明は％　Ｍｏ５ｔ、／ｐｏｔｙｓｔ／ｓｔｏ、　　
という構造にするどとにより、剥離の問題を解決するも
のであって、多結晶シリコン膜厚のほぼ半分以下に、モ
リブデン膜厚をおさえれはこの構造は容易に実現するこ
とができる。The present invention is % Mo5t, /potyst/sto,
This structure solves the problem of peeling, and this structure can be easily realized by keeping the thickness of the molybdenum film to about half or less than the thickness of the polycrystalline silicon film.

以下、本発明の一実施例を第１図を用いて説明する。第
１図（１）は、５ｉ（ｘｏｏ）ｘ上に熱酸化膜２を１０
００人形成した後、ｐｏｌｙＳｉ　（多結晶シリコン）
膜３を低圧ＣＶ　Ｄ　（ＣｈｅｍｉｃａｌＤｅｐｏｓ目
１ｏｎ）で膜厚２０００人蒸着し、さらにＭＯＯ４０電
子線蒸着した電極配線の構造を示す。An embodiment of the present invention will be described below with reference to FIG. FIG. 1 (1) shows a thermal oxide film 2 of 10
After forming 00 people, polySi (polycrystalline silicon)
The structure of the electrode wiring is shown in which the film 3 was deposited to a thickness of 2000 using low-pressure CVD (Chemical Deposits 1 on), and was further deposited by MOO40 with an electron beam.

この場合、ＭＯＯ４０膜厚ｄ１を、それぞれ５００人、
５５０人、７００人、９００人にし九場合には、第１図
（りに示すように、７００、β、１０分間加熱すると剥
離せずにＭｏ５ｔ、ｓが形成され、安定な電極配線がで
き喪。なお、このときにはｐｏｌｙ３ｉｓが残っていた
。In this case, MOO40 film thickness d1 is 500 people,
In the case of 550, 700, and 900 people, as shown in Figure 1, Mo5t,s is formed without peeling when heated at 700, β for 10 minutes, and stable electrode wiring is created. .At this time, poly3is remained.

これに反しｄ、を１００θÅ以上（１３００人。On the other hand, d is more than 100θÅ (1300 people).

１８５０人、２０００人）にした場合には、同様な加熱
によりＭＯ４とｐｏｌｙｓｉｓが反応した後、Ｓｉへ界
面から剥離した。なお、このときには反応後ｐｏｌｙＳ
ｉが洩っていなかった。すなわち、熱処理温度２７００
Ｃ以上としたとき％ＭＯ膜厚ｄ、をｐｏ１ｙ８１１１１
厚ｄ、のほぼ１７２以下にすれば、剥離せずに良好なＭ
Ｏ８’ｌ電極配線が形成される。1850 people, 2000 people), after MO4 and polysis reacted by similar heating, they were peeled off from the interface to Si. In addition, at this time, after the reaction polyS
i was not missed. That is, the heat treatment temperature is 2700
When C or more, %MO film thickness d, is po1y81111
If the thickness d is approximately 172 or less, good M can be achieved without peeling.
O8'l electrode wiring is formed.

本発明によれば、ＭＯとｐｏｌｙＳｉ　の重ね膜構造で
、安定なシリサイドを形成できるので、超高集積化回路
における配線電極形成方法として、特に有用である。According to the present invention, a stable silicide can be formed with a stacked film structure of MO and polySi, and therefore it is particularly useful as a method for forming wiring electrodes in ultra-highly integrated circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

＠１図は、本発明における熱処理前後の断面構造を説明
するため断面図である。 １・・・８４基板、２・・・シリコン酸化膜、３・・・
多結晶シリコン膜、４・・・モリブデン膜、５・・・モ
リブデン第　　１ （１ン （２〕Figure @1 is a cross-sectional view for explaining the cross-sectional structure before and after heat treatment in the present invention. 1...84 substrate, 2...silicon oxide film, 3...
Polycrystalline silicon film, 4... Molybdenum film, 5... Molybdenum 1st (1 n (2)

Claims (1)

【特許請求の範囲】[Claims] １、半導体基板上に酸化シリコン膜、多結晶シリコン膜
およびモリブデン膜を順次積層して被着した後、加熱し
てモリブデンシリサイド膜を形成するものにおいて、上
記モリブデン膜の膜厚は一上記多結晶シリコ／膜の膜厚
のほぼｌ／２以下であることを特徴とする配線電極形成
方法。1. In a method in which a silicon oxide film, a polycrystalline silicon film, and a molybdenum film are successively deposited and deposited on a semiconductor substrate and then heated to form a molybdenum silicide film, the thickness of the molybdenum film is equal to or less than the polycrystalline film. A method for forming a wiring electrode, characterized in that the thickness is approximately 1/2 or less of the film thickness of silicon/film.
JP19680581A 1981-12-09 1981-12-09 Formation of wiring electrode Pending JPS5898921A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19680581A JPS5898921A (en) 1981-12-09 1981-12-09 Formation of wiring electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19680581A JPS5898921A (en) 1981-12-09 1981-12-09 Formation of wiring electrode

Publications (1)

Publication Number Publication Date
JPS5898921A true JPS5898921A (en) 1983-06-13

Family

ID=16363935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19680581A Pending JPS5898921A (en) 1981-12-09 1981-12-09 Formation of wiring electrode

Country Status (1)

Country Link
JP (1) JPS5898921A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5211987A (en) * 1987-07-10 1993-05-18 Kabushiki Kaisha Toshiba Method and apparatus for forming refractory metal films
CN110373636A (en) * 2019-09-02 2019-10-25 西安邮电大学 A kind of preparation method of molybdenum silicide transistion metal compound thin-film material

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5211987A (en) * 1987-07-10 1993-05-18 Kabushiki Kaisha Toshiba Method and apparatus for forming refractory metal films
CN110373636A (en) * 2019-09-02 2019-10-25 西安邮电大学 A kind of preparation method of molybdenum silicide transistion metal compound thin-film material

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