JPS5893289A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5893289A JPS5893289A JP19212481A JP19212481A JPS5893289A JP S5893289 A JPS5893289 A JP S5893289A JP 19212481 A JP19212481 A JP 19212481A JP 19212481 A JP19212481 A JP 19212481A JP S5893289 A JPS5893289 A JP S5893289A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon nitride
- forming
- nitride film
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 2
- 239000007943 implant Substances 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は、ＭＮＯＳ不揮発メモリの製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing an MNOS nonvolatile memory.
従来ＭＮＯ９素子の製造に関しては、シリコン酸化膜を
５０〜１００人形成し、その上にシリコン窒化膜を５０
０大程度形成し、このシリコン酸化膜とシリコン窒化膜
の界面捕獲準位に電荷をトラップし、これによりしきい
値電圧をシフトさせデータを記録する不揮発メモリーと
している。ところが、実際のシリコン窒化膜には、多く
の準位が、膜内に広く分布するため、シリコン酸化膜を
トンネル効果で通過した、電荷（主に電子）は、シリコ
ン酸化膜−シリコン窒化膜界面だけでなくこのシリコン
窒化膜内の準位に多くトラップされる。このことは、消
去時、つまり、ゲート電極とシリコン基板層間に、電圧
を印加しても、ゲート電極近傍にトラップされている電
子は、基板へ逃げにくくなり、結果的に、消去特性の悪
い不揮発メモリーとなり、問題となっている。Conventionally, in manufacturing MNO9 elements, 50 to 100 people formed a silicon oxide film, and 50 to 50 people formed a silicon nitride film on top of it.
A non-volatile memory is formed in which the charge is trapped in the interface trap level between the silicon oxide film and the silicon nitride film, thereby shifting the threshold voltage and recording data. However, in an actual silicon nitride film, many levels are widely distributed within the film, so the charges (mainly electrons) that have passed through the silicon oxide film due to the tunnel effect are transferred to the silicon oxide film-silicon nitride film interface. Not only that, but a large amount of energy is trapped in the levels within this silicon nitride film. This means that during erasing, that is, even if a voltage is applied between the gate electrode and the silicon substrate layer, the electrons trapped near the gate electrode will have difficulty escaping to the substrate, resulting in a nonvolatile material with poor erasing characteristics. This becomes a memory problem.
従来これらの欠点を、除く方法として、シリコン酸化膜
−シリコン窒化膜界面に、金属層とか、金属酸化物層を
非常に薄くコーティングすることが試みられているが、
可動イオン等の混入がさけられず、ゲート電極へのリー
クが生じ易くなり、信頼性に欠けるものであった。Conventionally, attempts have been made to eliminate these drawbacks by coating the silicon oxide film-silicon nitride film interface with a very thin layer of metal or metal oxide.
The contamination of mobile ions and the like cannot be avoided, and leakage to the gate electrode is likely to occur, resulting in a lack of reliability.
そこで、本発明はトンネル効果により、侵入してきた電
荷を、効率よくシリコン酸化膜−シリコン窒化膜界面に
、捕獲し、しかも、従来の方法にみられる。ゲート電極
へのリークなどのないＭＮＯ８不揮発メモリの製造方法
を提供するものである。Therefore, the present invention uses a tunnel effect to efficiently trap the invading charges at the silicon oxide film-silicon nitride film interface, which is different from the conventional method. The present invention provides a method of manufacturing an MNO8 nonvolatile memory without leakage to the gate electrode.
第１図に、本発明の実施例をＰチャネルアルミゲー）Ｍ
ＮＯＳをもって説明する。Ｎ基板１０１に、Ｐ型不純物
としてボロンをドープしてソース・ドレイン１０２を形
成する。次に、シリコン酸化膜を形成後ゲート部のみエ
ツチング除去し、もう一度薄いゲート酸化膜１０３を形
成する。（第１図（ａ）） 次にシリコン窒化膜１
０４を、２００〜ａｏｏＸ稈度形成し、レジストもしく
は、シリコン酸化膜等によりゲート部以外全マスク１０
５十 ＋
する。これによりゲート部に、Ｈｅ、Ｎ などの不活
性軽元素イオンを２Ｘ１０ｎ〜８Ｘ １０” ｃｎｒ’
、シリコン窒化膜１０４の膜厚、加速電圧などのパラメ
ータに、シリコン酸化膜１０３に、イオン注入されない
よう考慮して打込みをする。（第１図（ｂ））
次に、マスク材１０５を除去後、シリコン窒化膜１０４
の一部を、エツチング除去し、もう一度シリコン窒化膜
１０６を形成し、前記のシリコン窒化膜１０４と合せて
４００〜８００Ｘの膜厚になるよう調整する。ここで、
シリコン窒化膜特に、上層のシリコン窒化膜の欠陥を取
り除くために、水素シンタ熱処理を行い、最後に、アル
ミニウムのゲート電極１０７を形成する。（“第１図（
Ｃ））このようにして作られた本発明のＭＮＯ８半導体
素子は次のような特長をもつ。An embodiment of the present invention is shown in FIG.
Explain using NOS. An N substrate 101 is doped with boron as a P type impurity to form a source/drain 102. Next, after forming a silicon oxide film, only the gate portion is removed by etching, and a thin gate oxide film 103 is again formed. (FIG. 1(a)) Next, silicon nitride film 1
04 to a 200 to aooX culm, and the entire mask 10 except the gate part is made of resist or silicon oxide film, etc.
50+. As a result, inert light element ions such as He and N are injected into the gate area at 2X10n~8X10"cnr'
The implantation is performed with consideration given to parameters such as the thickness of the silicon nitride film 104 and the acceleration voltage so that ions will not be implanted into the silicon oxide film 103. (FIG. 1(b)) Next, after removing the mask material 105, the silicon nitride film 104
A part of the silicon nitride film 106 is removed by etching, and a silicon nitride film 106 is formed again, and the film thickness is adjusted to be 400 to 800× in total with the silicon nitride film 104. here,
In order to remove defects in the silicon nitride film, especially the upper silicon nitride film, hydrogen sinter heat treatment is performed, and finally, an aluminum gate electrode 107 is formed. (“Figure 1 (
C)) The MNO8 semiconductor device of the present invention produced in this manner has the following features.
（１）軽イオン注入により下層のシリコン窒化膜には多
くの欠陥が拌在し、これによりこの層に多くの準位をも
つ。(1) Due to light ion implantation, many defects are mixed in the underlying silicon nitride film, and as a result, this layer has many levels.
（２） これに対し、上層のシリコン窒化膜は、欠陥
が少なく、同時に、準位も少ない。(2) In contrast, the upper silicon nitride film has fewer defects and, at the same time, fewer levels.
（３１（１）Ｉ（２）よりゲート酸化膜をトンネルして
通過した電荷は、ゲート酸化膜−下層シリコン窒化膜界
面近傍に多数存在する。(31(1)I(2)) A large number of charges that tunnel through the gate oxide film and pass through the gate oxide film exist near the interface between the gate oxide film and the lower silicon nitride film.
以上特長により、本発明のＭＮＯ８不揮発メモリーは、
消失特性、信頼性の高い素子といえる。Due to the above features, the MNO8 nonvolatile memory of the present invention has
It can be said that the element has high dissipation characteristics and high reliability.
第１図（α）〜（ｃ）が、本発明の実施例を示す。 以 上 出願人 株式会社諏訪精工舎 代理人 弁理士 最上 務 （矢） （０） 第１区 FIGS. 1(α) to (c) show examples of the present invention. that's all Applicant: Suwa Seikosha Co., Ltd. Agent Patent Attorney Mogami (arrow) (0) Ward 1
Claims (2)
Ｏｘｉｄｅ−８ｅｍｉｃｏｎｄｕｃｔｏｒ）素子の製造
に於いて、シリコン酸化膜を形成後、シリコン窒化＋
＋ 膜を形成、し、イオン打込みにより、Ｈｅ、Ｎ等の不活
性な軽元素イオンを、該シリコン窒化膜に注入し、熱処
理しそのあと第二シリコン窒化膜を形成することを特徴
とする半導体装置の製造方法。(1) MNOS (Metal-Nitride-
After forming a silicon oxide film, silicon nitride +
+ A semiconductor characterized by forming a film, implanting ions of an inert light element such as He or N into the silicon nitride film by ion implantation, heat-treating the film, and then forming a second silicon nitride film. Method of manufacturing the device.
を行なったのち、該シリコン窒化膜の一部をエツチング
除失することを特徴とする第一項記載の半導体装置の製
造方法。(2) The method for manufacturing a semiconductor device according to item 1, characterized in that after the ion-implanted silicon nitride film is subjected to heat treatment, a portion of the silicon nitride film is removed by etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19212481A JPS5893289A (en) | 1981-11-30 | 1981-11-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19212481A JPS5893289A (en) | 1981-11-30 | 1981-11-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5893289A true JPS5893289A (en) | 1983-06-02 |
| JPS6262070B2 JPS6262070B2 (en) | 1987-12-24 |
Family
ID=16286068
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19212481A Granted JPS5893289A (en) | 1981-11-30 | 1981-11-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5893289A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58212180A (en) * | 1982-06-03 | 1983-12-09 | Matsushita Electronics Corp | Nonvolatile memory device and manufacture thereof |
| JPS5969973A (en) * | 1982-10-15 | 1984-04-20 | Nec Corp | Semiconductor device |
| JPS603159A (en) * | 1983-06-21 | 1985-01-09 | Matsushita Electronics Corp | Manufacture of nonvolatile memory device |
| US5470771A (en) * | 1989-04-28 | 1995-11-28 | Nippondenso Co., Ltd. | Method of manufacturing a floating gate memory device |
| US6373093B2 (en) | 1989-04-28 | 2002-04-16 | Nippondenso Corporation | Semiconductor memory device and method of manufacturing the same |
| WO2004021449A1 (en) * | 2002-08-30 | 2004-03-11 | Fasl Llc | Semiconductor memory and method for manufacturing same |
-
1981
- 1981-11-30 JP JP19212481A patent/JPS5893289A/en active Granted
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58212180A (en) * | 1982-06-03 | 1983-12-09 | Matsushita Electronics Corp | Nonvolatile memory device and manufacture thereof |
| JPH0334672B2 (en) * | 1982-06-03 | 1991-05-23 | Matsushita Electronics Corp | |
| JPS5969973A (en) * | 1982-10-15 | 1984-04-20 | Nec Corp | Semiconductor device |
| JPS603159A (en) * | 1983-06-21 | 1985-01-09 | Matsushita Electronics Corp | Manufacture of nonvolatile memory device |
| US5470771A (en) * | 1989-04-28 | 1995-11-28 | Nippondenso Co., Ltd. | Method of manufacturing a floating gate memory device |
| US6365458B1 (en) | 1989-04-28 | 2002-04-02 | Nippondenso Co., Ltd. | Semiconductor memory device and method of manufacturing the same |
| US6373093B2 (en) | 1989-04-28 | 2002-04-16 | Nippondenso Corporation | Semiconductor memory device and method of manufacturing the same |
| US6525400B2 (en) | 1989-04-28 | 2003-02-25 | Denso Corporation | Semiconductor memory device and method of manufacturing the same |
| WO2004021449A1 (en) * | 2002-08-30 | 2004-03-11 | Fasl Llc | Semiconductor memory and method for manufacturing same |
| US7253046B2 (en) | 2002-08-30 | 2007-08-07 | Spansion Llc. | Semiconductor memory device and manufacturing method thereof |
| US7410857B2 (en) | 2002-08-30 | 2008-08-12 | Spansion Llc. | Semiconductor memory device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6262070B2 (en) | 1987-12-24 |
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