JPS5893251A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5893251A
JPS5893251A JP19216381A JP19216381A JPS5893251A JP S5893251 A JPS5893251 A JP S5893251A JP 19216381 A JP19216381 A JP 19216381A JP 19216381 A JP19216381 A JP 19216381A JP S5893251 A JPS5893251 A JP S5893251A
Authority
JP
Japan
Prior art keywords
recess
film
field region
insulating film
field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19216381A
Other languages
Japanese (ja)
Inventor
Riyouichi Hazuki
巴月　良一
Takahiko Moriya
守屋　孝彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP19216381A priority Critical patent/JPS5893251A/en
Publication of JPS5893251A publication Critical patent/JPS5893251A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To obtain a flat field insulating layer in a recess formed in a field region of a semiconductor substrate by first forming an insulating layer having a thickness deeper than the recess on the entire surface including the recess when the recess is buried with an insulating film, and removing the thick insulating layer except the recess by reactive ion etching specified in the flow are rate ratio of C3F8 to H2. CONSTITUTION:A thin SiO2 is covered on a P type Si substrate 1 having a surface azimuth (100), a window is opened corresponding to a field region, the film is etched with a mixture solution of KOH and isopropyl alcohol, thereby forming a recess on the field region, and a field inversion preventive layer 3 is formed on the bottom surface of the recess. Then, the film 2 is removed, a thin oxidized film 4 is formed on the overall surface including the recess, and an SiO2 film 5 having a thickness deeper than the depth of the recess is covered by a plasma gas phase growing method on the film 4. Subsequently, it is etched by 10-50%-H2/C3H8 reactive gas ions, thereby removing most of the film 5, and the film 5 having flat surface is allowed to remain only in the recess.

Description

【発明の詳細な説明】 発明の技術分野 本発明は、フィールド領域に絶縁膜を埋め込む半導体装
置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which an insulating film is buried in a field region.

発明の技術的背景とその問題点 従来、シリコンを用いた半導体装Ｖイ、特にＭＯ８半導
体果檀回路装置では、寄生チャネルによる絶縁不良をな
くし寄生容量を小さくするために素子間のフィールド領
域に厚い絶縁膜を形成する方法として、選択酸化法が多
用されている。Technical background of the invention and its problems Conventionally, in semiconductor devices using silicon, especially MO8 semiconductor circuit devices, thick field regions between elements have been used to eliminate insulation defects caused by parasitic channels and reduce parasitic capacitance. A selective oxidation method is often used as a method for forming an insulating film.

しかしながら、微細化および高密度化が進む集積回路の
素子間分離に上記選択酸化法を用いる場合、次のような
問題があった。すなわち、厚いフィールド酸化膜を選択
的に形成する際、横方°向にも酸化が進行するため、耐
酸化性マスクである窒化シリコン膜の端部から酸化膜が
鳥のくちばしくバードビーク）状に食い込み、これが素
子領域の寸法誤差を生じ、高密度化の妨げとなる。また
、酸化時には例えば１０００［Ｕ）５時間といった高温
で長時間の熱処理が必要なため、既にドープされている
フィールド領域の不純物の再拡散によ多素子特性の劣化
を招く。However, when the above-mentioned selective oxidation method is used for isolation between elements of integrated circuits that are becoming increasingly finer and more dense, the following problems arise. In other words, when a thick field oxide film is selectively formed, oxidation also progresses in the lateral direction, causing the oxide film to form a bird's beak shape from the edge of the silicon nitride film, which is an oxidation-resistant mask. This intrusion causes dimensional errors in the element area, which impedes higher density. Further, during oxidation, a long time heat treatment at a high temperature of, for example, 1000 [U] for 5 hours is required, which causes deterioration of multi-element characteristics due to re-diffusion of impurities in the already doped field region.

さらに、選択酸化法では、基板表向にフィールド酸化膜
膜厚の約手分の段差が生じる。この段差は、配緋層の段
切れ等の原因となシ、製品の歩留りを低下させる。Furthermore, in the selective oxidation method, a level difference approximately equal to the thickness of the field oxide film occurs on the surface of the substrate. This step causes breakage of the scarlet layer and reduces the yield of the product.

一力、フィールド酸化膜全形成する前に基板表面を一部
エッチングして、フィールド酸化膜を基板中に埋め込む
方法がＢＯＸ構造として公知であるが、前述のように、
酸化中、フィールド酸化膜は窒化シリコン膜の端部から
鳥のくちばし状に食い込むため、窒化シリコン膜の端で
は、鳥の頭（バードヘッド）状に酸化膜が盛シ土がシ、
やけシ段差が生じることになシ、配線の信頼性を低下さ
せ、製品の歩留シラ落とす原因となる。A method known as the BOX structure is to partially etch the surface of the substrate and bury the field oxide film in the substrate before forming the entire field oxide film, but as mentioned above,
During oxidation, the field oxide film digs into the edge of the silicon nitride film in a bird's beak shape.
Unavoidable occurrence of burnt steps will reduce the reliability of the wiring and cause a drop in product yield.

発明の目的 本発明の目的は、基板表面を一部エッチングして形成し
たフィールド領域に絶縁膜を完全に埋め込み、かつその
表面を平坦化することができ、微ａ＋素子の高集積化全
可能とする半導体装置の製造方法を提供することにある
。Purpose of the Invention The purpose of the present invention is to completely embed an insulating film in a field region formed by partially etching the surface of a substrate, and to flatten the surface, thereby making it possible to achieve high integration of micro-A+ devices. An object of the present invention is to provide a method for manufacturing a semiconductor device.

発明の概要 本発明者等は、凹凸を有した絶縁膜の段差をなだらかに
することを目的として鋭意研究を重ねた結果、Ｃ、Ｈ、
Ｆ’に含む混合ガスを反応性ガスとする反応性イオンエ
ツチング法を用い絶縁膜の表面を所定量エツチングすれ
はよいことを見出した。すなわち、本発明者等の実験に
よればＣ３Ｆ８とＨ２との混合ガスを反応性ガスとする
反応性イオンエツチング法を用いて凹凸のある絶縁膜を
エツチングしたところ絶縁膜の表面段差を急峻なものか
らなだらかなものにすることができた。これは、絶縁膜
のエツチング時に生じるポリマが絶−膜の平坦部に付着
し易く凸部端部には付着し難いためである。つまり、絶
縁膜の凸部や凹部の平坦部では上記ポリマの付着が多い
ためエツチングか阻害され、凸部端ではポリマの付着が
少ないためエツチングがほとんど阻害されないからであ
る。そして、ポリマ生成量は反応性ガスの一部として添
加するＨの添加量によシ可変することが判った。さらに
、本発明者等は、Ｈの添加量を適当に選択することによ
って、絶縁膜の凹部に特にポリマを付着させ易くできる
ことを見出した。Summary of the Invention The inventors of the present invention have conducted extensive research aimed at smoothing out the steps of an insulating film with unevenness, and as a result, they have developed C, H,
It has been found that the surface of the insulating film can be etched by a predetermined amount using a reactive ion etching method using a mixed gas contained in F' as a reactive gas. That is, according to experiments conducted by the present inventors, when an uneven insulating film was etched using a reactive ion etching method using a mixed gas of C3F8 and H2 as a reactive gas, the surface level difference of the insulating film became steep. I was able to make it gentle. This is because the polymer produced during etching of the insulating film tends to adhere to the flat parts of the insulating film and is difficult to adhere to the ends of the convex parts. In other words, etching is inhibited on the flat portions of the convex portions and concave portions of the insulating film since there is a large amount of the polymer attached thereto, whereas etching is hardly inhibited at the edges of the convex portions because there is less polymer attached thereon. It has also been found that the amount of polymer produced varies depending on the amount of H added as part of the reactive gas. Furthermore, the present inventors have found that by appropriately selecting the amount of H added, it is possible to make it particularly easy to attach the polymer to the recesses of the insulating film.

本発明はこのような点に着目し、半導体基板のフィール
ド領域に凹部を形成したのち、上記凹部が形成された基
板上に該凹部の段差より厚く絶縁層を被着し、しかるの
ちＣ、Ｈ、Ｆ′ｆ：含む混合ガスを反応性ガスとする反
応性イオンエツチング法を用いて上記絶縁Ｍをエツチン
グするようにした方法である。The present invention has focused on such points, and after forming a recess in the field region of a semiconductor substrate, an insulating layer is deposited on the substrate in which the recess is formed to be thicker than the step of the recess, and then C, H , F'f: This is a method in which the insulation M is etched using a reactive ion etching method using a mixed gas containing the reactive gas.

発明の効果 本発明によれは、Ｃ，Ｈ，Ｆを含む混合ガスを反応性ガ
スとする反応性イオンエツチング法を用い、Ｈの添加量
を適当に制御することによって、前述した如く絶縁膜の
凹部におけるポリマの付着を特に多くすることができる
。したが＝５− って、絶縁膜の凸部を凹部に比して速いエツチング速度
でエツチングすることができ、これによシフイールド領
域である凹部に絶縁膜を残存せしめ、かつその表面全路
平坦なものにすることができる。このため、フィールド
酸化膜の段差をなくし、製品歩留シの向上をはかシ得る
。Effects of the Invention According to the present invention, an insulating film can be formed as described above by using a reactive ion etching method using a mixed gas containing C, H, and F as a reactive gas, and by appropriately controlling the amount of H added. Particularly high adhesion of the polymer in the recesses can be achieved. Therefore, the convex portions of the insulating film can be etched at a higher etching speed than the concave portions, and this allows the insulating film to remain in the concave portions, which are the shift field regions, and to make the entire surface flat. can be made into something. Therefore, the step difference in the field oxide film can be eliminated and the product yield can be improved.

さらに、高温長時間の熱処理が不要となるため、フィー
ルド領域の不純物の再分布もなくな勺、素子特性の向上
をはかシ得る。したがって、微細素子の高集積化に絶大
なる効果を発揮する。Furthermore, since high-temperature, long-term heat treatment is not necessary, there is no redistribution of impurities in the field region, and device characteristics can be improved. Therefore, it is extremely effective in increasing the degree of integration of fine elements.

発明の実施例 第１図乃至第４図は本発明の一実施例を示す工程断面図
である。壕す、第１図に示す如く、面方位（１００）の
Ｐ型シリコン基板１土に酸化シリコン膜２を、例えば３
０００〔Ｘ）程度形成し、素子形成領域上の酸化膜２を
残して、フィールド領域上の酸化膜を、例えはＲＩＥ法
（反応性イオンエツチング法）でエツチングし、続いて
酸化膜２をマスクして、１．０（μｍ〕程度フィールド
領域のシリコン基板１をエツチングして凹６− 部を形成する。シリコン基板１のエツチングは、例えは
ＲＩＥ法や、ＫＯＨとイソプロピルアルコールの混液に
よシ行なう。次に、第２図に示す如く酸化膜２をマスク
してフィールド反転防止層３を形成する。その後、酸化
膜２を除去し第３図に示す如く、例えは１０００〔℃〕
０２中で、約１ｏｏｏ［Ｘ）程度の熱酸化膜４を改めて
全面に形成した後、酸化シリコン膜５を、例えば５ＩＨ
４とＮ２０ガスを用いたプラズマ気相成長法或いはＳｉ
Ｈ４と０□ガスを用いた減圧気相成長法によシ約１．５
〔μｍ〕被着する。次いで、Ｃ３Ｆ８とＮ２との混合ガ
スを用いたＲＩＥ法によシ酸化シリコン膜５を約１．５
〔μｍ〕除去したところ、第４図に示す如くフィールド
領域のみに平坦に酸化シリコン膜５が残存された。ここ
で、上記ＲＩＥ法によるエツチングでは、平行平板電極
の内、高周波印加側の電極に試料を置き、Ｃ３Ｆ（３２
０（ｃｃ／ｍｉｎ　）、Ｎ２２〜１０〔ｃｃ／ｒｒ１１
ｎ〕、ＲＦｐｏｗｅｒ　５０〜２００［：Ｗ］、圧力０
．００５〜０：０５［Ｔｏｒｒ　：］の範囲条件で行な
った。Embodiment of the Invention FIGS. 1 to 4 are process sectional views showing an embodiment of the invention. As shown in FIG.
The oxide film 2 on the field region is etched by, for example, RIE (reactive ion etching), leaving the oxide film 2 on the element formation region, and then the oxide film 2 is etched with a mask. Then, the silicon substrate 1 is etched in a field region of about 1.0 (μm) to form a recess 6. The silicon substrate 1 is etched by, for example, the RIE method or a mixture of KOH and isopropyl alcohol. Next, as shown in FIG. 2, the oxide film 2 is masked to form a field inversion prevention layer 3. After that, the oxide film 2 is removed and heated to a temperature of, for example, 1000°C, as shown in FIG.
After forming a thermal oxide film 4 of approximately 1ooo[X] on the entire surface in 02, the silicon oxide film 5 is coated with
4 and N20 gas or Si
Approximately 1.5
[μm] Deposit. Next, the silicon oxide film 5 is heated to approximately 1.5
When [μm] was removed, a flat silicon oxide film 5 remained only in the field region as shown in FIG. Here, in the etching by the RIE method described above, the sample is placed on the high frequency application side of the parallel plate electrodes, and C3F (32
0 (cc/min), N22~10 [cc/rr11
n], RF power 50-200 [:W], pressure 0
．． The test was carried out under conditions ranging from 0.005 to 0.05 [Torr:].

酸化シリコン膜５か凹部にのみなだらかに残存する理由
はＣ，ＦａとＮ２とを反応性ガスとして用いた反応性イ
オンエツチング法により酸化シリコンをエツチングした
場合、凹部でのエツチング速度が平坦部に比べて小さい
ためである。なお、Ｎ２の添加はエツチング進行を阻害
するＣ−Ｆポリマー生成の役を果し、またＣ−Ｆポリマ
ーは凹部で特に付着しやすいと考えられるので、Ｎ２の
添加蓋が１０Ｃ％）未満では、Ｃ−Ｆポリマーはほとん
ど生成せず、エツチングは場所によらず垂直方向に均一
に行なわれ、本発明の効果は得られなかった。また、Ｎ
２添加量が５０〔チ〕を越えると、酸化シリコン膜５全
而にＣ−Ｆポリマーが生成するので、やけシ本発明の効
果は得られなかった。The reason why the silicon oxide film 5 remains only in the recesses is that when silicon oxide is etched by the reactive ion etching method using C, Fa, and N2 as reactive gases, the etching speed in the recesses is faster than in the flat parts. This is because it is small. Note that the addition of N2 plays a role in the production of C-F polymers that inhibit the progress of etching, and it is thought that C-F polymers are particularly likely to adhere to recesses, so if the N2 addition cap is less than 10C%, Almost no C--F polymer was produced, and etching was performed uniformly in the vertical direction regardless of location, so that the effects of the present invention could not be obtained. Also, N
When the amount of 2 added exceeds 50 [chi], the C--F polymer is formed throughout the silicon oxide film 5, so that the effects of the present invention could not be obtained.

かくして本夷流例力法によれは、従来の選択酸化法と同
様に一回の写真食刻工程により、フィールド領域に絶縁
膜と反転防止層をセルファラインで形成することができ
る。しかも、前述したような選択酸化法による問題点も
解決された。即ち、寸法誤差なくフィールド絶縁ｆＭ全
平坦な状態で埋め込むことができ、フィールド絶縁膜の
形成に高温長時間の熱処理工程が全く不要になったため
、フィールド領域の不純物の再分布をも防止することが
できる。Thus, according to the present method, an insulating film and an anti-inversion layer can be formed in the field region in a self-aligned manner by a single photolithography process, similar to the conventional selective oxidation method. Moreover, the problems caused by the selective oxidation method as described above have also been solved. That is, the field insulation fM can be buried in a completely flat state without any dimensional errors, and a high temperature and long time heat treatment process is completely unnecessary for forming the field insulation film, so that redistribution of impurities in the field region can also be prevented. can.

なお、本発明は上述した実施例に限定されるものではな
い。例えは、前記酸化シリコン膜をエツチングする際の
反応性ガスとしては、０５Ｆ８−Ｎ２との混合ガスに限
るものではなく、Ｃ２Ｆ６　　”２　＊　ＣＦ４　　Ｎ
２混合ガス或いはＣＨＦ３’ｉｉ−用いることも可能で
ある。また、酸化シリコン膜の代夛に各種の絶縁膜に適
用することも可能である。その他、本発明の要旨を逸脱
しない範囲で、種々変形して実施することができる、Note that the present invention is not limited to the embodiments described above. For example, the reactive gas used when etching the silicon oxide film is not limited to a mixed gas with 05F8-N2, but also C2F6''2*CF4N.
It is also possible to use a mixed gas of CHF2 or CHF3'ii. Furthermore, it is also possible to apply the present invention to various types of insulating films instead of silicon oxide films. In addition, various modifications can be made without departing from the gist of the present invention.

【図面の簡単な説明】[Brief explanation of drawings]

第１図乃至第４図は本発明の一実施例を示す工程断面図
である。 １・・・シリコン基板（半導体基板〕、２・・・酸化シ
リコン膜、３・・・反転防止層、４・・・熱酸化膜。 ５・・・酸化シリコン膜（絶縁膜）。 ９− 第１図　　　。 ？ 第２図　　　２1 to 4 are process sectional views showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Silicon substrate (semiconductor substrate), 2... Silicon oxide film, 3... Inversion prevention layer, 4... Thermal oxide film. 5... Silicon oxide film (insulating film). 9-th Figure 1. ? Figure 2 2

Claims (3)

【特許請求の範囲】[Claims] （１）半導体基板のフィールド領域に凹部を形成する工
程と、上記凹部が形成された基板上に該凹部の段差よシ
厚く絶縁層を被着する工程と、Ｃ，Ｈ，Ｆｋ含む混合ガ
スを反応性ガスとする反応性イオンエツチング法を用い
て上記絶縁膜をエツチングする工程とを具備し、前記凹
部に上記絶縁膜を残存せしめ、かつその表面を平坦化す
ること’ｔ％徴とする半導体装置の製造方法。(1) A step of forming a recess in the field region of a semiconductor substrate, a step of depositing an insulating layer thicker than the step of the recess on the substrate in which the recess is formed, and a step of forming a mixed gas containing C, H, and Fk. a step of etching the insulating film using a reactive ion etching method using a reactive gas, leaving the insulating film in the recess and flattening the surface thereof. Method of manufacturing the device. （２）　　前記絶縁膜をエツチングする工程として、Ｃ
５Ｆ６とＨ２との混合ガスを反応性ガスとする反応性イ
オンエツチング法を用い、０５ＦＢとＨ２との流量比（
Ｈｚ／Ｃ３Ｆａ　）を１０〜５０［チ〕に設定したこと
全特徴とする特許請求の範囲第１項記載の半導体装置の
製造方法。(2) As the step of etching the insulating film, C
Using a reactive ion etching method using a mixed gas of 5F6 and H2 as a reactive gas, the flow rate ratio of 05FB and H2 (
2. The method of manufacturing a semiconductor device according to claim 1, characterized in that Hz/C3Fa) is set to 10 to 50 [chi]. （３）前ｉ上絶縁膜として酸化シリコン膜を用いたこと
を特徴とする特許請求の範囲第１項記載の半導体装置の
製造方法。(3) A method for manufacturing a semiconductor device according to claim 1, characterized in that a silicon oxide film is used as the insulating film on the front i.
JP19216381A 1981-11-30 1981-11-30 Manufacture of semiconductor device Pending JPS5893251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19216381A JPS5893251A (en) 1981-11-30 1981-11-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19216381A JPS5893251A (en) 1981-11-30 1981-11-30 Manufacture of semiconductor device

Publications (1)

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JPS5893251A true JPS5893251A (en) 1983-06-02

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JP19216381A Pending JPS5893251A (en) 1981-11-30 1981-11-30 Manufacture of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007083777A (en) * 2005-09-20 2007-04-05 Mazda Motor Corp Vehicular seat device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007083777A (en) * 2005-09-20 2007-04-05 Mazda Motor Corp Vehicular seat device

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