JPS5891681A - Field-effect type transistor - Google Patents
Field-effect type transistorInfo
- Publication number
- JPS5891681A JPS5891681A JP18907581A JP18907581A JPS5891681A JP S5891681 A JPS5891681 A JP S5891681A JP 18907581 A JP18907581 A JP 18907581A JP 18907581 A JP18907581 A JP 18907581A JP S5891681 A JPS5891681 A JP S5891681A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- type
- onto
- gaas layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 35
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は化合物中導体ICを構成する電界効果型トラ
ンジスタ(以下FETという)に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor (hereinafter referred to as FET) constituting a compound conductor IC.
従来、超高速型の化合物半導体ICI構成するFITと
して第1図に示すものがあった。このFETは、半絶縁
性のGJLA1基板1の上に、分子ビームエピタキシャ
ル法などの成長を精密に制御することができるエピタキ
シャル法によって高純度のGaAs層2お工びn型にド
ーピングしたGaAjAs層3t−成長させ、このGt
&&As層3の上にショットキf−)電1i4.オーミ
ック電極のソース電極5お工びドレイン電極6會形成し
たものである。Conventionally, there has been an FIT configured as an ultra-high-speed compound semiconductor ICI as shown in FIG. This FET consists of a high-purity GaAs layer 2 formed on a semi-insulating GJLA1 substrate 1 by an epitaxial method that allows precise growth control such as molecular beam epitaxial method, and an n-type doped GaAjAs layer 3t. -Grow this Gt
Schottky f-) electrode 1i4. on top of &&As layer 3. The source electrode 5 and the drain electrode 6 are formed as ohmic electrodes.
このようなGaAjAs層3とGN&I 2のへテロ界
面に形成される2次元電子ガス層7を利用したFETは
、イオン化したドナの散乱が少なくなるために、7オノ
ン散乱が少なくなる低温で高性能な特性が得られる。こ
の場合、n型のGtAjA@層3の厚さに工□jl、F
ETはノーマリオン型にもノーマリオン型にもなる。An FET that uses such a two-dimensional electron gas layer 7 formed at the hetero interface between the GaAjAs layer 3 and the GN&I 2 has high performance at low temperatures with less 7-onone scattering due to less scattering of ionized donors. characteristics can be obtained. In this case, the thickness of the n-type GtAjA@layer 3 is
ET can be either a normalion type or a normalion type.
また、1層のみの変調ドーピングについては、第1図に
示した構成の他に、第2図に示す工うにnJJのGaA
jAs層と高純度のGi人a層とを逆転させたものが考
えられる。すなわち、第2図に図すFETは、半絶縁性
GaAs基板8の上に、n型のGaAムS層9お工び高
純度のGaAs層10’を成長させたものである。しか
し、この構成の場合には、高純度のGaA1層10層表
0単位のためにとのGaAs 710表面から空乏層が
拡が9.2次元電子ガス層が形成されない場合が多い。Regarding the modulation doping of only one layer, in addition to the structure shown in FIG. 1, the structure shown in FIG.
It is conceivable that the jAs layer and the high-purity Gi a layer are reversed. That is, the FET shown in FIG. 2 has an n-type GaAs layer 9 and a high-purity GaAs layer 10' grown on a semi-insulating GaAs substrate 8. However, in the case of this configuration, a depletion layer spreads from the surface of the GaAs 710 due to the 0 units on the top of the 10 layers of high-purity GaA, and a 9.2-dimensional electron gas layer is not formed in many cases.
この場合には、電子は移動度の低いGaAlA1層9を
流れるために、変調ドーピングの利点が失なわれてしま
うという問題がある。In this case, there is a problem that the advantage of modulation doping is lost because electrons flow through the GaAlA1 layer 9 having low mobility.
この発明は、n型のGaAs層内層の上に成長させた高
純度のGaA1層の上に、さらK n IIのGaAm
層を形成することによシ、前述した表面単位の影響によ
る間M’を解決して、変調ドーピングによって形成され
る2次元電子ガス層を利用した高性能のli’ETを実
現させることt目的としている。In this invention, K n II GaAm is further grown on a high purity GaAl layer grown on an n-type GaAs inner layer.
The purpose is to solve the above-mentioned surface unit effect of M' by forming a layer, and to realize high-performance LI'ET using a two-dimensional electron gas layer formed by modulation doping. It is said that
以下、この発明の一実施例につき第3図を参照して詳述
する。この実施例のFETh、半絶縁性G−・3基板1
1上に、ドーピングしないGaAIAS層12をこれよ
シ上の層の電子が拡散して米ないように成長させ、この
GaAtA易層12の上にn型にドーピングしたGaA
AAs層13に成長させ、このGaAムS層13の上に
高純度のGaAs層14を成長させ、さらに高純度のG
aAs層14′の上にn型にドーピングしたGaAs層
15’tg長させる。このn型のG麩S層15の上にシ
ョットキf−)電極16、オーミック電極のソース電極
17おLびPレイン電極18を形成する4のである。そ
して、前記n型のGaAs層15がないものでは、 G
aAsの表面単位による空乏層の拡がシによって高純度
のGaAs層14とnWiのGaAtAs層13の界面
に2次元電子ガス層が形成されにくいが、n型のGaA
s層15があるこの実施例によるFETの場合には、n
型のGaAs層15に空乏層が拡がるのを抑えることが
でき、このために、高純度OGaAs層14とn型のG
aAA&m層13のへテロ界面に2次元電子ガス層18
が形成される。また、n型のGaAs層15の電子濃度
や厚さを制御することによって、このPETはノーマリ
オフ型にすることもノーマリオフ型にすることもできる
。さらに、FETとして動作する時に、n型のGtAs
層1s全1st電子ると、このnfiのGaAs層内の
イオン化し友ドナの散乱があるために、2次元電子ガス
層18の高移動度であることによる有利性が少なくなる
が、FETの動作範囲としてダート電極16の下のn型
のGaAs層15が常に完全に空乏層になっているよう
な条件にすれば、前記有利性が損なわれることはない。Hereinafter, one embodiment of the present invention will be described in detail with reference to FIG. FETh of this example, semi-insulating G-3 substrate 1
1, an undoped GaAIAS layer 12 is grown in such a way that electrons from the layer above are not diffused and do not form, and on this GaAtA layer 12, an n-type doped GaAI
A high-purity GaAs layer 14 is grown on the GaAs layer 13, and a high-purity GaAs layer 14 is grown on the GaAs layer 13.
An n-type doped GaAs layer 15'tg is formed on the aAs layer 14'. On this n-type G-S layer 15, a Schottky f-) electrode 16, an ohmic source electrode 17, and a P-rain electrode 18 are formed. In the case where the n-type GaAs layer 15 is not present, G
It is difficult to form a two-dimensional electron gas layer at the interface between the high-purity GaAs layer 14 and the nWi GaAtAs layer 13 due to the expansion of the depletion layer in units of the aAs surface.
For the FET according to this embodiment with s-layer 15, n
It is possible to suppress the expansion of the depletion layer in the type GaAs layer 15, and for this reason, the high purity OGaAs layer 14 and the n-type GaAs layer 15 can be prevented from expanding.
A two-dimensional electron gas layer 18 at the hetero interface of the aAA&m layer 13
is formed. Further, by controlling the electron concentration and thickness of the n-type GaAs layer 15, this PET can be made into a normally-off type or a normally-off type. Furthermore, when operating as a FET, n-type GtAs
When all 1st electrons in the layer 1s are used, the advantage of the high mobility of the two-dimensional electron gas layer 18 is reduced due to the scattering of ionized friends in the GaAs layer of this nfi, but the operation of the FET is As long as the conditions are such that the n-type GaAs layer 15 under the dirt electrode 16 is always completely depleted, the above advantages will not be impaired.
前述したようにこの実施例のFETは、高純度のGaA
s層14の上にn型のGaAs層15t−成長させて、
これらの上にダート、ソースおよびドレイン電極17.
16および18會形成することにエフ、GaAs表面の
表面準位の影響を除き、n型のGL仏s層13と高純度
のGaAs層14の界面にできる2次元電子ガス層18
を利用した高性能のF’ET ’を楊供することができ
る。そして、このFETの構成では、オーミック電極V
i−n型のGaAs層の上に形成しであるので、その接
触抵践はGmlAs層の上にオーミック電&を形成した
もの(第1図参照)に比べて小さく、ICの能動素子と
して使用した場合に、そのオン抵抗が小さくなる。また
、このFITは、表面のn型のGaAs層の電子濃度、
厚さによってFETのスレッシュホルド電圧を制御でき
るので、ノーマリオン型、ノーマリオフ型のどちらのF
ETKすることも可能である。As mentioned above, the FET of this example is made of high-purity GaA
An n-type GaAs layer 15t is grown on the s-layer 14,
On top of these are dirt, source and drain electrodes 17.
16 and 18, the two-dimensional electron gas layer 18 formed at the interface between the n-type GL S layer 13 and the high-purity GaAs layer 14, excluding the influence of the surface level on the GaAs surface.
It is possible to provide a high-performance F'ET' using . In this FET configuration, the ohmic electrode V
Since it is formed on an i-n type GaAs layer, its contact resistance is smaller than that of an ohmic conductor formed on a GmlAs layer (see Figure 1), making it suitable for use as an active element in an IC. In this case, the on-resistance becomes smaller. In addition, this FIT is based on the electron concentration of the n-type GaAs layer on the surface,
Since the threshold voltage of the FET can be controlled depending on the thickness, it is possible to control whether the FET is normally on or normally off.
It is also possible to do ETK.
以上説明したように、この発明のFETは、表面がn型
のGaAsであり、これの下の高純度のG1As層に2
次元電子ガス層が形成される構造であるので、オーミッ
ク電極を形成し易く、またオン抵抗が小さくなるという
効果がある。As explained above, the FET of the present invention has an n-type GaAs surface, and a high-purity G1As layer below it.
Since the structure is such that a dimensional electron gas layer is formed, it is easy to form an ohmic electrode, and the on-resistance is reduced.
第1図は従来の変調ドーピングを用いたFBTO断面図
、第2図はGaAs層とGaAハ$層【第1図の場合と
逆転させたものの断面図、第3図にこの発明の一実施例
によるFETの断面図である。
1 、8 、11 ・・・半絶縁性GaAs基板、2,
10.14・・・高純度のG仏8層、3,9.13・・
・n型のGaAAAs層、4,16・・・ダート電極、
5.17−・・ソース電極、6,18・・・ドレイン電
極、7,18・・・2次元電子ガス層、12・・・ドー
ピングしないGaAAAs層、15・・・n型のGaA
s層。
特許出願人 沖電気工業株式会社
第1図
第3図Fig. 1 is a cross-sectional view of an FBTO using conventional modulation doping, Fig. 2 is a cross-sectional view of a GaAs layer and a GaA hard layer (reversed from the case in Fig. 1), and Fig. 3 is an embodiment of the present invention. FIG. 1, 8, 11...semi-insulating GaAs substrate, 2,
10.14...High purity G Buddha 8 layers, 3,9.13...
・N-type GaAAAs layer, 4,16... dart electrode,
5.17-... Source electrode, 6,18... Drain electrode, 7,18... Two-dimensional electron gas layer, 12... Undoped GaAAAs layer, 15... N-type GaA
s layer. Patent applicant: Oki Electric Industry Co., Ltd. Figure 1 Figure 3
Claims (1)
高純度のGaAB層を成長させた、ヘテロ界面を利用す
る電界効果型トランジスタにおいて、前記高純度のG■
8層の上にn型のGaAs層を形成し、このn型のGa
As層の上にダート、ソースおよびドレイン電極を形成
したことVW−特徴とする電界効果型トランジスタ。In a field-effect transistor using a heterointerface, in which a high-purity GaAB layer is grown on a GajkjAs layer doped with nfll, the high-purity G
An n-type GaAs layer is formed on top of the 8 layers, and this n-type GaAs layer is
VW - A field effect transistor characterized in that dirt, source and drain electrodes are formed on an As layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18907581A JPS5891681A (en) | 1981-11-27 | 1981-11-27 | Field-effect type transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18907581A JPS5891681A (en) | 1981-11-27 | 1981-11-27 | Field-effect type transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5891681A true JPS5891681A (en) | 1983-05-31 |
Family
ID=16234881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18907581A Pending JPS5891681A (en) | 1981-11-27 | 1981-11-27 | Field-effect type transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5891681A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61161773A (en) * | 1985-01-11 | 1986-07-22 | Matsushita Electric Ind Co Ltd | Field effect transistor |
JPS61280674A (en) * | 1985-06-06 | 1986-12-11 | Nec Corp | Semiconductor device |
WO1988008617A1 (en) * | 1987-04-20 | 1988-11-03 | Research Corporation Technologies, Inc. | Buried well dram |
US4821090A (en) * | 1983-12-05 | 1989-04-11 | Fujitsu Limited | Compound semiconductor integrated circuit device |
-
1981
- 1981-11-27 JP JP18907581A patent/JPS5891681A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4821090A (en) * | 1983-12-05 | 1989-04-11 | Fujitsu Limited | Compound semiconductor integrated circuit device |
JPS61161773A (en) * | 1985-01-11 | 1986-07-22 | Matsushita Electric Ind Co Ltd | Field effect transistor |
JPS61280674A (en) * | 1985-06-06 | 1986-12-11 | Nec Corp | Semiconductor device |
WO1988008617A1 (en) * | 1987-04-20 | 1988-11-03 | Research Corporation Technologies, Inc. | Buried well dram |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4748484A (en) | Heterojunction field effect transistor | |
JPH0783107B2 (en) | Field effect transistor | |
JPS5891681A (en) | Field-effect type transistor | |
JPH0328065B2 (en) | ||
JPH05275453A (en) | Junction fet and manufacture thereof | |
JP2500459B2 (en) | Heterojunction field effect transistor | |
JP2723901B2 (en) | Semiconductor device and its application circuit | |
JP3443034B2 (en) | Field effect transistor | |
JP2578745B2 (en) | Field effect transistor | |
JP2655594B2 (en) | Integrated semiconductor device | |
JPS6276565A (en) | Field-effect type transistor | |
JPH0715018A (en) | Field-effect transistor | |
JPH06252176A (en) | Transistor having high electron mobility | |
JPH0371774B2 (en) | ||
JP2695832B2 (en) | Heterojunction field effect transistor | |
JPH01257372A (en) | Insulated gate field effect transistor | |
JP2834172B2 (en) | Field effect transistor | |
JPH0156544B2 (en) | ||
JPS6255316B2 (en) | ||
JPH084141B2 (en) | Field effect transistor | |
JPH05102192A (en) | Field-effect transistor | |
JPS6367342B2 (en) | ||
JPH036834A (en) | Field-effect transistor | |
JPH0372637A (en) | Semiconductor device and its manufacture | |
JPH03192732A (en) | Iii-v group semiconductor field effect transistor |