JPS5891681A - Field-effect type transistor - Google Patents
Field-effect type transistorInfo
- Publication number
- JPS5891681A JPS5891681A JP18907581A JP18907581A JPS5891681A JP S5891681 A JPS5891681 A JP S5891681A JP 18907581 A JP18907581 A JP 18907581A JP 18907581 A JP18907581 A JP 18907581A JP S5891681 A JPS5891681 A JP S5891681A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- type
- onto
- gaas layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 35
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は化合物中導体ＩＣを構成する電界効果型トラ
ンジスタ（以下ＦＥＴという）に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor (hereinafter referred to as FET) constituting a compound conductor IC.
従来、超高速型の化合物半導体ＩＣＩ構成するＦＩＴと
して第１図に示すものがあった。このＦＥＴは、半絶縁
性のＧＪＬＡ１基板１の上に、分子ビームエピタキシャ
ル法などの成長を精密に制御することができるエピタキ
シャル法によって高純度のＧａＡｓ層２お工びｎ型にド
ーピングしたＧａＡｊＡｓ層３ｔ−成長させ、このＧｔ
＆＆Ａｓ層３の上にショットキｆ−）電１ｉ４．オーミ
ック電極のソース電極５お工びドレイン電極６會形成し
たものである。Conventionally, there has been an FIT configured as an ultra-high-speed compound semiconductor ICI as shown in FIG. This FET consists of a high-purity GaAs layer 2 formed on a semi-insulating GJLA1 substrate 1 by an epitaxial method that allows precise growth control such as molecular beam epitaxial method, and an n-type doped GaAjAs layer 3t. -Grow this Gt
Schottky f-) electrode 1i4. on top of &&As layer 3. The source electrode 5 and the drain electrode 6 are formed as ohmic electrodes.
このようなＧａＡｊＡｓ層３とＧＮ＆Ｉ ２のへテロ界
面に形成される２次元電子ガス層７を利用したＦＥＴは
、イオン化したドナの散乱が少なくなるために、７オノ
ン散乱が少なくなる低温で高性能な特性が得られる。こ
の場合、ｎ型のＧｔＡｊＡ＠層３の厚さに工□ｊｌ、Ｆ
ＥＴはノーマリオン型にもノーマリオン型にもなる。An FET that uses such a two-dimensional electron gas layer 7 formed at the hetero interface between the GaAjAs layer 3 and the GN&I 2 has high performance at low temperatures with less 7-onone scattering due to less scattering of ionized donors. characteristics can be obtained. In this case, the thickness of the n-type GtAjA@layer 3 is
ET can be either a normalion type or a normalion type.
また、１層のみの変調ドーピングについては、第１図に
示した構成の他に、第２図に示す工うにｎＪＪのＧａＡ
ｊＡｓ層と高純度のＧｉ人ａ層とを逆転させたものが考
えられる。すなわち、第２図に図すＦＥＴは、半絶縁性
ＧａＡｓ基板８の上に、ｎ型のＧａＡムＳ層９お工び高
純度のＧａＡｓ層１０’を成長させたものである。しか
し、この構成の場合には、高純度のＧａＡ１層１０層表
０単位のためにとのＧａＡｓ ７１０表面から空乏層が
拡が９．２次元電子ガス層が形成されない場合が多い。Regarding the modulation doping of only one layer, in addition to the structure shown in FIG. 1, the structure shown in FIG.
It is conceivable that the jAs layer and the high-purity Gi a layer are reversed. That is, the FET shown in FIG. 2 has an n-type GaAs layer 9 and a high-purity GaAs layer 10' grown on a semi-insulating GaAs substrate 8. However, in the case of this configuration, a depletion layer spreads from the surface of the GaAs 710 due to the 0 units on the top of the 10 layers of high-purity GaA, and a 9.2-dimensional electron gas layer is not formed in many cases.
この場合には、電子は移動度の低いＧａＡｌＡ１層９を
流れるために、変調ドーピングの利点が失なわれてしま
うという問題がある。In this case, there is a problem that the advantage of modulation doping is lost because electrons flow through the GaAlA1 layer 9 having low mobility.
この発明は、ｎ型のＧａＡｓ層内層の上に成長させた高
純度のＧａＡ１層の上に、さらＫ ｎ ＩＩのＧａＡｍ
層を形成することによシ、前述した表面単位の影響によ
る間Ｍ’を解決して、変調ドーピングによって形成され
る２次元電子ガス層を利用した高性能のｌｉ’ＥＴを実
現させることｔ目的としている。In this invention, K n II GaAm is further grown on a high purity GaAl layer grown on an n-type GaAs inner layer.
The purpose is to solve the above-mentioned surface unit effect of M' by forming a layer, and to realize high-performance LI'ET using a two-dimensional electron gas layer formed by modulation doping. It is said that
以下、この発明の一実施例につき第３図を参照して詳述
する。この実施例のＦＥＴｈ、半絶縁性Ｇ−・３基板１
１上に、ドーピングしないＧａＡＩＡＳ層１２をこれよ
シ上の層の電子が拡散して米ないように成長させ、この
ＧａＡｔＡ易層１２の上にｎ型にドーピングしたＧａＡ
ＡＡｓ層１３に成長させ、このＧａＡムＳ層１３の上に
高純度のＧａＡｓ層１４を成長させ、さらに高純度のＧ
ａＡｓ層１４′の上にｎ型にドーピングしたＧａＡｓ層
１５’ｔｇ長させる。このｎ型のＧ麩Ｓ層１５の上にシ
ョットキｆ−）電極１６、オーミック電極のソース電極
１７おＬびＰレイン電極１８を形成する４のである。そ
して、前記ｎ型のＧａＡｓ層１５がないものでは、 Ｇ
ａＡｓの表面単位による空乏層の拡がシによって高純度
のＧａＡｓ層１４とｎＷｉのＧａＡｔＡｓ層１３の界面
に２次元電子ガス層が形成されにくいが、ｎ型のＧａＡ
ｓ層１５があるこの実施例によるＦＥＴの場合には、ｎ
型のＧａＡｓ層１５に空乏層が拡がるのを抑えることが
でき、このために、高純度ＯＧａＡｓ層１４とｎ型のＧ
ａＡＡ＆ｍ層１３のへテロ界面に２次元電子ガス層１８
が形成される。また、ｎ型のＧａＡｓ層１５の電子濃度
や厚さを制御することによって、このＰＥＴはノーマリ
オフ型にすることもノーマリオフ型にすることもできる
。さらに、ＦＥＴとして動作する時に、ｎ型のＧｔＡｓ
層１ｓ全１ｓｔ電子ると、このｎｆｉのＧａＡｓ層内の
イオン化し友ドナの散乱があるために、２次元電子ガス
層１８の高移動度であることによる有利性が少なくなる
が、ＦＥＴの動作範囲としてダート電極１６の下のｎ型
のＧａＡｓ層１５が常に完全に空乏層になっているよう
な条件にすれば、前記有利性が損なわれることはない。Hereinafter, one embodiment of the present invention will be described in detail with reference to FIG. FETh of this example, semi-insulating G-3 substrate 1
1, an undoped GaAIAS layer 12 is grown in such a way that electrons from the layer above are not diffused and do not form, and on this GaAtA layer 12, an n-type doped GaAI
A high-purity GaAs layer 14 is grown on the GaAs layer 13, and a high-purity GaAs layer 14 is grown on the GaAs layer 13.
An n-type doped GaAs layer 15'tg is formed on the aAs layer 14'. On this n-type G-S layer 15, a Schottky f-) electrode 16, an ohmic source electrode 17, and a P-rain electrode 18 are formed. In the case where the n-type GaAs layer 15 is not present, G
It is difficult to form a two-dimensional electron gas layer at the interface between the high-purity GaAs layer 14 and the nWi GaAtAs layer 13 due to the expansion of the depletion layer in units of the aAs surface.
For the FET according to this embodiment with s-layer 15, n
It is possible to suppress the expansion of the depletion layer in the type GaAs layer 15, and for this reason, the high purity OGaAs layer 14 and the n-type GaAs layer 15 can be prevented from expanding.
A two-dimensional electron gas layer 18 at the hetero interface of the aAA&m layer 13
is formed. Further, by controlling the electron concentration and thickness of the n-type GaAs layer 15, this PET can be made into a normally-off type or a normally-off type. Furthermore, when operating as a FET, n-type GtAs
When all 1st electrons in the layer 1s are used, the advantage of the high mobility of the two-dimensional electron gas layer 18 is reduced due to the scattering of ionized friends in the GaAs layer of this nfi, but the operation of the FET is As long as the conditions are such that the n-type GaAs layer 15 under the dirt electrode 16 is always completely depleted, the above advantages will not be impaired.
前述したようにこの実施例のＦＥＴは、高純度のＧａＡ
ｓ層１４の上にｎ型のＧａＡｓ層１５ｔ−成長させて、
これらの上にダート、ソースおよびドレイン電極１７．
１６および１８會形成することにエフ、ＧａＡｓ表面の
表面準位の影響を除き、ｎ型のＧＬ仏ｓ層１３と高純度
のＧａＡｓ層１４の界面にできる２次元電子ガス層１８
を利用した高性能のＦ’ＥＴ ’を楊供することができ
る。そして、このＦＥＴの構成では、オーミック電極Ｖ
ｉ−ｎ型のＧａＡｓ層の上に形成しであるので、その接
触抵践はＧｍｌＡｓ層の上にオーミック電＆を形成した
もの（第１図参照）に比べて小さく、ＩＣの能動素子と
して使用した場合に、そのオン抵抗が小さくなる。また
、このＦＩＴは、表面のｎ型のＧａＡｓ層の電子濃度、
厚さによってＦＥＴのスレッシュホルド電圧を制御でき
るので、ノーマリオン型、ノーマリオフ型のどちらのＦ
ＥＴＫすることも可能である。As mentioned above, the FET of this example is made of high-purity GaA
An n-type GaAs layer 15t is grown on the s-layer 14,
On top of these are dirt, source and drain electrodes 17.
16 and 18, the two-dimensional electron gas layer 18 formed at the interface between the n-type GL S layer 13 and the high-purity GaAs layer 14, excluding the influence of the surface level on the GaAs surface.
It is possible to provide a high-performance F'ET' using . In this FET configuration, the ohmic electrode V
Since it is formed on an i-n type GaAs layer, its contact resistance is smaller than that of an ohmic conductor formed on a GmlAs layer (see Figure 1), making it suitable for use as an active element in an IC. In this case, the on-resistance becomes smaller. In addition, this FIT is based on the electron concentration of the n-type GaAs layer on the surface,
Since the threshold voltage of the FET can be controlled depending on the thickness, it is possible to control whether the FET is normally on or normally off.
It is also possible to do ETK.
以上説明したように、この発明のＦＥＴは、表面がｎ型
のＧａＡｓであり、これの下の高純度のＧ１Ａｓ層に２
次元電子ガス層が形成される構造であるので、オーミッ
ク電極を形成し易く、またオン抵抗が小さくなるという
効果がある。As explained above, the FET of the present invention has an n-type GaAs surface, and a high-purity G1As layer below it.
Since the structure is such that a dimensional electron gas layer is formed, it is easy to form an ohmic electrode, and the on-resistance is reduced.
第１図は従来の変調ドーピングを用いたＦＢＴＯ断面図
、第２図はＧａＡｓ層とＧａＡハ＄層【第１図の場合と
逆転させたものの断面図、第３図にこの発明の一実施例
によるＦＥＴの断面図である。
１ 、８ 、１１ ・・・半絶縁性ＧａＡｓ基板、２，
１０．１４・・・高純度のＧ仏８層、３，９．１３・・
・ｎ型のＧａＡＡＡｓ層、４，１６・・・ダート電極、
５．１７−・・ソース電極、６，１８・・・ドレイン電
極、７，１８・・・２次元電子ガス層、１２・・・ドー
ピングしないＧａＡＡＡｓ層、１５・・・ｎ型のＧａＡ
ｓ層。
特許出願人 沖電気工業株式会社
第１図
第３図Fig. 1 is a cross-sectional view of an FBTO using conventional modulation doping, Fig. 2 is a cross-sectional view of a GaAs layer and a GaA hard layer (reversed from the case in Fig. 1), and Fig. 3 is an embodiment of the present invention. FIG. 1, 8, 11...semi-insulating GaAs substrate, 2,
10.14...High purity G Buddha 8 layers, 3,9.13...
・N-type GaAAAs layer, 4,16... dart electrode,
5.17-... Source electrode, 6,18... Drain electrode, 7,18... Two-dimensional electron gas layer, 12... Undoped GaAAAs layer, 15... N-type GaA
s layer. Patent applicant: Oki Electric Industry Co., Ltd. Figure 1 Figure 3
Claims (1)
高純度のＧａＡＢ層を成長させた、ヘテロ界面を利用す
る電界効果型トランジスタにおいて、前記高純度のＧ■
８層の上にｎ型のＧａＡｓ層を形成し、このｎ型のＧａ
Ａｓ層の上にダート、ソースおよびドレイン電極を形成
したことＶＷ−特徴とする電界効果型トランジスタ。In a field-effect transistor using a heterointerface, in which a high-purity GaAB layer is grown on a GajkjAs layer doped with nfll, the high-purity G
An n-type GaAs layer is formed on top of the 8 layers, and this n-type GaAs layer is
VW - A field effect transistor characterized in that dirt, source and drain electrodes are formed on an As layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18907581A JPS5891681A (en) | 1981-11-27 | 1981-11-27 | Field-effect type transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18907581A JPS5891681A (en) | 1981-11-27 | 1981-11-27 | Field-effect type transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5891681A true JPS5891681A (en) | 1983-05-31 |
Family
ID=16234881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18907581A Pending JPS5891681A (en) | 1981-11-27 | 1981-11-27 | Field-effect type transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5891681A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61161773A (en) * | 1985-01-11 | 1986-07-22 | Matsushita Electric Ind Co Ltd | Field effect transistor |
| JPS61280674A (en) * | 1985-06-06 | 1986-12-11 | Nec Corp | Semiconductor device |
| WO1988008617A1 (en) * | 1987-04-20 | 1988-11-03 | Research Corporation Technologies, Inc. | Buried well dram |
| US4821090A (en) * | 1983-12-05 | 1989-04-11 | Fujitsu Limited | Compound semiconductor integrated circuit device |
-
1981
- 1981-11-27 JP JP18907581A patent/JPS5891681A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4821090A (en) * | 1983-12-05 | 1989-04-11 | Fujitsu Limited | Compound semiconductor integrated circuit device |
| JPS61161773A (en) * | 1985-01-11 | 1986-07-22 | Matsushita Electric Ind Co Ltd | Field effect transistor |
| JPS61280674A (en) * | 1985-06-06 | 1986-12-11 | Nec Corp | Semiconductor device |
| WO1988008617A1 (en) * | 1987-04-20 | 1988-11-03 | Research Corporation Technologies, Inc. | Buried well dram |
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