JPS5890737A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5890737A
JPS5890737A JP18878381A JP18878381A JPS5890737A JP S5890737 A JPS5890737 A JP S5890737A JP 18878381 A JP18878381 A JP 18878381A JP 18878381 A JP18878381 A JP 18878381A JP S5890737 A JPS5890737 A JP S5890737A
Authority
JP
Japan
Prior art keywords
wiring
resistor
film
thin film
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18878381A
Other languages
Japanese (ja)
Inventor
Koichiro Misaki
見崎 光一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP18878381A priority Critical patent/JPS5890737A/en
Publication of JPS5890737A publication Critical patent/JPS5890737A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To realize crossing of a thin film resistor and an Al wiring by providing the first kind of metal resistor and the first metal wiring on a semiconductor substrate through an insulation film, providing the second metal wiring which is in contact with the first wiring through the second insulation film and covering it with the third insulation film. CONSTITUTION:A Ni-Cr thin film resistor 203 is formed on the thermally oxide film 202 of the N type Si substrate 201 forming the pn junction, it is connected to an element by an Al wiring 204, an interlayer oxide film 205 is formed by the vapor growth method in such a thickness as corresponding to a voltage used. A window 207 is opened on the Al wiring 204 and the second Al wiring 208 is generated. At this time, the Al wiring 208 crosses the Ni-Cr resistor 203. Finally, the surface is covered with a surface protection film 205. According to this structure, a thin film resistor and the second Al wiring layer cross and a degree of freedom of mask layout can be increased.

Description

【発明の詳細な説明】 本発明は半導体装置に係り、籍に薄膜抵抗が設げらnf
c衿導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a thin film resistor is provided in a semiconductor device.
This relates to a c-collar conductor device.

便来、4挨抵抗tl−乗積tO1路に用いる場合、第1
図の様な断面図の傳造が一般的であった。第1図におい
て、101は半4体基板、102は手導座漬板上に形成
ざnた熱酸化膜、103は金媚七言んだ擾襖批抗、10
4は薄膜抵抗と他の^子とを結ぶ為のアルミニウム配−
−105は衣N保護の→気相成長酸化膜でめる。CQ)
様な4遺においては、薄膜抵抗104と同一平面上にめ
るアルミ配媚は砥仇両署のアルミ電極以外の部分で薄膜
抵抗104と交叉することは出来す、この点が従来の拡
敢砥杭に比べると欠点であり、マスクレイアウト上のI
I′lJ約ともなっていた。
For convenience, when used in the 4th resistance tl - product tO1 path, the first
Denzo with cross-sectional views as shown in the figure were common. In FIG. 1, 101 is a half-quad board, 102 is a rough thermal oxide film formed on the guide seat plate, 103 is a diaphragm plate, and 10
4 is an aluminum wire for connecting the thin film resistor to other wires.
-105 is coated with a → vapor phase grown oxide film that protects N. CQ)
In such a case, the aluminum electrode placed on the same plane as the thin film resistor 104 can intersect with the thin film resistor 104 at a part other than the aluminum electrodes on both sides.This point is an improvement over the conventional method. This is a drawback compared to a grinding stake, and I
It was also about I'lJ.

本発明は、上記の本計な制約t−填り除き、薄膜抵抗と
アルミニウム配線とが交叉し得る半導体装置を提供せん
とす4・ものである。
The present invention aims to overcome the above-mentioned serious constraints and provide a semiconductor device in which thin film resistors and aluminum wiring can intersect.

本発明による半導体装mは、−411t型の半導体基板
と、該半導体基板上に形成さnた第1.の絶縁゛膜と、
該第1の絶縁膜上に形成さnた少なくとも一櫨頌の金I
t4J:v成る抵抗体と、前記#!lの絶縁膜上にフl
fj成さiした第1の金捕配襟と、前記第1の1d縁I
QLに形成さγした第2の絶縁膜と前記第lの雀@閂己
嫌上に設げら扛た目?Jmci第2の絶縁膜の窓と、イ
4を、filLで前記第1の金属配−と接するよう形1
Ji5さfした弔2り曾−配線と、前記第2の絶縁膜上
にル成→γした第3の伯嫌模とから成ることを特徴とす
る。
A semiconductor device m according to the present invention includes a -411t type semiconductor substrate and a first semiconductor substrate formed on the semiconductor substrate. an insulating film of
At least one layer of gold I formed on the first insulating film.
A resistor consisting of t4J:v and the #! On the insulating film of l
The first gold collar made of fj and the first 1d edge I
The second insulating film formed on the QL and the pattern formed on the first sparrow? Jmci the window of the second insulating film and A4 are shaped so as to contact the first metal wiring at filL.
It is characterized in that it consists of a wiring line formed by JI5F and a third pattern formed on the second insulating film.

以下、図・[I]?用いて本兄明の実施pHに付き、説
明する。
Below is the figure/[I]? The practical pH of the present invention will be explained below.

本完明の央・虐列を第2図(a)〜(dlに示す。PI
N接合素子(図示ゼず)の形成さ[したN微半導体承板
201に熱酸化にLり熱醸化膜202を形成し、この熱
酸化4201上に一例としてへi−t;rよりIjlL
る博嗅ケ触層し、匠米り写疼貢刻法にエリl\i−シ[
砥−fc203’を形成する(第2図(a))。
The central and brutal lines of Honkanmei are shown in Figure 2 (a) to (dl). PI
After forming the N junction element (not shown), a thermally fermented film 202 is formed by thermal oxidation on the N microsemiconductor base plate 201, and as an example, the thermally fermented film 202 is
The tactile layer was created by the master craftsman, and the technique of copying and engraving was performed by the master craftsman.
A grindstone fc203' is formed (FIG. 2(a)).

人VC1?1−Crぶ抗203の電極配線として、父餌
のPi′11≠合本子を接続する配線(図示せず)とし
ての41着アルミニウム配線204會形成し、社に全回
に気相成艮膚1川酸化膜206を1更用亀圧VCIl!
した==にノ験成する(第2図(b))。
As the electrode wiring of the resistor 203 for the VC1? One change of oxidized film 206 on the completed skin and turtle pressure VCIl!
The result is ``(Figure 2(b))''.

第1・−アルミニウム配@204上の1間酸化膜の42
07全形成し、この悪を1良して第11曽アルミニウム
配線に按じかつ1−間酸化d205上に泣1tする椋第
2アルミニウム配硼208’に形成する。
1st - 42 of the 1st oxide film on the aluminum wiring @204
07 is completely formed, this defect is applied to the 11th aluminum wiring, and the second aluminum wiring 208' is formed on the oxidized d205.

この時アルミニウム配7208はlN1−er抵仇20
3上にてへi−1;r屯抗203とクロスすることがで
きる。最後に、気相成長1化膜を全面に成長させ、次間
保護膜205とする(第2図(d))。
At this time, the aluminum wiring 7208 has a lN1-er resistance of 20
3 can be crossed with the i-1; r tunnel 203. Finally, a vapor-phase monolithic film is grown over the entire surface to form an interlayer protective film 205 (FIG. 2(d)).

同、渠2図(d)は第2に)tc)の 面図の入−Xt
の切断域に宿った。!fr@図である。
In the same way, culvert 2 (d) is secondly) tc) -Xt
It resided in the amputation area. ! fr@ diagram.

以上の様に、本発明によnは、薄膜抵抗とアルミ配@(
二層目)の交叉が可能で、マスクレイアウト上の自由度
が増すことになる。
As described above, according to the present invention, n is a thin film resistor and an aluminum wiring (
The second layer) can be crossed over, increasing the degree of freedom in mask layout.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は薄膜抵抗を半導体基板に用いた場合の従来のT
44断面図、第2図(a)〜(d)は本元明実厖例にj
;b薄膜抵抗の構造を製造順に示したもので、第2図(
d)は被縫断面図で#!2図(C)はその 面図である
。 なお図において、101*201・・・・・・半導体裾
板、1(+2+202・・・・・・熱酸化膜、103+
203・・・・・・lN1−Cr北抗、104う204
・・°・°°アルミ3ウム配・+151(第一1−目)
、105,205・・・・・・力/<−酸化膜、’20
6・・・・・・1曽旧■獲化膜、 207・・・・・・
1−曲便化擬の4.208・・・・・・第2J曽目アル
ミニウム自己−壁、  マ゛ ある。 め 1図 篤 Z図
Figure 1 shows the conventional T when a thin film resistor is used on a semiconductor substrate.
44 sectional views, Figures 2 (a) to (d) are based on the original Ming actual example.
;b The structure of the thin film resistor is shown in the order of manufacture, as shown in Figure 2 (
d) is #! in the cross-sectional view of the sewing material. Figure 2 (C) is its top view. In the figure, 101*201... Semiconductor base plate, 1(+2+202... Thermal oxide film, 103+
203...lN1-Cr Hokuhan, 104 U204
・・°・°°Aluminum 3um arrangement・+151 (1st 1-st)
, 105,205...force/<-oxide film, '20
6・・・・・・1 Zeng old■prey membrane, 207・・・・・・
1 - Contoured pseudo 4.208... 2nd J Somme Aluminum Self - Wall, my. Figure 1 Atsushi Figure Z

Claims (1)

【特許請求の範囲】[Claims] 一44型の半4庫唸板と、核半4体漬5板上に形成さn
たiglの氾−膜と該第lの絶縁膜上に形成さrL7’
c少なくとも一4類の金I4より成る抵抗体と萌iL第
1v艷嫌膜上に形成さ扛た第lの金椙配−と、前ad第
Iの杷−膜上に形成さfL次第2の杷−14と、前記第
1の金鴎配機上に設けらnた前記第2の絶縁膜の4と、
該g紫通して前記第81の金属配線と咲するよう形成さ
扛た第2の金礪配被と、’+11 ad第2の絶縁膜上
に形成ざnた第3の東縁膜とrゴむことを待鐵とする半
導体装置。
- Formed on a 44-type semi-four-barrel plate and a nuclear half-four plate and a five-plate n
rL7' formed on the flood film of Igl and the first insulating film
c A resistor made of at least Class 14 gold I4, a first metal layer formed on the first layer, and a second layer formed on the second layer. 4 of the second insulating film provided on the first gold plater,
a second metal layer formed on the 81st metal wiring through the g; a third eastern edge film formed on the second insulating film; Semiconductor equipment that relies on solid state.
JP18878381A 1981-11-25 1981-11-25 Semiconductor device Pending JPS5890737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18878381A JPS5890737A (en) 1981-11-25 1981-11-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18878381A JPS5890737A (en) 1981-11-25 1981-11-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5890737A true JPS5890737A (en) 1983-05-30

Family

ID=16229709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18878381A Pending JPS5890737A (en) 1981-11-25 1981-11-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5890737A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242792B1 (en) 1996-07-02 2001-06-05 Denso Corporation Semiconductor device having oblique portion as reflection
US6274452B1 (en) 1996-11-06 2001-08-14 Denso Corporation Semiconductor device having multilayer interconnection structure and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242792B1 (en) 1996-07-02 2001-06-05 Denso Corporation Semiconductor device having oblique portion as reflection
US6274452B1 (en) 1996-11-06 2001-08-14 Denso Corporation Semiconductor device having multilayer interconnection structure and method for manufacturing the same

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