JPS5889937U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS5889937U
JPS5889937U JP1981185242U JP18524281U JPS5889937U JP S5889937 U JPS5889937 U JP S5889937U JP 1981185242 U JP1981185242 U JP 1981185242U JP 18524281 U JP18524281 U JP 18524281U JP S5889937 U JPS5889937 U JP S5889937U
Authority
JP
Japan
Prior art keywords
electrode
semiconductor
semiconductor equipment
external connection
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1981185242U
Other languages
Japanese (ja)
Other versions
JPS5943733Y2 (en
Inventor
三宅 正保
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP1981185242U priority Critical patent/JPS5943733Y2/en
Publication of JPS5889937U publication Critical patent/JPS5889937U/en
Application granted granted Critical
Publication of JPS5943733Y2 publication Critical patent/JPS5943733Y2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図A、 Bは従来の半導体素子の特性検査を説明す
るための半導体ウェーハの平面図、及び要部拡大平面図
、第2図はケルビン接続を説明する原理図、第3図A、
 Bはケルビン接続を用いた従来手段による特性測定を
説明する図、第4図はそれの半導体ウェーハにおける接
続状態を示す側面図、第5図はウェーハと接触するチャ
ックトップの上面図、第6図はケルビン接続を用いた従
来手段で、トランジスタのVCE(SAT)を測定した
値が、第5図X−X線に沿う横方向抵抗の変動に対して
変化する状態を示す特性曲線図、第7図は本考案の一実
施例を示す半導体素子の拡大上面図、第8図は第7図の
半導体素子にケルビン接続を行う場合の検針の当接状態
を示す上面図である。 1・・・・・・半導体ウェーハ、2・・・・・・半導体
素子、5・・・・・・チャックトップ、7・・・・・・
センシングバッド、E・・・・・・半導体素子表面の電
極(エミッタ)、B・・・・・・半導体素子表面の電極
(ベース)、C・・・・・・半導体素子裏面の電極(コ
レクタ)、S・・・・・・センシング、F・・・・・・
フォーシング、T・・・・・・テスター。
FIGS. 1A and 1B are a plan view of a semiconductor wafer and an enlarged plan view of essential parts to explain conventional characteristic testing of semiconductor elements, FIG. 2 is a principle diagram explaining Kelvin connection, and FIGS. 3A and 3B are
B is a diagram explaining characteristic measurement by conventional means using Kelvin connection, FIG. 4 is a side view showing the connection state on a semiconductor wafer, FIG. 5 is a top view of the chuck top in contact with the wafer, and FIG. 6 7 is a characteristic curve diagram showing how the measured VCE (SAT) of a transistor changes with respect to fluctuations in lateral resistance along line X-X in FIG. The figure is an enlarged top view of a semiconductor device showing an embodiment of the present invention, and FIG. 8 is a top view showing the contact state of a meter when a Kelvin connection is made to the semiconductor device of FIG. 7. 1...Semiconductor wafer, 2...Semiconductor element, 5...Chuck top, 7...
Sensing pad, E... Electrode on the surface of the semiconductor element (emitter), B... Electrode on the surface of the semiconductor element (base), C... Electrode on the back surface of the semiconductor element (collector) , S...Sensing, F...
Forcing, T...Tester.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体ウェーハ上の半導体素子表面に外部接続用の電極
が設けられるとともに半導体ウエーノ\裏面にも外部接
続用の電極を設けたものにおいて、裏面の外部接続用の
電極と同一の電極を表面側にもセンシングパッドとして
設けたことを特徴とする半導体装置。
In a semiconductor wafer in which an electrode for external connection is provided on the surface of the semiconductor element and also an electrode for external connection is provided on the back side of the semiconductor wafer, the same electrode as the electrode for external connection on the back side is also provided on the front side. A semiconductor device characterized by being provided as a sensing pad.
JP1981185242U 1981-12-12 1981-12-12 semiconductor equipment Expired JPS5943733Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981185242U JPS5943733Y2 (en) 1981-12-12 1981-12-12 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981185242U JPS5943733Y2 (en) 1981-12-12 1981-12-12 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS5889937U true JPS5889937U (en) 1983-06-17
JPS5943733Y2 JPS5943733Y2 (en) 1984-12-26

Family

ID=29986117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981185242U Expired JPS5943733Y2 (en) 1981-12-12 1981-12-12 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5943733Y2 (en)

Also Published As

Publication number Publication date
JPS5943733Y2 (en) 1984-12-26

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