JPS5888417U - Transistor amplifier bias circuit - Google Patents
Transistor amplifier bias circuitInfo
- Publication number
- JPS5888417U JPS5888417U JP14019482U JP14019482U JPS5888417U JP S5888417 U JPS5888417 U JP S5888417U JP 14019482 U JP14019482 U JP 14019482U JP 14019482 U JP14019482 U JP 14019482U JP S5888417 U JPS5888417 U JP S5888417U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- bias circuit
- feedback impedance
- collector
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は、従来のバイアス回路の1例を示す原理図、第
2図は第1図のバイアス回路を用いた場合のコレクタ電
流と入出力の特性を示す図、第3図は本考案のバイアス
回路の1実施例を示す原理図、第4図は第3図のバイア
ス回路の実際使用状態を示す回路図、第5図aないしC
は帰還用インピーダンスを示す図、第6図ないし第8図
は本考案のバイアス回路を使用した場合のコレクタ電流
と入出力の特性を示す図である。 、TR□・・・
増幅用トランジスタ、R□、R2・・・分圧抵抗、R3
・・・コレクタ抵抗、P□・・・入力端子、R2・・・
出力端子、1・・・入力端子、2.3・・・分圧抵抗、
4・・・ ゛帰還用トランジスタ、5・・・増幅用ト
ランジスタ、6・・・帰還用インピーダンス、7・・・
コレクタ抵抗、−8・・・出力端子、9・・・入力整合
回路、10・・・ベース負荷、11・・・コレクタ負荷
、12・・・出力整合回路、13.14・・・バイパス
コンデンサ、21.24・・・抵抗、22.23・・・
定電圧素子。Fig. 1 is a principle diagram showing an example of a conventional bias circuit, Fig. 2 is a diagram showing the collector current and input/output characteristics when the bias circuit of Fig. 1 is used, and Fig. 3 is a diagram showing the characteristics of the collector current and input/output when the bias circuit of Fig. 1 is used. A principle diagram showing one embodiment of the bias circuit, FIG. 4 is a circuit diagram showing the actual usage state of the bias circuit of FIG. 3, and FIGS. 5 a to C.
6 is a diagram showing feedback impedance, and FIGS. 6 to 8 are diagrams showing collector current and input/output characteristics when the bias circuit of the present invention is used. , TR□...
Amplification transistor, R□, R2...Voltage dividing resistor, R3
...Collector resistance, P□...Input terminal, R2...
Output terminal, 1... Input terminal, 2.3... Voltage dividing resistor,
4... Feedback transistor, 5... Amplification transistor, 6... Feedback impedance, 7...
Collector resistance, -8... Output terminal, 9... Input matching circuit, 10... Base load, 11... Collector load, 12... Output matching circuit, 13.14... Bypass capacitor, 21.24...Resistance, 22.23...
Constant voltage element.
Claims (1)
用トランジスタのコレクタ負荷のコールドエンドと電源
とを接続するコレクタ抵抗、電源と接地間に接続された
2個の直列抵抗からなる分圧抵抗、エミッタを前記増幅
用トランジスタのコレクタ負荷のコールドエンドに接続
され、ベースを前記分圧抵抗の中間接続点に接続され、
コレクタを帰還用インピーダンスを経て前記増幅用トラ
ンジスタのベース負荷のコールドエンドに接続された前
記増幅用トランジスタと逆極性のトランジスタからなり
、前記コレクタ負荷のコールドエンドと前記分圧抵抗の
中間接続点との間の電圧変化に応じて前記増幅用トラン
ジスタのベース電流を帰還用インピーダンスを介して制
御する帰還用トランジスタとを具えたことを特徴とする
トランジスタ増幅器のバイアス回路。 2 前記帰還用インピーダンスが抵抗であることを特徴
とする実用新案登録請求の範囲第1項記載のトランジス
タ増幅器のバイアス回路。 3 前記帰還用インピーダンスが定電圧素子であること
を特徴とする実用新案登録請求の範囲第1項記載のトラ
ンジスタ増幅器のバイアス回路。 4 前記帰還用インピーダンスが定電圧素子と抵抗の直
列回路であることを特徴とする実用新案登録請求の範囲
第1項記載のトランジスタ増幅器のバイアス回路。[Claims for Utility Model Registration] 1. In an emitter-grounded transistor amplifier, a collector resistor connects the cold end of the collector load of the amplifying transistor to the power supply, and a component consisting of two series resistors connected between the power supply and the ground. a piezoresistor, an emitter connected to the cold end of the collector load of the amplifying transistor, and a base connected to the intermediate connection point of the voltage dividing resistor;
It consists of a transistor of opposite polarity to the amplifying transistor whose collector is connected to the cold end of the base load of the amplifying transistor via a feedback impedance, and the cold end of the collector load is connected to the intermediate connection point of the voltage dividing resistor. 1. A bias circuit for a transistor amplifier, comprising: a feedback transistor that controls the base current of the amplification transistor via a feedback impedance in accordance with a voltage change between the amplifier transistors. 2. The bias circuit for a transistor amplifier according to claim 1, wherein the feedback impedance is a resistor. 3. The bias circuit for a transistor amplifier according to claim 1, wherein the feedback impedance is a constant voltage element. 4. The bias circuit for a transistor amplifier according to claim 1, wherein the feedback impedance is a series circuit of a constant voltage element and a resistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14019482U JPS5838647Y2 (en) | 1982-09-16 | 1982-09-16 | Transistor amplifier bias circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14019482U JPS5838647Y2 (en) | 1982-09-16 | 1982-09-16 | Transistor amplifier bias circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5888417U true JPS5888417U (en) | 1983-06-15 |
JPS5838647Y2 JPS5838647Y2 (en) | 1983-09-01 |
Family
ID=29933366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14019482U Expired JPS5838647Y2 (en) | 1982-09-16 | 1982-09-16 | Transistor amplifier bias circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5838647Y2 (en) |
-
1982
- 1982-09-16 JP JP14019482U patent/JPS5838647Y2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5838647Y2 (en) | 1983-09-01 |
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