JPS5885528A - Forming method of electrode for semiconductor device - Google Patents
Forming method of electrode for semiconductor deviceInfo
- Publication number
- JPS5885528A JPS5885528A JP18297881A JP18297881A JPS5885528A JP S5885528 A JPS5885528 A JP S5885528A JP 18297881 A JP18297881 A JP 18297881A JP 18297881 A JP18297881 A JP 18297881A JP S5885528 A JPS5885528 A JP S5885528A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- region
- hole
- type
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000013078 crystal Substances 0.000 claims abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- 238000001704 evaporation Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 3
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 241000218645 Cedrus Species 0.000 description 1
- 235000011511 Diospyros Nutrition 0.000 description 1
- 244000236655 Diospyros kaki Species 0.000 description 1
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 239000000806 elastomer Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は十淘体装置用電柿Ｉの形成方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a persimmon I for a ten-body device.
従来半導体装置の電極（ゴ、半導体基板表面に酸化膜８
１の絶縁層を形成し、この絶縁層の上にアルミニウム等
の導電層を蒸着等により形ｂν１し、この導ｔｌＬ層が
絶縁層しこ設けられた窓を介して基板表面上１こ接動す
るようにして、半導体基板表面と導電層とのオーミック
接触を得ていた。Electrodes of conventional semiconductor devices (eg, oxide film 8 on the surface of the semiconductor substrate)
A conductive layer such as aluminum is formed on this insulating layer by vapor deposition or the like, and this conductive TL layer is brought into contact with the substrate surface through a window provided in the insulating layer. In this way, ohmic contact between the semiconductor substrate surface and the conductive layer was obtained.
しかし半導体装置の領域９こは半導体基板表面からある
程度の深さの所をこ位置して、基板前ｍ口こ達していな
いものがある。このような表面下の領域９こは基、板表
面から電極を直接接続することができす、このことが従
来半導体装ｆｆｔの型動特性の但下□を招いていた。However, some regions of the semiconductor device are located at a certain depth from the surface of the semiconductor substrate and do not reach the front surface of the substrate. In such a subsurface region 9, an electrode can be directly connected from the surface of the substrate or the plate, and this has conventionally led to poor type dynamic characteristics of semiconductor devices fft.
本発明の目的（、゛Ｉ上述した欠めを除去し、半導体装
圧ｔの７１４気％ ’ｔ＜トを向上さぜることのできる
半導体装置用電極の形成方法を提供することシこある。The object of the present invention is to provide a method for forming an electrode for a semiconductor device that can eliminate the above-mentioned defects and improve the semiconductor packaging pressure t by 714%. .
本発明は午涛体装簡が形成ざねる１”導体基板り面から
該基板Ｗ Ｉｌｌ下の所定深さに位置する領域【こ向け
て異方性エツチングを行ない、これ（こより形成された
エツチング面上Ｅこ電極屑を設けることを特徴とする半
導体装置用電極の形成方法にある。In the present invention, anisotropic etching is performed toward a region located at a predetermined depth below the 1" conductor substrate surface where the carrier structure is formed, and the etching formed from this A method for forming an electrode for a semiconductor device, characterized in that electrode scraps are provided on a surface.
図面【こつき本発明を説明する。Drawings [Explanation of the present invention]
第１図は従来の電ｔ！！Ｉ／構造をηするＮＰＮ形のバ
イ１ホーラトランジスタの一例を示す断面図であり、。Figure 1 shows the conventional electric t! ! FIG. 3 is a cross-sectional view showing an example of an NPN bi-1 Hola transistor having an I/structure.
ここにｌθけＰ形基板、／２けＮ形拡散領域をもって形
成するｆｉｌｌ込み胎、／ぐはコレクタ領域を成すＮ形
エピタキシャル領域、１６は高濃度Ｎ影領域、７ｇけＰ
形ベース拡散領域、〃はＮ形エミッタ拡散領域、〃は絶
縁層、２グはエミッタ電極、左はベースπＬ極、Ｉはコ
レクタ電極であ４ノ。Here, lθ is a P-type substrate, /2 is a fill region formed with an N-type diffusion region, / is an N-type epitaxial region forming a collector region, 16 is a high concentration N shadow region, and 7g is a P-type substrate.
type base diffusion region, 〃 is the N type emitter diffusion region, 〃 is the insulating layer, 2g is the emitter electrode, the left is the base πL pole, and I is the collector electrode.
ｌυｒＦＭのトランジスタＦこおいては、コレクタシリ
ーズ抵抗を低泗させるため（こ、坪込み層１２を股ケ１
１ており、本来コレクタ電極ｊはこの埋込み層１２に直
接接続するのが債ましいが、コレクタ電狗、Ｉは半導体
基板の表面と接峡するので、叩込み層１２とは直ｆｉ−
’ｒｘ （，４することはできない。そこで表面コレク
タ′１１）極ｊを取出す部分〔こ高濃度領域／６を拡散
波“術を用いて形成して、コレクタシリーズ抵抗の低力
、も１化を図っていた。In the transistor F of lυrFM, in order to reduce the collector series resistance (in this case, the depression layer 12 is
1, and originally it is desirable to connect the collector electrode j directly to this buried layer 12, but since the collector electrode I is in contact with the surface of the semiconductor substrate, it should be directly connected to the buried layer 12.
'rx (, 4) Therefore, the part where the surface collector '11) pole j is taken out [this high concentration region/6] is formed using the diffusion wave technique, and the low force of the collector series resistance is also reduced to 1. was aiming for
しかしコレクタとして作用する主要部分は埋込み痩／２
とベース領域１ｇ＆こ挾まれた領域であり、主なコレク
タＴｒｉ流は埋込み僧１２を流れる。したかつ−゛て、
高濃度Ｎ形不純物拡散領域１６がら埋込み＋９５７２
。However, the main part that acts as a collector is embedded thin/2
The main collector Tri flow flows through the embedded monk 12. Shitakatsu-te,
High concentration N type impurity diffusion region 16 buried +9572
.
をこ至るまでのＮ形エピタキシャル領域／ｌの部分はコ
レクタ電こ直列に接続された抵抗として作用し、コレク
タ抵抗を薩くする要因となっており、これがバイポーラ
トランジスタの電気的特性の低下を招いていた。The part of the N-type epitaxial region /l up to the point acts as a resistor connected in series with the collector voltage, and is a factor that reduces the collector resistance, which causes a deterioration of the electrical characteristics of the bipolar transistor. was.
以下実施例として、第１図の場合と同様、ＮＰＮ形バイ
ポーラトランジスタ（こっきそのコレクタ領域９こ本発
明方法を適用した場合につき説明する。As an example, a case in which the method of the present invention is applied to the collector region 9 of an NPN type bipolar transistor (hereinafter referred to as the collector region 9) will be described as in the case of FIG. 1.
なお、各図において、第１図のトランジスタと同□日−
ｍｉ分を示すものをこけ同一符号を付して示しである。In addition, in each figure, the same day as the transistor in Figure 1 -
The same reference numerals are used to indicate the mi minutes.
第２，３およびダ図は半導体装置としてのＮＰＮ形バイ
ポーラトランジスタの製造工程の各断面図を示したもの
である。Figures 2, 3 and 3 show cross-sectional views of the manufacturing process of an NPN type bipolar transistor as a semiconductor device.
先ず第２図に示すようしこ、通常のバイポーラトランジ
スタ製造技術を用いて、結晶面＜ｉｏｏ＞を有するＰ形
半導体基板／θ上にＮ形埋込み拡散領域／２、Ｎ形エピ
タキシャル成長領域／グ、ベース領域／に、エミッタ領
域〃を順次形成し、さらに基板表面／Ｓ上【こ酸化膜の
絶縁層ｎを形成する。従来の １ＮＰＮ形バイポーラト
ランジスタの製造工程では、第１図に示すように、エミ
ッタ領域〃を熱拡散法によって形成する工程において、
四時にアルミニウムのような金ＦＡ 電極ｆｆとのオー
ミック接触を容易ならしめるため、高不純物濃度のＮ影
領域１６をコレクタ領域／りの表面【こ形成していたが
、本実施例ではコレクタ［ｔｄＩ／にこ本発明方法を適
用するため、エミッタ領域〃のみを高濃度Ｎ形不純物熱
拡散する。First, as shown in FIG. 2, an N-type buried diffusion region /2, an N-type epitaxial growth region /G, An emitter region is sequentially formed on the base region /, and an insulating layer n of this oxide film is further formed on the substrate surface /S. In the conventional manufacturing process of a 1NPN type bipolar transistor, as shown in FIG. 1, in the process of forming the emitter region by a thermal diffusion method,
In order to facilitate ohmic contact with the gold FA electrode ff, such as aluminum, an N shadow region 16 with a high impurity concentration was formed on the surface of the collector region. In order to apply the method of the present invention, only the emitter region is thermally diffused with high concentration N-type impurities.
つぎ（こ第３図番こ示すようしこ、コレクタ電極を取出
すｇｌ’分Ｅこ、半導体基板の表面／Ｓから内部【こ向
け、埋込み層／２＆こ達するまでの穴３θをあける。こ
の穴３０目つきのようをこして形成する。Next (as shown in Figure 3), a hole 3θ is made from the surface /S of the semiconductor substrate until it reaches the buried layer /2&. Strain and form a 30-mesh mixture.
先ず、ホトエツチング法により基板表面ｌｊ上の□絶縁
層ｎのコレクタ電極形成予定部をこ、各辺が結晶軸＜／
／／＞と平行となるように矩形の窓をあけ、ついでこの
窓を通してＮ形エピタキシャル領域／りを異方性エツチ
ングし、埋込み層／２ ＆こ達する断面かＶ字状の穴３
θを形成する。この実施例では異方゛□性エツチングと
してエチレンジアミン曽ピロカテコール水混合液による
エツチング（以下ＪＥＰＷエツチング」と称する）技術
を用いる。ＥＰＷエツチングによれは、＜／／／＞面の
エツチング速度が他に比べて非常に遅いため、絶縁層〃
の窓の直下のエピタキシャル領域／グにはＶ字状の穴３
θをあけることができる。この穴３θの深さは絶縁層〃
にあける窓の幅で一義的に定まるので、穴３θの深さの
制御は正確（こ行なうことができる。例えは、穴３θの
深さを５μｍとするには窓の幅を約７μｍにすれば□よ
い。First, by photo-etching the portion where the collector electrode is to be formed of the insulating layer n on the substrate surface lj, each side is aligned with the crystal axis.
A rectangular window is made parallel to //>, and then the N-type epitaxial region /2 is anisotropically etched through this window to form a buried layer /2 & a V-shaped hole 3 in cross section.
form θ. In this embodiment, an etching technique using a mixture of ethylene diamine and pyrocatechol water (hereinafter referred to as JEPW etching) is used as anisotropic etching. Due to EPW etching, the etching speed of the <///> plane is very slow compared to other surfaces, so the insulating layer
There is a V-shaped hole 3 in the epitaxial region directly under the window.
θ can be opened. The depth of this hole 3θ is the insulating layer
Since it is uniquely determined by the width of the window drilled in the hole, the depth of the hole 3θ can be accurately controlled. For example, in order to make the depth of the hole 3θ 5 μm, the width of the window should be approximately 7 μm. It's good.
その後第グ肉に示すようをこ、絶縁層２２にエミッタ’
ａｓｈおよびペース電極取出し用の窓もあけ、これらの
窓と前記コレクタ１［１ｔｔｉ＜取出し用の穴３θを介
して従来法をこならって各領域にアルミニウム電極１膜
を同時（こ蒸着してエミッタ電極２４ｔ１ベース電極ｘ
Ｈよびコレクタ電＠ｒ 、２Ｊ’を形成する。After that, apply the emitter to the insulating layer 22 as shown in the figure.
Windows for taking out the ash and pace electrodes were also opened, and one aluminum electrode film was simultaneously deposited on each area using the conventional method through these windows and the collector 1[1tti<exit hole 3θ. Electrode 24t1 base electrode x
H and collector voltage @r, 2J' are formed.
上述したようにすれは、アルミニウム’ＫＴｈｆｆは埋
込み層／２とｉ［ｔ６オーミツク接触するため、従来構
造の′電極の場合に存在したコレクタ電極と埋込み僧／
２との間の抵抗を取り除くことができる。 □上＞？ｌ
＼の実施例ではＮＰＮ形バイホーラトランジスタの例を
こつきｋ、明したが、本発明はＰＮＰ ｊ？ ｈランジ
スタても同ト）【こ適用てきることは勿Ｍ：ｉｌであり
、Ｈた１１・しこバイポーラトランジスタのコレクタ面
々１１抵抗の但滅たけで７’ｌ： ＜ 、竿本体基板内
部に存在する領域９こｉｌｉ、 ｆｄｌ、を］１１杉、
掻糾する場合に全て適月Ｊすることができる。As mentioned above, since the aluminum 'KThff is in i[t6 ohmic contact with the buried layer /2, the collector electrode and the buried layer /2, which existed in the case of the ' electrode of the conventional structure,
2 can be removed. □Top＞? l
In the embodiment of \, an example of an NPN type bihole transistor was explained, but the present invention is a PNP type bihole transistor. (The same applies to the H transistor) [This can of course be applied to M:il, and the collector side of the bipolar transistor is 7'l: <, inside the rod main board. Existing area 9 koili, fdl,] 11 cedar,
If you want to discuss everything, you can do it all at the appropriate time.
ｌ「お、第３図図下のＪ２施例において、ＥＰＶ／エッ
士ング後に、穴ゴ０の表面から高濃度Ｎ形不純物を′□
４］／、 ｆＸｖＬ／て破ζ１７ ｆこて示すようＥこ
高濃度Ｎ形り八じｒ領域３ノを升ｅ成すれは、アルミニ
ウム電神１２ＸとＩＪ ＞ｂエピタキシャル領域／グと
のオーミック接触面積を大きくシ、エレクトロマイグレ
ーションの防＋Ｉ−にこ役立つ。さらＧこその場合【こ
は、例えは第Ｓ図のように”…［而か７字状の穴３θの
先端３グかＮ形坤込み拡１け領ｒｐ＞化ル遡〃にあける
窓中１１Ｔを１・きくすることもできる。``Oh, in the J2 example shown at the bottom of Figure 3, after EPV/etching, high concentration N-type impurities were removed from the surface of the hole 0.''
4] /, f It increases the area and helps prevent electromigration. Furthermore, in the case of G [for example, as shown in Figure S]...[And the window to be made in the tip 3 of the 7-shaped hole 3θ or the N-shaped kon-in-in expansion area rp>retrograde] You can also listen to 11T in middle school.
以上実施例で革［７たよう（こ、半導体表面がら内部に
向けて異方性エラチンブレこより穴をあけ、その穴の表
面に導電膜を形成した電挿シを使用することにより、あ
る深さをもって形成された１４ Ｇこ′電極を必要とす
る領域を有する半導体装置の電気特性の低下を防ぐこと
ができると云う優れた効果がある。In the above embodiments, holes were made inward from the semiconductor surface using an anisotropic elastomer, and a conductive film was formed on the surface of the holes. This has the excellent effect of preventing deterioration of the electrical characteristics of a semiconductor device having a region requiring a 14G electrode formed using the same method.
第１図は従来の電極構造を有するＮＰＮ形のバイポーラ
トランジスタの一例を示すｉ＋面図、第２〜１図は本発
明方法を適用してＮＰＮ形のバイポーラトランジスタを
形成する順次の製造工程【こおけ□る断面図、第乏図は
本発明方法の他の実施例を示す断面図である。
ｌθ・・・Ｐ形基板、１２・・・埋込み層、／グ・・・
Ｎ形エピタキシャル領域、／Ｓ・・・半導体基板の表面
、ｌｔ・・・高濃度Ｎ影領域、７ｇ・・・Ｐ形ベース領
域、〃・・・Ｎ形エミ）ツタ領域、〃・・・わ・Ｉ縁層
、２り・・・エミッタ電極、ｎ・・・ベース電極、π・
・フレフタ’ＫＬ％、３θ・・・穴、３２．・・・高濃
度Ｎ形拡散領域。
第１図
第２図
汝 σ］ で−
５−丁二ｒｔイー−１
第４図
ｉＩ塚に 、Ｔ伊
ｌノ＋７ ｖ、、 、／さ４
３４ ３０２２
ｚｉシーゴ７ジーｆ５
第１頁の続き
■発 明 者 −瀬功
東京都渋谷区幡ケ谷２丁目４３番
２号才リンパス光学工業株式会
社内
、塑合 明 者 中村康男
東京都渋谷区幡ケ谷２丁目４３番
２号才リンパス光学工業株式会
社内
塑合 明 者 小牧大卒
東京都渋谷区幡ケ谷２丁目４３番
２号才リンパス光学工業株式会
社内
１１２−FIG. 1 is an i+ side view showing an example of an NPN bipolar transistor having a conventional electrode structure, and FIGS. The sectional views shown in the left and right are sectional views showing other embodiments of the method of the present invention. lθ...P-type substrate, 12...buried layer, /G...
N-type epitaxial region, /S...Semiconductor substrate surface, lt...High concentration N shadow region, 7g...P-type base region, 〃...N-type emitter) ivy region, 〃...W・I edge layer, 2...emitter electrode, n...base electrode, π・
・Frefter'KL%, 3θ...hole, 32. ...High concentration N-type diffusion region. Fig. 1 Fig. 2 Thou σ] de-5-cho2 rtE-1 Fig. 4 iI mound , Tilno+7 v,, , /sa4 34 3022 zi Shego 7 Zi f5 Continuation of page 1 ■Inventor: Seko, 2-43-2 Hatagaya, Shibuya-ku, Tokyo, within Lymphus Optical Industry Co., Ltd.; Yasuo Nakamura, 2-43-2 Hatagaya, Shibuya-ku, Tokyo; within Lymphus Optical Industry Co., Ltd. Graduated from Komaki University 2-43-2 Hatagaya, Shibuya-ku, Tokyo 112-2, Lymphus Optical Industry Co., Ltd.
Claims (1)
前１ｎｉ下の所定深さに位置する領域に向けて異方性エ
ツチングを行ない、これにより形成されたエツチング面
上をこ霜′、極層を設けることを特徴とする半導体装置
用電極の形成方法。 ２、特許請求の範囲第１頂記載の方法（こおいて・ζ異
方１）１：エツチングをＥＰＷエツチングとすることを
特徴とする半導体装置用電極の形成方法。 ３ 特許請求の範囲第２項記１モ・の方法において、Ｅ
ＰＷエツチングを行なう半４４体基板の結晶面を＜ １
００ ＞面とすることを特徴とする半導体装置用電極の
形成方法。[Claims] L Anisotropic etching is performed from the surface of a semiconductor substrate on which a semiconductor device is formed to a region located at a predetermined depth 1 ni below the front of the substrate, and the etched surface formed thereby is etched. A method for forming an electrode for a semiconductor device, characterized by providing a frost layer and a polar layer. 2. The method described in the first claim (herein: ζ anisotropy 1) 1: A method for forming an electrode for a semiconductor device, characterized in that the etching is EPW etching. 3 In the method of Claim 2, Paragraph 1,
The crystal plane of the semi-44-piece substrate to be subjected to PW etching is < 1
A method for forming an electrode for a semiconductor device, characterized in that the electrode has a 00> plane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18297881A JPS5885528A (en) | 1981-11-17 | 1981-11-17 | Forming method of electrode for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18297881A JPS5885528A (en) | 1981-11-17 | 1981-11-17 | Forming method of electrode for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5885528A true JPS5885528A (en) | 1983-05-21 |
Family
ID=16127623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18297881A Pending JPS5885528A (en) | 1981-11-17 | 1981-11-17 | Forming method of electrode for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5885528A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55162270A (en) * | 1979-06-02 | 1980-12-17 | Sharp Corp | Semiconductor device |
-
1981
- 1981-11-17 JP JP18297881A patent/JPS5885528A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55162270A (en) * | 1979-06-02 | 1980-12-17 | Sharp Corp | Semiconductor device |
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