JPS588268U - Input level limit circuit - Google Patents
Input level limit circuitInfo
- Publication number
- JPS588268U JPS588268U JP10211481U JP10211481U JPS588268U JP S588268 U JPS588268 U JP S588268U JP 10211481 U JP10211481 U JP 10211481U JP 10211481 U JP10211481 U JP 10211481U JP S588268 U JPS588268 U JP S588268U
- Authority
- JP
- Japan
- Prior art keywords
- audio signal
- input level
- limit circuit
- level limit
- output audio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Television Signal Processing For Recording (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案になる入力レベル制限回路の1実施例のブロ
ック系統図である。
1.5・・・入力端子、2・・・増幅器、3・・・出力
端子、4・・・スイッチ、6・・・制御電圧発生回路、
7・・・可変インピーダンス素子、R1・・・抵抗。The figure is a block diagram of one embodiment of the input level limiting circuit according to the present invention. 1.5...Input terminal, 2...Amplifier, 3...Output terminal, 4...Switch, 6...Control voltage generation circuit,
7...Variable impedance element, R1...Resistance.
Claims (1)
ーダのRFコンバータに供給する増幅器と、該出力音声
信号を供給され該出力音声信号が過大とならないよう該
増幅器の利得を調整する自動利得制御回路と、該自動利
得制御回路の動作を該ビデオテープレコーダの再生時の
みに限定するスイッチとよりなる入力レベル制限回路。an amplifier that amplifies an audio signal and supplies the output audio signal to an RF converter of a video tape recorder; and an automatic gain control circuit that is supplied with the output audio signal and adjusts the gain of the amplifier so that the output audio signal does not become excessive. , an input level limiting circuit comprising a switch that limits the operation of the automatic gain control circuit only to playback of the video tape recorder.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10211481U JPS588268U (en) | 1981-07-09 | 1981-07-09 | Input level limit circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10211481U JPS588268U (en) | 1981-07-09 | 1981-07-09 | Input level limit circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS588268U true JPS588268U (en) | 1983-01-19 |
JPS6130357Y2 JPS6130357Y2 (en) | 1986-09-05 |
Family
ID=29896766
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10211481U Granted JPS588268U (en) | 1981-07-09 | 1981-07-09 | Input level limit circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS588268U (en) |
-
1981
- 1981-07-09 JP JP10211481U patent/JPS588268U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6130357Y2 (en) | 1986-09-05 |
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