JPS5877311A - Automatic gain controlling circuit - Google Patents
Automatic gain controlling circuitInfo
- Publication number
- JPS5877311A JPS5877311A JP17622681A JP17622681A JPS5877311A JP S5877311 A JPS5877311 A JP S5877311A JP 17622681 A JP17622681 A JP 17622681A JP 17622681 A JP17622681 A JP 17622681A JP S5877311 A JPS5877311 A JP S5877311A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- gain
- level
- signal
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 8
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 4
- 230000010355 oscillation Effects 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Analogue/Digital Conversion (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、データ伝！ＩＶステ五等において受償償号し
ペｋを一定ｗｋ＠にする九めの自動利得制御回路に関す
る。 。[Detailed Description of the Invention] The present invention is based on data transmission! This invention relates to a ninth automatic gain control circuit that adjusts pek to a constant wk@ in IV step 5, etc. .
青声帯賊Ｏ電話四線を用いたデータ伝送等で拡、加入者
線による信号の減衰が回線接続毎に変化する九め、デー
タ受信装置の初ＲＫ受信信号レベルを一定にする九めの
自動利得制御（ムＱＣ）１回路を設妙る必要がある。最
近、音声帯域０１１Ｗ／ｉＩ圏線用変復調装置（モデム
）は、半導体技術の進歩によルｒイジタルＬＳＩ、マイ
クロ／ロセを等で構成される傾向に６Ｊ）、ムＧＣｇｉ
路へもディジタル信号ＩＩＪＡＩｌ技術が適用され始め
でいる。しかしながら、ディジタル化され九人０Ｃ回路
で鉱アナログ形ＡＧＣｇｌ路と比べて、無調整で安定動
作が得られる反面、利得の設定がディスクリートクまタ
ステッｌ的になる丸め、単一の基準レベルで受信信号レ
ベルを判定し、それに基いて利得Ｏ−制御を行なうと、
基準レベルを境として利得の最小メテッｌで利得が振動
４して雑音を発生させる。この丸めディジタル化ＡＧＣ
＠ ＠ ＃ｉ、７す０ ／ＡＧＣ１１１ＩＫ比べ性能＃
劣化すると、ｖｈう欠点、を有していえ。Blue Voice Bandit O Telephone Expanded by data transmission using four wires, the ninth point is that the attenuation of the signal by the subscriber line changes with each line connection, and the ninth point is automatic, which keeps the initial RK reception signal level of the data receiving device constant. It is necessary to design a gain control (MUQC) circuit. Recently, due to advances in semiconductor technology, modems for voice band 011W/iI area lines have tended to be composed of digital LSIs, micro/Loss chips, etc.6J), mu GCgi
Digital signal IIJAIl technology is also beginning to be applied to roads. However, compared to the digital analog AGC circuit, the digitized 9-channel 0C circuit provides stable operation without any adjustment, but the gain setting is discrete or rounded, and reception is received at a single reference level. By determining the signal level and performing gain O-control based on it,
The gain oscillates at a minimum level of 4 with respect to the reference level, generating noise. This rounding digitization AGC
@ @ #i, 7s0 / Performance compared to AGC111IK #
When it deteriorates, it has some disadvantages.
本発明状、このような従来Ｏ岡層点に鍾みなされ良もＯ
で、利得の振動Ｏ生しな一高性能のディジタル化された
ムＧＣａ路を提供する事を目的として−１゜
本発−は入カアナ四ダ信号をそＯ振幅を変化させ為利得
可変回路と４／ｂ′ｍ′換崗路を通じてｒイジタル演算
回路に導電、こＯディジタル演算１略によって利得可変
回路Ｏ利得を制御するムＧＣＨ路におｉで、ディジタル
演算回路を前記Ｎ勺変換１ａｖｏａｓカ信−＋ｔｏ平均
レベルを検出すｉａｍと、ζＯ平均レベルを複数の基準
レベルと比較して判定するレベル判、定回路と、この判
ｍａｓｏｎ定結果に基量前記平均しくルが前記基準レベ
ルＯ任意の２つのレベルの関Ｋ１１Ｌ東す為方向に前記
利得可変回路の利得をステップ的に制御する丸めの制御
償勺を発生する制御信号発生回路とから構威しえととを
特徴とする。The present invention is based on the conventional Ooka layer point.
In order to provide a high-performance digitized GCa circuit with no gain oscillations, a variable gain circuit is used to change the amplitude of the input analog signal. The digital arithmetic circuit is connected to the GCH path which controls the gain of the variable gain circuit by the digital arithmetic operation 1, and the digital arithmetic circuit is connected to the digital arithmetic circuit through the 4/b'm' conversion path. iam for detecting the average level, a level judgment circuit for determining the ζO average level by comparing it with a plurality of reference levels, and a constant circuit for determining the average level. The present invention is characterized by comprising a control signal generating circuit that generates a rounding control compensation for controlling the gain of the variable gain circuit stepwise in the direction of the K11L of arbitrary two levels.
Ｉ！９て、本発−にぶれば前記平均レベルが会意０２つ
の基準レベルの間に収束した段階で利得が一定となるの
で、利得の振動が生ずること娘なく、Ｉ２定なムＱＣ動
作を達成することができ為。I! 9. According to the present invention, the gain becomes constant at the stage when the average level converges between the two reference levels, so no gain oscillation occurs and I2 constant QC operation is achieved. Because you can.
以下、図面を参照して本発明の一実施例を説明する。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示し九％Ｇで、入力端子Ｉ
Ｋは例えばデータ受信装置の受償償４＃Ｏようなアナロ
グ信号が久方される・ζ０人カアナログ信号は外部から
の制御によ）利得が変化する利得可変回路２で振幅制御
された後、ル勺変換回路１でディジタル信号に襞換され
て一イジタル擁算回路４に与えられる。すなわち、〜勺
変換回路ＪＯ出力信号はデ０．イジタルフィルタによ）
構成された直流除去フィルタＪＫよって〜勺変換回路Ｉ
で生じえ直流分を除去され先後、ムＧＣＩＩＩＩＯ後段
に配置され九復調回路等のディｙＩル儒号旭理回路へ出
力端子Ｃを介して出力されるとともに、絶対値■路ｒシ
よびディジタルフィルタによ〕構成畜れえ低域通過フィ
ルターを通してそＯ平均レベルが検出される。FIG. 1 shows an embodiment of the present invention with 9% G and input terminal I.
For example, K is an analog signal such as 4 #O of a data receiving device, which is used for a long time. After the amplitude of the analog signal is controlled by a variable gain circuit 2 whose gain is changed by external control, The digital signal is converted into a digital signal by the digital conversion circuit 1 and is applied to the digital addition circuit 4. That is, the output signal of the conversion circuit JO is de0. (by digital filter)
According to the configured DC removal filter JK ~ 2000 conversion circuit I
After removing the DC component that may occur in The average level is detected through a low-pass filter.
低域通湯フィルタ＃Ｏ出力は異なる基準レベルＬ１ ｗ
ＡＩが与えられ＊！りわレベル比較四路＃ｌ＊＃ｌから
なるレベル判定回路１０でレベル判定され、その判定艙
来が制御信号発生１ｌｌｌＩＪＪＫ与えられる。制御信
号発生回路１１は上記判定鏑果に１暑、利得可変鴎路ｇ
ｏ１１＠得をステップ的に制御するえめＯ制御償奇を発
生する。Low-pass hot water filter #O output is at different reference level L1 w
AI is given *! A level judgment circuit 10 consisting of four level comparison circuits #l*#l judges the level, and the judgment result is given to a control signal generation 1llllIJJK. The control signal generation circuit 11 has a variable gain control signal for the above judgment.
o11 Generates O control compensation that controls the gain in steps.
Ｃ０ＡＧＣＱ１１０１１６作を第＊＊を用ｈ”（説明す
る。第２ＩＩ（ａ）は基準レベルを１つしか誇大１に％
Ａ質来Ｏディジタル化鄭に回路の動作を示し、伽）は３
りＯ基準レベルＬ＠ ｅ Ｌ嘗を有する本発明夷論例
ＯＡＧＣ−路Ｏ動作を示して−１゜第冨−一）Ｏ場舎、
検出畜れた平均レベル１１紘時ｍｔ＠ＫＴｈ９／ｈて基
準レベルＬよ〕上にあるから、利得可変回路の利得を下
げる様な制御値４Ｉが出力１れ、時ｍ ｔ 重で検出堪
れ為平均レベルは時ｔｓｔ・でＯレベルより％小さくな
る０時刻ｔ１でＯ平均レベルは基準レベルＬよ）も會に
上Ｗｃ−為丸め、さらに時刻ｔ−で平均レベルが下うて
、基準レベルＬよルも下のレベルとなる拳し九がりて、
今ｌＩ！紘利得可変回路の利得を上げる制御償奇が出方
され、時刻１．で紘、平均レベル２６＆基準レベルよ〕
上のレベルとなる。The C0AGCQ110116 work is explained using the ``h'' (Explain. 2nd II (a) sets the reference level to only one exaggerated 1%
A) shows the operation of the circuit in O digitalization, 伽) is 3
The present invention's example OAGC-route O operation having an O reference level L@e L嘗 is shown in the following example.
Since the detected average level 11 mt@KTh9/h is above the reference level L, the control value 4I that lowers the gain of the variable gain circuit is output 1, and the detection is completed at mt. Therefore, the average level becomes % smaller than the O level at time tst.0 At time t1, the O average level is the reference level L), so the average level is rounded up by Wc-, and furthermore, at time t-, the average level decreases and becomes the reference level. L's fists are also at a lower level,
Now lI! Controlled compensation is performed to increase the gain of the variable gain circuit, and at time 1. Hiro, average level 26 & standard level]
It will be the upper level.
ζ０ＩＩＩＩＫＩＩＩ準レベルなｌりしか持たない従来
のディジタル化ムＱＣｇ路で紘、基準レベルを中心とし
て利得Ｏ最小制御ステ、ｆで平均レベルがｆｉｆッ：＃
ＪＫ−績動する事Ｋｔｌこのレベル変化がディジタル化
ムＧＣ＠路で新九に発生しぇ雑費となって、出力され１
事になる。ζ0IIIKIII In the conventional digitized system QCg which has only quasi-level, the gain O is minimum control stage centered around the reference level, and the average level is fif at f: #
JK-Ktl This level change occurs in the digital system GC@road, becomes a miscellaneous cost, and is output.
It's going to happen.
これに対し、第１図のムＧＣ回路の動作は、第２ｗＡ伽
）Ｋ示すように時刻ｔ・ ｅｔｌは上Ｏ基準し゛ペルｔ
ｌと比較されて平均レベルｊ２は基準レベル１１に近づ
き、時刻ｔ３で基準レベルｔ１と１．との間に入る。今
、制御信号発生闘賂ＪＪＫよる利得可変回路ｊｏ利得制
御を、平均レベル１２が基準レベル２＝よ）上に６ると
自利得を下げ、Ｌｌよ）下ｔｃ＆ると自利得を上げ、さ
らに、基準レベルＬ１と１．と０ＩＩＫあると１紘利得
を変化させな＆１ｍ１Ｋすれば、＠２図６）Ｋ示される
如く、受信信号の平均信号レベルは時刻４ｍ以降、一定
値上な）、従来Ｏｒィジタル化ＡＧＣｍ１ｌｌ Ｋ見ら
れるステラＩ的な振動拡止じなくなる。On the other hand, the operation of the GC circuit shown in FIG.
The average level j2 approaches the reference level 11 when compared with the reference level t1 and 1.l at time t3. come between. Now, the variable gain circuit jo gain control by the control signal generation bribe JJK, the average level 12 is the reference level 2 = Y) above 6 lowers the own gain, Ll) below tc& increases the own gain, and , reference levels L1 and 1. If there is 0IIK, do not change the gain &1m1K, @2 As shown in Figure 6), the average signal level of the received signal is above a constant value after time 4m). Stella I-like vibration expansion is no longer possible.
なお、第１ｌｌＯ実施例ではレベル判定回路を２つのレ
ベル比較回路で構威し九が、必ずし４２つ設置する必要
はなく、複数Ｏ基準レベルと平均レベルとＯ複数ｌＩＯ
比職を１’）０レベル比較回路で時分割的に用いて行１
にりてよい、また、上記実施例で紘基準レベルを２つと
して説−したが、基準レベルを更に増中して平均ジベル
が任意Ｏ隣接すｈ２つの基準レベル０ｒＡＫ１１Ｌ東す
み橡に利得制御を行なりてもよい、そＯ場合、制御値４
＃発生肯賂による利得制御量（利得制御Ｏステップ幅）
を、レベル判定回路の判定鐘果に応じて、りｔ）平均レ
ベルが基準レペクで設置ｉ！１れ大レベル領域０２０位
置にあるかに応じてＪＨｋらせることによｐ、利得制御
が安定する迄ＫＩＩｆ為時間を短縮化することもで自重
。In the first embodiment, the level judgment circuit is composed of two level comparison circuits, but it is not necessarily necessary to install 42 of them, and it is not necessary to install 42 level comparison circuits.
Row 1 using ratio time in 1') 0 level comparison circuit
In addition, in the above embodiment, it was explained that there are two reference levels, but it is possible to further increase the reference level and apply gain control to the two adjacent reference levels so that the average giber is arbitrary. If so, the control value 4
#Gain control amount by generated reward (gain control O step width)
, depending on the judgment result of the level judgment circuit, the average level is set at the reference level i! By adjusting JHk depending on whether the gain control is stabilized or not, it is possible to shorten the time required for KIIf until the gain control is stabilized.
表１爾の簡単亀Ｉ！―
第１ＩＩは本１ａ＠〇−夷論例に係る利得制御圃路〇−
路図、嬉２閣伏その動作を説−すｈえ゛めの値ｉ＃図で
Ｔｏｈ。Table 1: Easy Turtle I! - Part 1 II is Book 1a @〇-Gain control field according to the example of the theory〇-
Explain the operation of the map, the value of the first value i # Toh.
１−入力端子、ｊ−１１得可変回路、Ｉ−φ変ｌｌ１１
１ＩＩＩ％４・−ディジタル演算−路、Ｊ −・直流除
去フィルタ、“ト・出力端子、ｒ・・・絶対値ａｍ。1-input terminal, j-11 gain variable circuit, I-φ change ll11
1III%4 - Digital calculation path, J - - Direct current removal filter, "output terminal, r... Absolute value am.
ｇ−低ｍ通過フィルタ、＃＊ｍＭ重−レベル比較圏路、
１＃・・・レベル判定回路、１１−制御償今発生鴎略。g-low m pass filter, #*mM heavy-level comparison path,
1#...Level judgment circuit, 11-control compensation current occurrence method.
１１１図 ｍ２図 第１頁の続き ０発 明 者 能勢敏部 日野市旭が丘３丁目１番地の１ 東京芝浦電気株式会社日野工場 内Figure 111 m2 diagram Continuation of page 1 0 shots clear person Toshibe Nose 3-1-1 Asahigaoka, Hino City Tokyo Shibaura Electric Co., Ltd. Hino Factory Inside
Claims (2)
変回路と、この利得可変回路の出力信号をディジタル信
号に変換する〜勺変換回路と、この〜勺変換回路の出力
信号を受けて前記利得可変回路の利得を制御する９４ジ
タル演算−路とを備え、前記、ディジタル演算回路は前
記め変換回路の出力信号の平均レベルを検出する回路と
、この平均レベルを複数の基準レベルと比較して判定す
るレベル判定回路と、ヒ０４１ＩＪｉ！回路の判定結果
に葺き前記平均レベルが前記基準レベルの任意の２つの
レベル０１１１に収束する方向に前記利得回路の利得を
ステップ的に制御する九めの制御信号を出力すみ制御備
考発生回路とから構成されることを特徴とする自動利得
制御回路。(1) A variable gain circuit that changes the amplitude of an input analog signal, a conversion circuit that converts the output signal of the variable gain circuit into a digital signal, and a variable gain circuit that receives the output signal of the conversion circuit. 94 digital arithmetic circuits for controlling the gain of the digital arithmetic circuit; the digital arithmetic circuits include a circuit for detecting the average level of the output signal of the conversion circuit; and a circuit for determining the average level by comparing it with a plurality of reference levels. Level judgment circuit and Hi041IJi! A ninth control signal is outputted based on the judgment result of the circuit, and a ninth control signal is outputted to control the gain of the gain circuit stepwise in a direction in which the average level converges to any two levels 0111 of the reference level. An automatic gain control circuit comprising:
レベルとＯ比、較を１つのレベル比Ｉｌ１ｗＡ路を時分
割的に用−て行なうものであることを特徴とする特許請
求の範囲第１項記載の自動利得制御−路。 ―） 制御信号発生關路紘、レベル判定回路Ｏ判電紬果
に応じて利得可変回路に、対す為利得制御量を変化１せ
るようを制御信号を出力するもＯ″ｅあることを特徴と
する特許請求の範囲第１項記載Ｏ自動利得制御閏路。(2) The level determination circuit line performs the comparison between the average level and a plurality of reference levels in a time-sharing manner using one level ratio Il1wA path. Automatic gain control as described in Section 1. --) The control signal generation circuit is characterized by outputting a control signal to the gain variable circuit to change the gain control amount by 1 according to the output of the level judgment circuit. An automatic gain control tunnel according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17622681A JPS5877311A (en) | 1981-11-02 | 1981-11-02 | Automatic gain controlling circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17622681A JPS5877311A (en) | 1981-11-02 | 1981-11-02 | Automatic gain controlling circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5877311A true JPS5877311A (en) | 1983-05-10 |
| JPH0156575B2 JPH0156575B2 (en) | 1989-11-30 |
Family
ID=16009828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17622681A Granted JPS5877311A (en) | 1981-11-02 | 1981-11-02 | Automatic gain controlling circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5877311A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59224907A (en) * | 1983-06-06 | 1984-12-17 | Fujitsu Ltd | Digital control type agc circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7117744B2 (en) | 2019-09-17 | 2022-08-15 | 国立大学法人埼玉大学 | Current interrupting device and current interrupting method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS503759A (en) * | 1973-05-15 | 1975-01-16 |
-
1981
- 1981-11-02 JP JP17622681A patent/JPS5877311A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS503759A (en) * | 1973-05-15 | 1975-01-16 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59224907A (en) * | 1983-06-06 | 1984-12-17 | Fujitsu Ltd | Digital control type agc circuit |
| JPH0223098B2 (en) * | 1983-06-06 | 1990-05-22 | Fujitsu Kk |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0156575B2 (en) | 1989-11-30 |
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