JPS5875495U - Inverter output voltage control device - Google Patents
Inverter output voltage control deviceInfo
- Publication number
- JPS5875495U JPS5875495U JP16826381U JP16826381U JPS5875495U JP S5875495 U JPS5875495 U JP S5875495U JP 16826381 U JP16826381 U JP 16826381U JP 16826381 U JP16826381 U JP 16826381U JP S5875495 U JPS5875495 U JP S5875495U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- limit value
- inverter
- addition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図はインバータの出力電圧制御装置の回路図、第2
図は第1図における各部の波形およびタイミングチャー
トである。
1〜インバータ、4,5〜ドライブ回路、10〜変圧器
、11〜整流回路、12〜電圧−周波数変換回路、13
〜力ウンター回路、14〜加減算回路、15〜加減算結
果比較プログラム回路、16〜シフト量ロツクプログラ
ム回路、17〜メモリ一回路、18〜シフト量指令回路
、19〜ダウンカウンタ−補助設定回路、20〜シフト
パルス回路、21〜主パルス回路、22〜発振回路、2
3〜分周回路、24〜タイミング信号回路。Figure 1 is a circuit diagram of the inverter output voltage control device, Figure 2
The figure is a waveform and timing chart of each part in FIG. 1. 1 - Inverter, 4, 5 - Drive circuit, 10 - Transformer, 11 - Rectifier circuit, 12 - Voltage-frequency conversion circuit, 13
~Power counter circuit, 14~Addition/subtraction circuit, 15~Addition/subtraction result comparison program circuit, 16~Shift amount lock program circuit, 17~Memory circuit, 18~Shift amount command circuit, 19~Down counter auxiliary setting circuit, 20~ shift pulse circuit, 21 - main pulse circuit, 22 - oscillation circuit, 2
3 - frequency divider circuit, 24 - timing signal circuit.
Claims (1)
の変圧器10に接続された整流回路11と、この整流回
路11に接続された電圧−周波数変換回路12と、この
電圧−・周波数変換回路12に接続されインバータ出力
の一周期毎に周波数をカウントするカウンター回路13
と、このカウンター回路13に接続され、カウンター回
路13から出力されるデジタルデータ数から一定数を減
算し、かつ後記メモリー回路17の内容を加算する加減
算回路14と、この加減算回路14に接続され加減算回
路14の演算結果をメモリーするとともに、後記シフト
量指令回路18に送るメモリー回路17と、このメモリ
ー回路17に接続されメモリー回路17の内容をダウン
カウンタ−補助設定回路19で設定した値までダウンカ
ウントし、シフト指令信号を出すシフト量指令回路18
と、インバータのシフト量固定のトランジスタTrl、
Tr2のドライブ回路4にドライブ信号を出す主パルス
回路21と、前記シフト量指令回路18のシフト指令信
号を受はインバータのシフト量可変のトランジスタTr
3.Tr4のドライブ回路5にドライブ信号を出すシフ
トパルス回路20と、からなるインバ〜りの出力電圧制
御装置。 2 加減算回路14とメモリー回路17との間に、デジ
タルデータ数の入力が予め定めた上限値および下限値を
オーバーしたときにオーバー信号を出し、下限値ないし
上限値の範囲内のときはそのまま出力する加減算結果比
較プログラム回路15と、この加減算結果比較プログラ
ム回路15の出力が前記下限値ないし上限値の範囲内の
ときはそのまま出力し、前記オーバー信号のときは上限
値又は下限値を出力するシフト量ロックプッグラム回路
16と、を挿入したことを特徴とする実用新案登録請求
の範囲第1項記載のインバータの出力電圧制御装置。[Claims for Utility Model Registration] 1. A transformer 10 connected to the output side of an inverter, a rectifier circuit 11 connected to this transformer 10, and a voltage-frequency conversion circuit 12 connected to this rectifier circuit 11. , a counter circuit 13 connected to this voltage-frequency conversion circuit 12 and counting the frequency for each cycle of the inverter output.
An addition/subtraction circuit 14 is connected to this counter circuit 13 and subtracts a certain number from the number of digital data output from the counter circuit 13, and adds the contents of a memory circuit 17, which will be described later. There is a memory circuit 17 that stores the calculation result of the circuit 14 and sends it to the shift amount command circuit 18 described later, and a down counter that is connected to this memory circuit 17 and counts down the contents of the memory circuit 17 to the value set by the auxiliary setting circuit 19. and a shift amount command circuit 18 that outputs a shift command signal.
and a transistor Trl with a fixed shift amount of the inverter,
A main pulse circuit 21 that outputs a drive signal to the drive circuit 4 of the Tr2, and a transistor Tr that receives a shift command signal from the shift amount command circuit 18 and that can change the shift amount of the inverter.
3. An inverter output voltage control device comprising a shift pulse circuit 20 that outputs a drive signal to a drive circuit 5 of a Tr4. 2. An over signal is output between the addition/subtraction circuit 14 and the memory circuit 17 when the input number of digital data exceeds a predetermined upper and lower limit value, and when it is within the range of the lower limit value or upper limit value, it is output as is. an addition/subtraction result comparison program circuit 15 that outputs the addition/subtraction result comparison program circuit 15; when the output of the addition/subtraction result comparison program circuit 15 is within the range of the lower limit value or the upper limit value, the output is output as is; when the over signal is present, the upper limit value or the lower limit value is output. An inverter output voltage control device according to claim 1, characterized in that a quantity lock program circuit 16 is inserted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16826381U JPS5875495U (en) | 1981-11-13 | 1981-11-13 | Inverter output voltage control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16826381U JPS5875495U (en) | 1981-11-13 | 1981-11-13 | Inverter output voltage control device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5875495U true JPS5875495U (en) | 1983-05-21 |
Family
ID=29960315
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16826381U Pending JPS5875495U (en) | 1981-11-13 | 1981-11-13 | Inverter output voltage control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5875495U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52111622A (en) * | 1976-03-17 | 1977-09-19 | Hitachi Ltd | Semiconductor control apparatus |
-
1981
- 1981-11-13 JP JP16826381U patent/JPS5875495U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52111622A (en) * | 1976-03-17 | 1977-09-19 | Hitachi Ltd | Semiconductor control apparatus |
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