JPS5868710U - frequency multiplier - Google Patents

frequency multiplier

Info

Publication number
JPS5868710U
JPS5868710U JP16354581U JP16354581U JPS5868710U JP S5868710 U JPS5868710 U JP S5868710U JP 16354581 U JP16354581 U JP 16354581U JP 16354581 U JP16354581 U JP 16354581U JP S5868710 U JPS5868710 U JP S5868710U
Authority
JP
Japan
Prior art keywords
circuit
outputs
input signal
phase
linear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16354581U
Other languages
Japanese (ja)
Inventor
大塚 敏正
Original Assignee
アンリツ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by アンリツ株式会社 filed Critical アンリツ株式会社
Priority to JP16354581U priority Critical patent/JPS5868710U/en
Publication of JPS5868710U publication Critical patent/JPS5868710U/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の周波数てい倍器の構成を示すブロック図
、第2図は非直線回路の出力の周波数スペクトルと選択
回路の周波数特性との関係を示す図、第3図は本考案の
一実施例の周波数てい倍器の構成を示すブロック図、第
4図はその各部の波形を示す図、第5図は加減算回路の
出力の周波数スペクトルと選択回路の周波数特性との関
係を示す図、第6図は本考案による周波数てい倍器の具
体的構成例を示す回路図である。 1・・・非直線回路、2・・・選択回路、11・・・位
相反転回路、12・・・第1の非直線回路、13・・・
第2の非直線回路、14・・・加減算回路、15・・・
選択回路。
Figure 1 is a block diagram showing the configuration of a conventional frequency multiplier, Figure 2 is a diagram showing the relationship between the frequency spectrum of the output of the nonlinear circuit and the frequency characteristics of the selection circuit, and Figure 3 is a diagram showing the structure of a conventional frequency multiplier. A block diagram showing the configuration of the frequency multiplier of the embodiment, FIG. 4 is a diagram showing the waveforms of each part, FIG. 5 is a diagram showing the relationship between the frequency spectrum of the output of the adder/subtractor circuit and the frequency characteristic of the selection circuit, FIG. 6 is a circuit diagram showing a specific example of the structure of the frequency multiplier according to the present invention. DESCRIPTION OF SYMBOLS 1... Nonlinear circuit, 2... Selection circuit, 11... Phase inversion circuit, 12... First nonlinear circuit, 13...
Second non-linear circuit, 14... Addition/subtraction circuit, 15...
selection circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号を受領して、入力信号と同相の第1の゛  信
号と、入力信号と逆相の第2の信号とを発生する位相反
転回路と;前記第1の信号を受領して、入力信号と同周
波数の基本波成分とその高調波成分とを含む歪み波を出
力する第1の非直線回路と;前記第2の信号を受領して
入力信号と同周波数の基本波成分とその高調波成分とを
含み、前記第1の非直線回路の出力とは逆相の歪み波を
出力する第2の非直線回路と;前記第1、第2の非直線
回路の出力を加算又は減算して偶数次又は奇数次の高調
波成分のみを出力する加減算回路と;前記加減算回路の
出力から所望の周波数の高調波を取出す選択回路とを備
えた周波数てい倍器。
a phase inversion circuit that receives an input signal and generates a first signal that is in phase with the input signal and a second signal that is opposite in phase to the input signal; a first non-linear circuit that outputs a distorted wave including a fundamental wave component of the same frequency as the input signal and its harmonics; a second non-linear circuit that outputs a distorted wave having a phase opposite to that of the output of the first non-linear circuit; adding or subtracting the outputs of the first and second non-linear circuits; A frequency multiplier comprising: an adder/subtractor circuit that outputs only even-order or odd-order harmonic components; and a selection circuit that extracts harmonics of a desired frequency from the output of the adder/subtractor circuit.
JP16354581U 1981-10-31 1981-10-31 frequency multiplier Pending JPS5868710U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16354581U JPS5868710U (en) 1981-10-31 1981-10-31 frequency multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16354581U JPS5868710U (en) 1981-10-31 1981-10-31 frequency multiplier

Publications (1)

Publication Number Publication Date
JPS5868710U true JPS5868710U (en) 1983-05-10

Family

ID=29955838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16354581U Pending JPS5868710U (en) 1981-10-31 1981-10-31 frequency multiplier

Country Status (1)

Country Link
JP (1) JPS5868710U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4938157B1 (en) * 1968-10-05 1974-10-15
JPS505284U (en) * 1973-05-09 1975-01-20
JPS52119159A (en) * 1976-03-29 1977-10-06 Rca Corp Third harmonic wave signal generator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4938157B1 (en) * 1968-10-05 1974-10-15
JPS505284U (en) * 1973-05-09 1975-01-20
JPS52119159A (en) * 1976-03-29 1977-10-06 Rca Corp Third harmonic wave signal generator

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