JPS5862891A - Memory rewrite system - Google Patents
Memory rewrite systemInfo
- Publication number
- JPS5862891A JPS5862891A JP56161262A JP16126281A JPS5862891A JP S5862891 A JPS5862891 A JP S5862891A JP 56161262 A JP56161262 A JP 56161262A JP 16126281 A JP16126281 A JP 16126281A JP S5862891 A JPS5862891 A JP S5862891A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- error
- address
- storage device
- refresh
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はダイナミックメモリ素子により構成され、且つ
エラー訂正機能を有する記憶装置のエラー検出によりデ
ータを再書込みする場合のメモリ再書込み方式に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory rewriting method for rewriting data by detecting an error in a storage device configured with a dynamic memory element and having an error correction function.
最近、ダイナミックメモリ素子における再書込みを行な
えば正常に使用出来るような一時的に発生する不良（ソ
フトエラーと貯ばれる〕が注目されている。例えば微弱
な放射線によるノイズによる誤動作などがこれに含まれ
る。半導体製造技術の進歩によりダイナミックメモリ素
子そのものの物理的な要因による破壊にもとすくハード
エラーは減少しており、この為前記ソフトエラーのｓ＃
ｌの方が高いのが現状である。Recently, attention has been focused on temporary defects (known as soft errors) that occur in dynamic memory devices that can be used normally by rewriting.For example, this includes malfunctions caused by noise caused by weak radiation. Due to advances in semiconductor manufacturing technology, hard errors are decreasing as dynamic memory elements themselves are susceptible to destruction due to physical factors, and for this reason, the s# of soft errors is decreasing.
Currently, l is higher.
従来エラー訂正符号（ＦＣＣ）を付加してエラーな訂正
するエラー訂正機能の主たる目的はエラーを有するデー
タも訂正して処理製電に転送することであるが、最近で
は前記の如くソフトエラーの頻度が高いため記憶装置に
おいて、前記エラー訂正機能を利用して再書込みする方
式がとられて来てお９．該再書込みによって記憶装置の
信頼度は着しく向上することが期待出来る。しかしなが
ら一般には再書込みの実行は処理製蓋に対して記憶装置
の使用率の低下を招く欠点がある。Conventionally, the main purpose of the error correction function, which corrects errors by adding an error correction code (FCC), is to correct data with errors and transfer it to the processing equipment, but recently, as mentioned above, the frequency of soft errors has increased. 9. Since the error is high, a method of rewriting using the error correction function has been adopted in storage devices. It can be expected that the reliability of the storage device will be significantly improved by this rewriting. However, rewriting generally has the drawback of reducing the usage rate of the storage device for processing lids.
本発明の目的は前記欠点を除くため記憶装置の使、吊車
を低下させることなく再書込みを実行することが出来る
メモリ再書込み方式を提供することにある。そしてその
ために本発明＃′ｉ、ダイナミックメモリ素子によｐ構
成され且つエラー訂正機能を有する記憶装置において、
エラーを検出してデータ再書込みｔ行なう場合ダイナミ
ックメモリ素子のリフレッシュサイクルを利用すること
ｔ−＊徴とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a memory rewriting method that can perform rewriting without degrading the use of a storage device or suspending the suspension wheel, in order to eliminate the above-mentioned drawbacks. To this end, the present invention #'i is a storage device configured with dynamic memory elements and having an error correction function.
When an error is detected and data is rewritten t, it is assumed that a refresh cycle of the dynamic memory element is used.
ダイナミックメモリはその性質上必ずり７レツシーサイ
クルと叶はれる処理装置より見れば無駄な動作を心壁と
する為該無駄な動作時間を利用して再書込みｔ実行する
ことが可能である。一般にリフレッシュサイクルの周期
は１７１００秒のオーダーで実行されるため最近のシフ
トエラーの発生頻基に対しては十分な効果會得ることが
出来る。Dynamic memory, by its nature, always takes seven receivable cycles.From the perspective of a processing device, it is possible to perform rewriting using the wasted operation time, since it is concerned with wasted operations. Generally, the period of the refresh cycle is executed on the order of 17,100 seconds, so that a sufficient effect can be obtained against the recent frequent occurrence of shift errors.
以下図面に従い詳細に説明する。図は本発明の一実施例
を示す回路のブロック図でおる。ＩＵ処理装置、２，３
．４は切替回路、ｓＦｉ記憶装置。A detailed explanation will be given below according to the drawings. The figure is a block diagram of a circuit showing one embodiment of the present invention. IU processing device, 2,3
．． 4 is a switching circuit and an sFi storage device.
６はエラーアドレス保持回路、７＃′ｉエラー７ラグレ
ジスタ、８１１−１：エラー検出訂正回路、９は一致回
路、１０はデータ保持回路、１１はリフレッシ為制御回
路、１２はタイミング制御回路、１３はＡＮＤ回路でる
る。処理装ｍｘ゛よりアドレス信号用に１４と１５の信
号線２系列がありいずれも通常動作時に用いられるアド
レス用であるが１信号Ｉｗ１５のアドレス系はり７し、
シーに関係するアドレスである。又データの入出力用に
信号線】６゜】７があり信号線１６は処理装置１より送
出され記憶装置５に入力するデータ入力用で信号線】７
は記憶装置５より読み出され処理装置】に入力するデー
タ出力用である。通常動作時は切替回路２゜３．４Ｆｉ
すべて処理装置１よりの信号線１４，１５゜１６側に接
続され記憶装置５は処理装置１からのアドレス、データ
が選択され処理装置ｉｔ】の要求に従りて動作する。記
憶装置５から読出されたデータはエラー検出訂正回路８
によりエラーがあれば訂正され信号線１７を経て処理装
置１に送られもり７し、シュ時はりフレッシュ制御回路
】１の制御ｌｌにより切替回路３ｒ！信号ａ１８側に接
続されり７し、シュ回路１１よりのりフレクシ：Ｌｉ号
−リフレッシュアドレスにより記憶装置５はリフレッシ
為動作を行なう。この時信号線】４のアドレス：１１：
系はリフレッシュ動作には無関係であり切換回路は動作
を要求されない、又記憶装置への書込みは禁止される。6 is an error address holding circuit, 7#'i error 7 lag register, 811-1: error detection and correction circuit, 9 is a coincidence circuit, 10 is a data holding circuit, 11 is a refresh control circuit, 12 is a timing control circuit, 13 is an AND circuit. There are two signal lines 14 and 15 for address signals from the processing unit mx', both of which are for addresses used during normal operation, but the address system line of 1 signal Iw15 is 7,
This is an address related to the sea. There is also a signal line ]6゜]7 for inputting and outputting data, and a signal line 16 is a signal line ]7 for inputting data sent from the processing device 1 and input to the storage device 5.
is for outputting data read from the storage device 5 and input to the processing device. During normal operation, switching circuit 2゜3.4Fi
All are connected to the signal lines 14, 15, and 16 from the processing device 1, and the storage device 5 selects addresses and data from the processing device 1 and operates according to requests from the processing device it. The data read from the storage device 5 is sent to the error detection and correction circuit 8.
If there is an error, it is corrected and sent to the processing device 1 via the signal line 17, and then the switching circuit 3r! It is connected to the signal a18 side, and the storage device 5 performs a refreshing operation according to the flexi:Li number-refresh address from the flash circuit 11. At this time, the address of signal line ]4: 11: The system is unrelated to the refresh operation, the switching circuit is not required to operate, and writing to the storage device is prohibited.
記憶装置５より読出されたデータにエラーがあシェラ−
検出訂正回路８にょシ駁エラーが検出されると、エラー
検出訂正回ｊｉｉｉｉ８よりエラー検出信号がエラー７
ラグレジスタ７に送られエラーが存在した事がレジスタ
７にセットされる。同時にエラーアドレス保持回路６に
本信号が送られ、その時のエラーアドレスがアドレス保
持回路６にセ。There is an error in the data read from the storage device 5.
When an error is detected in the detection and correction circuit 8, the error detection signal is output from the error detection and correction circuit jiii8.
The signal is sent to the lag register 7, and the presence of an error is set in the register 7. At the same time, this signal is sent to the error address holding circuit 6, and the error address at that time is stored in the address holding circuit 6.
トされる。一致回路９１−ｔエラーアドレス保持回路６
のアドレスの一部とリフ・レッジ、制御１回路１１のア
ドレスを比較し一致する′とＡＮＤ回路１３へ信号を送
出する回路である。ＡＮＤ回路】３けエラーフラグレジ
スタ７よりエラーが発生していること、一致回路９より
り７し、シ、制御１回路から送ｄされているアドレスが
エラーの存在するアドレスと一致していること、リフレ
ッシ、制御回路１１よりリフレッシュサイクルであるこ
との３条作の揃ったφでゲートを開き切替回路２ｔ−エ
ラーアドレス保持す路６側へ、切替回路４をエラー検出
訂正ｌ！２１路８よシェラ−検出時のエラー訂正済のデ
ータ１＝顎しているデータ保持回路１ｏ側え切替えると
共にタイミング制御回路１２を駆動して記憶装置５へ書
込み制御信号を送る。リフレッシュは通常は読出しモー
ドで動作しているが、前記条件の成立によシ再畳込み時
には前記書込み制御信号により書込みが行なわれる。こ
のとき記憶装置５には切替回路２よりエラーアドレス保
持回路６の出力が又切替回路４よりはデータ保持回路１
゜の出力が夫々入力するため正しいデータの再書込みを
すると共にリフレッシュＬは自動釣に遂行される０
以上説明した如く本発明はダイナミックメモリが必要と
するりフレッシュサイクル時にソフトエラーを訂正して
再書込みを行なうことが出来るため記憶装置の使用率を
低下させることなくエラーデータの訂正を行なうことが
出来ダイナミックメモリ素子を用いた記憶Ｉ！置の信和
此を著しく向上させることが出来る。will be played. Matching circuit 91-t error address holding circuit 6
This circuit compares a part of the address of the refrigeration control circuit 11 with the address of the control 1 circuit 11, and sends a signal to the AND circuit 13 if they match. AND circuit] The 3-digit error flag register 7 indicates that an error has occurred, the match circuit 9 indicates that an error has occurred, and the address sent from the control 1 circuit matches the address where the error exists. , Refresh, The control circuit 11 opens the gate at φ when the three lines are completed indicating that it is a refresh cycle, and the switching circuit 2t--to the path 6 side that holds the error address, switches the switching circuit 4 to error detection and correction l! 21 path 8, error corrected data at the time of Scherrer detection 1 = data holding circuit 1o is switched to the side, and the timing control circuit 12 is driven to send a write control signal to the storage device 5. Refresh normally operates in read mode, but when the above conditions are satisfied, writing is performed by the write control signal at the time of reconvolution. At this time, the output of the error address holding circuit 6 is sent to the storage device 5 from the switching circuit 2, and the output from the data holding circuit 1 is sent from the switching circuit 4 to the storage device 5.
Since the outputs of ゜ are respectively input, the correct data is rewritten and the refresh L is performed automatically. Since it is possible to perform writing, error data can be corrected without reducing the usage rate of the storage device. Storage using dynamic memory elements I! Nobukazu of the position can significantly improve this.
図は本発明の一実施例を示す回路のブロック図である。
１は処理装置、２，３．４は切替回路。
５は記憶装置、６はエラーアドレス保持回路、７はエラ
ーフラグレジスタ、８はエラー検出訂正回路、９は一致
回路、１０はデーＩ保持回路、】１はリフレッシュ制御
回路、１２はタイイング制御回路である。The figure is a block diagram of a circuit showing one embodiment of the present invention. 1 is a processing device, and 2, 3.4 are switching circuits. 5 is a storage device, 6 is an error address holding circuit, 7 is an error flag register, 8 is an error detection and correction circuit, 9 is a coincidence circuit, 10 is a data I holding circuit, ] 1 is a refresh control circuit, and 12 is a tying control circuit. be.
Claims (1)
機能を有する記憶装置において、エラーを検出してデー
タ再書込みを行なう場合ダイナミ、クメモリ素子のりフ
レッシュサイクルを利用することを特徴とするメモリ再
書込み方式。1. A memory rewriting method which uses a dynamic memory element refresh cycle when detecting an error and rewriting data in a storage device configured with dynamic memory elements and having an error correction function.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56161262A JPS5862891A (en) | 1981-10-09 | 1981-10-09 | Memory rewrite system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56161262A JPS5862891A (en) | 1981-10-09 | 1981-10-09 | Memory rewrite system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5862891A true JPS5862891A (en) | 1983-04-14 |
Family
ID=15731749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56161262A Pending JPS5862891A (en) | 1981-10-09 | 1981-10-09 | Memory rewrite system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5862891A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61117788A (en) * | 1984-11-13 | 1986-06-05 | Fujitsu Ltd | Method and device for refreshing and data checking of semiconductor memory |
| JPS61123957A (en) * | 1984-11-21 | 1986-06-11 | Nec Corp | Storage device |
| US5055541A (en) * | 1989-06-27 | 1991-10-08 | Sequa Chemicals, Inc. | Starch polymer graft composition and method of preparation |
| EP2455942A3 (en) * | 2010-11-18 | 2013-01-09 | Grandis, Inc. | Memory write error correction circuit |
-
1981
- 1981-10-09 JP JP56161262A patent/JPS5862891A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61117788A (en) * | 1984-11-13 | 1986-06-05 | Fujitsu Ltd | Method and device for refreshing and data checking of semiconductor memory |
| JPS61123957A (en) * | 1984-11-21 | 1986-06-11 | Nec Corp | Storage device |
| US5055541A (en) * | 1989-06-27 | 1991-10-08 | Sequa Chemicals, Inc. | Starch polymer graft composition and method of preparation |
| EP2455942A3 (en) * | 2010-11-18 | 2013-01-09 | Grandis, Inc. | Memory write error correction circuit |
| US8456926B2 (en) | 2010-11-18 | 2013-06-04 | Grandis, Inc. | Memory write error correction circuit |
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