JPS5857192A - Liquid crystal display system - Google Patents
Liquid crystal display systemInfo
- Publication number
- JPS5857192A JPS5857192A JP15524381A JP15524381A JPS5857192A JP S5857192 A JPS5857192 A JP S5857192A JP 15524381 A JP15524381 A JP 15524381A JP 15524381 A JP15524381 A JP 15524381A JP S5857192 A JPS5857192 A JP S5857192A
- Authority
- JP
- Japan
- Prior art keywords
- display
- liquid crystal
- screen
- memory
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、゛ドツトマトリックス構造を持った時分割駆
動方式による液晶パネル、４Ｉにライン走査形の単純マ
トリックスアドレス方式による電圧平均化法を用いた液
晶パネルＪこおける弐示像の中間調が簡単に表示できる
表示方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention is a liquid crystal panel using a time-division driving method having a dot matrix structure, and a liquid crystal panel J using a voltage averaging method using a line scanning simple matrix addressing method for 4I. The present invention relates to a display method that can easily display halftones of an image.
電圧平均化法を用いた単純マトリックスアドレス方式に
よる液晶パネルの中間調表示には、従来パルス幅変調方
式がある。これは、信号電極側の駆動波形のパルス幅を
変調して、中間調を表示するもので、テレビジ１ン画儂
表示などに用いられる。この方式はテレビジ冒ン表示な
どには有効であるが、文字表示などに用いられる小形の
パネルに使用する奢こは駆動パルス幅変調回路を要し、
駆動回路が複雑となる。There is a conventional pulse width modulation method for displaying halftones on a liquid crystal panel using a simple matrix addressing method using a voltage averaging method. This modulates the pulse width of the drive waveform on the signal electrode side to display halftones, and is used for displaying single picture images on television. This method is effective for displaying television screens, etc., but it requires a drive pulse width modulation circuit for small panels used for character display, etc.
The drive circuit becomes complicated.
本発明はかかる点に鑑みなされたもので、簡単な回路構
成で中間調表示ができる液晶表示方式を提供することを
目的とする。The present invention has been made in view of the above, and an object of the present invention is to provide a liquid crystal display system that can display halftones with a simple circuit configuration.
第１図は液晶表示装置構成図であって、ドツトマトリッ
クス配列の画素を有する液晶パネル１のＹ電極側駆動回
路２、Ｘ電極側駆動回路３を具え、１ＪＥ２ＦＩ！Ｊに
示ＴようＩζ７本のＹ電極Ｙ、〜Ｙ、Ｊこは線順次走査
駆動方式により駆動パルス電圧が加えられる。FIG. 1 is a configuration diagram of a liquid crystal display device, which includes a Y electrode side drive circuit 2 and an X electrode side drive circuit 3 of a liquid crystal panel 1 having pixels in a dot matrix arrangement. As shown in J, a drive pulse voltage is applied to the seven Y electrodes Y, - Y, J by a line sequential scanning drive method.
第３図は表示制御回路構成図であって、４は文字コード
メモリ、５は中ヤラクタジェネレータ、６は文字パター
ンアドレスカウンタである。マイクロブ四セッサ（ＭＰ
Ｕ）等から送出される２表示面分の文字コード情報は文
字コードメモリ４の領域４ｈ４．に各々蓄えられる。キ
ャラクタジェネレータ５からは文字コードメモリの第１
の領域４ｍの文字コードに対応した表示データを文字パ
ターンアドレスカウンタ６で指定される（ドツトマトリ
ックス画素の）列画素のデータ信号として出力される◎
このデータ信号はＸ電極側駆動回路３へ入力される。こ
の操作の繰り返し憂こよってｔず、文字コードメモリ４
の第１の領域４．にある文字コード情報が第４図（ａ）
４こ示すようにパネルに表示される。このようにして
第２図に示すように画面表示ｌが完了Ｔる。つづいて同
様の操作により文字コードメモリの第２の領域にある文
字コード情報が第４図（ｂ）のようにパネルに表示され
、第２図に示す如く画面表示２が完了Ｔる。FIG. 3 is a block diagram of a display control circuit, in which 4 is a character code memory, 5 is a middle-order generator, and 6 is a character pattern address counter. Microbe foursessor (MP
The character code information for two display screens sent from the areas 4h4. are stored in each. From character generator 5, the first character code memory
The display data corresponding to the character code in the area 4m is output as the data signal of the column pixel (of the dot matrix pixel) specified by the character pattern address counter 6.
This data signal is input to the X electrode side drive circuit 3. If you repeat this operation repeatedly, the character code memory 4
The first area of 4. The character code information in Figure 4 (a)
4 will be displayed on the panel as shown here. In this way, the screen display I is completed as shown in FIG. Subsequently, by the same operation, the character code information in the second area of the character code memory is displayed on the panel as shown in FIG. 4(b), and screen display 2 is completed as shown in FIG. 2.
収装、この操作を繰返して画面表１と２を交互に行うと
第４図（Ｃ）のようにオペレータの月番こは視覚的に３
階調の文字パターンが表示される。If you repeat this operation and alternate between screens 1 and 2, the operator's month number will visually change to 3 as shown in Figure 4 (C).
A gradation character pattern is displayed.
対応する情報を蓄え、この情報を前述の如く順次表示す
れば表示階調を増加できる０
な詔メモリとして１ｓ５図に示すようｌこ表示ノ１ネル
の１画素に対応して割尚てられた記憶領域を有するＩリ
ーンメ毫す７を用い、このメそり７に複数表示面分の表
示情報を蓄えて、表示ノ（ネルに交互に表示するように
すれば中間調を有する画像表示が可能となる◎
第５＠において８．９は各々マトリックス状ξこ配され
た画素のｘｉｔｉａよびＹＩｌアドレスカウンタ、１０
はパターンメモリのアドレスを指定するアドレスセレク
タである。The display gradation can be increased by storing the corresponding information and sequentially displaying this information as described above.As shown in Figure 1s5, this memory is allocated to correspond to one pixel in the display channel. By using an I-lean screen 7 having a storage area, storing display information for multiple display screens in the screen 7 and displaying it alternately on the display panel, it is possible to display an image with intermediate tones. ◎ In the 5th @, 8.9 is the xitia and YIl address counter of each pixel arranged in a matrix, 10
is an address selector that specifies the address of the pattern memory.
さらに第６図に示すようにメモリ１１に階調データを記
憶させておき、１ｉｉｉ面アドレスカウン・り１２の指
示に従りてこの階調データを読出し、デコーダでデコー
ドして表示データとしてＸ電極側駆動回路へ送出Ｔるよ
うにＴればメモリ１１内を複数両面分−こ応じて分割す
る必要がなくメモリ容量が少なくて済む。Further, as shown in FIG. 6, gradation data is stored in the memory 11, read out in accordance with instructions from the 1iii plane address counter 12, decoded by a decoder, and displayed on the X electrodes as display data. If T is sent out to the side drive circuit, there is no need to divide the inside of the memory 11 for a plurality of both sides, and the memory capacity can be reduced.
以上の説明から明らかなように本発明ｌこ係る液晶表示
方式は、複数組の表示偉を交互に表示面に表示し、その
合成音こより中間調表示を行うため液晶パネル駆動回路
が簡単になる。As is clear from the above description, the liquid crystal display method of the present invention alternately displays multiple sets of display signals on the display screen, and displays the intermediate tone from the synthesized sound, which simplifies the liquid crystal panel drive circuit. .
第１図は本発明の一実施例構成図、第２図は走査信号図
、第３図は駆動信号発生回路図、第４図（ａ）〜（ｅ）
は表示パターン図、第５図、第６図は本発明の他の実施
例回路構成図である。
１：パネル、２：Ｘ電極側駆動回路、３：Ｘ電極側駆動
回路、４：文字コードメモリ、５：キャラクタジェネレ
ータ、６：アドレスカウンタ。
渾１図
算２図
算 ３躬
羊 ４ 目
第 ５ 図
琴６ｙＩ
２Fig. 1 is a configuration diagram of an embodiment of the present invention, Fig. 2 is a scanning signal diagram, Fig. 3 is a drive signal generation circuit diagram, and Figs. 4 (a) to (e).
5 is a display pattern diagram, and FIGS. 5 and 6 are circuit configuration diagrams of other embodiments of the present invention. 1: Panel, 2: X electrode side drive circuit, 3: X electrode side drive circuit, 4: Character code memory, 5: Character generator, 6: Address counter. Arm 1 Illustration 2 Illustration 3 The sheep 4th eye 5 Zukoto 6yI 2
Claims (1)
回路を備えた表示装置において複数の画面データを記憶
するメモリとそのメモリデータを選択Ｔる制御回路によ
り、複数画面の表示データを順次一画面づつ前記液晶パ
ネルに表示して、複数画面の表示データを適宜間引くこ
とにより、画面表示のデユーティを変えて、複数階調の
中間調が表示できるようにしたことを峙微とＴる液晶表
示方式。In a display device equipped with a liquid crystal panel having a dot matrix structure and its driving circuit, a memory for storing multiple screen data and a control circuit for selecting the memory data sequentially display display data for multiple screens one screen at a time. A liquid crystal display method that is unique in that it is possible to display multiple intermediate tones by changing the screen display duty by appropriately thinning out the display data of multiple screens on a liquid crystal panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15524381A JPS5857192A (en) | 1981-09-30 | 1981-09-30 | Liquid crystal display system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15524381A JPS5857192A (en) | 1981-09-30 | 1981-09-30 | Liquid crystal display system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5857192A true JPS5857192A (en) | 1983-04-05 |
Family
ID=15601657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15524381A Pending JPS5857192A (en) | 1981-09-30 | 1981-09-30 | Liquid crystal display system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5857192A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60153028A (en) * | 1984-01-23 | 1985-08-12 | Canon Inc | Image reproducing device |
| JPS6125194A (en) * | 1984-07-13 | 1986-02-04 | 株式会社 アスキ− | Display controller |
| JPH01130195A (en) * | 1987-10-09 | 1989-05-23 | Thomson Csf | System for displaying image on matrix panel in halftone |
| JPH0618854A (en) * | 1984-08-18 | 1994-01-28 | Canon Inc | Display device |
| JPH0643832A (en) * | 1992-08-17 | 1994-02-18 | Seiko Epson Corp | Liquid crystal display device |
| US5309170A (en) * | 1989-04-28 | 1994-05-03 | Hitachi, Ltd. | Half-tone representation system and controlling apparatus therefor |
| JPH08123352A (en) * | 1994-10-25 | 1996-05-17 | Rohm Co Ltd | Luminance adjusting circuit |
-
1981
- 1981-09-30 JP JP15524381A patent/JPS5857192A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60153028A (en) * | 1984-01-23 | 1985-08-12 | Canon Inc | Image reproducing device |
| JPS6125194A (en) * | 1984-07-13 | 1986-02-04 | 株式会社 アスキ− | Display controller |
| JPH0618854A (en) * | 1984-08-18 | 1994-01-28 | Canon Inc | Display device |
| JPH01130195A (en) * | 1987-10-09 | 1989-05-23 | Thomson Csf | System for displaying image on matrix panel in halftone |
| US5309170A (en) * | 1989-04-28 | 1994-05-03 | Hitachi, Ltd. | Half-tone representation system and controlling apparatus therefor |
| JPH0643832A (en) * | 1992-08-17 | 1994-02-18 | Seiko Epson Corp | Liquid crystal display device |
| JPH08123352A (en) * | 1994-10-25 | 1996-05-17 | Rohm Co Ltd | Luminance adjusting circuit |
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