JPS585611B2 - Lonely Cairo - Google Patents
Lonely CairoInfo
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- JPS585611B2 JPS585611B2 JP6997575A JP6997575A JPS585611B2 JP S585611 B2 JPS585611 B2 JP S585611B2 JP 6997575 A JP6997575 A JP 6997575A JP 6997575 A JP6997575 A JP 6997575A JP S585611 B2 JPS585611 B2 JP S585611B2
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- fet
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-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
この発明は絶縁ゲート電界効果トランジスタ（Ｉｎｓｕ
ｌａｔｅｄ Ｇａｔｅ Ｆｉｅｌｄ ＥｆｆｅｃｔＴｒ
ａｎｓｉｓｔｏｒ略してＩＧＦＥＴあるいはＭＯＳＦＥ
Ｔと称するが以後ＦＥＴと略記する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (Insu
rated Gate Field EffectTr
ansistor (abbreviated as IGFET or MOSFE)
Although it is called T, it will be abbreviated as FET hereafter.
）を用いた論理回路に関する。) related to logic circuits using
従来，ＦＥＴを用いた論理回路としてたとえば第１図に
示す様なＰチャネル形（以後Ｐ形という）ＦＥＴとＮチ
ャネル形（以後Ｎ形という）ＦＥＴとを組合わせた相補
対称型のＦＥＴ回路が構成されている。Traditionally, logic circuits using FETs include complementary symmetrical FET circuits that combine a P-channel type (hereinafter referred to as P-type) FET and an N-channel type (hereinafter referred to as N-type) FET, as shown in Figure 1. It is configured.
第１図は入力信号Ａ，Ｂに対してＡ・Ｂ＋Ａ・Ｂなる反
一致出力信号を得る論理回路で，いわゆるＥｘｃｌｕｓ
ｉｖｅＯＲ回路としてたとえば電子計算機の演算回路や
加算機に使用されるものである。Figure 1 shows a logic circuit that obtains an anti-coincidence output signal of A, B + A, B for input signals A and B, which is a so-called exclusive circuit.
The iveOR circuit is used, for example, in an arithmetic circuit or an adder of an electronic computer.
したがって，システム全体で使用している半導体数を低
減し．かつ低消費電力化，低価格化を実現することが，
上記論理回路においても当然に課せられた目的となって
いる。Therefore, the number of semiconductors used in the entire system can be reduced. In addition, achieving lower power consumption and lower prices is
This is naturally the objective imposed on the above logic circuit as well.
第１図の論理回路について説明する前に、ＦＥＴに関し
て説明すると，Ｐ形ＦＥＴもＮ形ＦＥＴも半導体の内部
あるいは表面の電流通路（チャネル）の導電度を電流方
向と直展する電界により制御する能動３端子素子で，前
者が正孔をキャリアとしているのに対し後者は電子をキ
ャリアとしてソース−ドレイン間に電流が流れる。Before explaining the logic circuit in Figure 1, let me explain about FETs. Both P-type FETs and N-type FETs control the conductivity of a current path (channel) inside or on the surface of a semiconductor by an electric field that extends directly to the current direction. It is an active three-terminal device, and while the former uses holes as carriers, the latter uses electrons as carriers and current flows between the source and drain.
一般にＥＦＴのソース，ドレインはバイポーラ素子（ト
ランジスタ）のコレクタ，エミツタのように電極構造上
の違いはほとんどない両方向性の素子であり，ソース，
ドレインの区別は回路動作上で表われる。In general, the source and drain of an EFT are bidirectional elements with almost no difference in electrode structure, like the collector and emitter of a bipolar element (transistor).
The distinction between drains appears in circuit operation.
ここではＰ形ＦＥＴとＮ形ＦＥＴとの相補対称型回路な
ので，出力側をドレインとし，バイアス電源側（接地側
）をソースとする。Since this is a complementary symmetrical circuit of a P-type FET and an N-type FET, the output side is the drain, and the bias power supply side (ground side) is the source.
そしてＶＤＤを正電源．ＶＳＳを負電源（接地）とし，
動作説明上，ＶＤＤを「１」レベルの電位．ＶＳＳを「
０」レベルの電位とし．いわゆる正論理を用いることに
する。And VDD is the positive power supply. Set VSS as a negative power supply (ground),
To explain the operation, VDD is set to a "1" level potential. VSS as “
0" level potential. We will use so-called positive logic.
第１図において，Ｐ形ＦＥＴ１１，１２は電源端子１と
出力端子２との間に直列接続され，さらにＰ形ＦＥＴ１
３，１４の直列回路が同様に配置され，電源端子３と出
力端子２との間にはＮ形ＦＥＴ１５，１６の直列回路と
Ｎ形ＦＥＴ１７，１８の直列回路とが並列に設けられて
いる。In FIG. 1, P-type FETs 11 and 12 are connected in series between power supply terminal 1 and output terminal 2, and P-type FET 1
3 and 14 are similarly arranged, and between the power supply terminal 3 and the output terminal 2, a series circuit of N-type FETs 15 and 16 and a series circuit of N-type FETs 17 and 18 are provided in parallel.
入力端子４，５には，それぞれ入力信号Ａ，Ｂが供給さ
れており，入力端子４はＦＥＴ１２，１５のゲート電極
と直接接続されかつインバータ６を介してＦＥＴ１４，
１７のゲート電極と接続されるとともに．入力端子５は
ＦＥＴ１３，１６と直接接続されかつインバータ７を介
してＦＥＴ１１，１８と接続される。Input signals A and B are supplied to input terminals 4 and 5, respectively.
It is connected to the gate electrode of 17. Input terminal 5 is directly connected to FETs 13 and 16 and connected to FETs 11 and 18 via inverter 7.
なお．インバータ６，７はいずれも２個のＦＥＴによっ
て構成される回路であり、上記出力端子２からは出力信
号Ｓ＝Ａ・Ｂ＋Ａ・Ｂの反一致出力が得られる。In addition. The inverters 6 and 7 are both circuits composed of two FETs, and the output terminal 2 provides an anticoincidence output of the output signal S=A.B+A.B.
すなわち，入力信号がＡ＝０，Ｂ＝０であればＰ形ＦＥ
Ｔ１２，１３はオン（導通状態）し、Ａ＝Ｂ＝１である
からＮ形ＦＥＴ１７，１８もオンし，他のＦＥＴがオフ
（非導通状態）となるので．出力信号Ｓは「０」レベル
となる。In other words, if the input signals are A=0 and B=0, the P-type FE
T12 and 13 are on (conducting state), and since A=B=1, N-type FETs 17 and 18 are also on, and the other FETs are off (non-conducting state). The output signal S becomes "0" level.
また入力信号がＡ＝１，Ｂ＝０であればＡ＝０、Ｂ＝１
でありＦＥＴ１３，１４お・よび１５，１８がオンして
，出力信号Ｓは「１」レベルとなる。Also, if the input signal is A=1, B=0, then A=0, B=1
Therefore, FETs 13, 14 and 15, 18 are turned on, and the output signal S becomes "1" level.
また入力信号がＡ＝０，Ｂ＝１であればＡ＝１，Ｂ＝０
であってＦＥＴ１１，１２およびＦＥＴ１６，１７がオ
ンして，出力信号Ｓは「１」レベルになる。Also, if the input signals are A=0, B=1, then A=1, B=0
Then, FETs 11 and 12 and FETs 16 and 17 are turned on, and the output signal S becomes "1" level.
また入力信号がＡ＝１，Ｂ＝１であればＡ＝Ｂ＝０であ
ってＦＥＴ１１，１４およびＦＥＴ１５，１６がオンし
，出力信号Ｓは「０」レベルになる。Further, if the input signals are A=1 and B=1, A=B=0, FETs 11 and 14 and FETs 15 and 16 are turned on, and the output signal S becomes the "0" level.
第１表はこうした反一致回路動作をまとめて示した真理
値表であり，合計１２個のＦＥＴで構成した第１図の論
理回路によって達成されることが示された。Table 1 is a truth table summarizing these anti-coincidence circuit operations, and it is shown that they can be achieved by the logic circuit shown in FIG. 1, which is composed of a total of 12 FETs.
ところが，上記論理回路では２個１組の直列ＦＥＴ回路
を４組使用して入力信号の４通りのそれぞれの場合に各
直列ＦＥＴ回路が選択的に導通するようにしているから
．ゲート制御のための２つのインバータを含め１２個も
のＦＥＴを必要としているのであって，集積回路化した
場合に構成素子（ＦＥＴ）数が多ければ単位論理機能回
路のチップ状での占有面積が増大し．良品率の低下を招
くとともに製造コストの増大の原因となる。However, in the above logic circuit, four sets of two series FET circuits are used so that each series FET circuit is selectively turned on in each of the four types of input signals. As many as 12 FETs are required, including two inverters for gate control, and if the number of components (FETs) increases when integrated into a circuit, the area occupied by the unit logic function circuit in chip form increases. death. This causes a decrease in the non-defective product rate and an increase in manufacturing costs.
また，ＦＥＴはＰＮ接合部に印加される逆方向電圧によ
って一般には数ＰＡ〜数ｎＡ程度の個有のリーク電流が
生じるから．論理回路を構成するＦＥＴの数が多ければ
多いほど消費電力が増大するという不都合があり、上記
の点とともに素子数の減少が望まれていた。In addition, FETs generally have their own leakage current of several PA to several nA due to the reverse voltage applied to the PN junction. There is a disadvantage that the larger the number of FETs constituting a logic circuit, the greater the power consumption, and in addition to the above point, it has been desired to reduce the number of elements.
この発明は上記事情に鑑みなされたもので．少ない構成
素子数で，しかも論理回路機能の多様化を実現した論理
回路を提供することを目的としている。This invention was made in view of the above circumstances. The objective is to provide a logic circuit that has a small number of components and has diversified logic circuit functions.
以下．この発明の一実施例を第２図，第３図を参照して
説明する。below. An embodiment of the present invention will be described with reference to FIGS. 2 and 3.
第２図において，正電源ＶＤＤが印加される電源端子２
１と接地電位との間には，Ｐ形ＦＥＴ２２とＮ形ＦＥＴ
２３とを直列接続した直列ＦＥＴ回路２４，Ｐ形ＦＥＴ
２５とＮ形ＦＥＴ２６とを直列接続した直列ＦＥＴ回路
２７が直列に接続されている。In Figure 2, power supply terminal 2 to which positive power supply VDD is applied
1 and the ground potential, a P-type FET 22 and an N-type FET are connected.
23 is connected in series with the series FET circuit 24, P-type FET
25 and an N-type FET 26 are connected in series.
各直列ＦＥＴ回路２４，２７はそれぞれＦＥＴ２２，２
３およびＦＥＴ２５，２６のゲート電極を共通接続し．
入力信号Ａが供給される入力端子２８に接続され．直列
ＦＥＴ回路２４，２７の接続点は入力信号Ｂが供給され
る入力端子２９に接続される。Each series FET circuit 24, 27 has FET 22, 2, respectively.
3 and the gate electrodes of FETs 25 and 26 are commonly connected.
connected to an input terminal 28 to which input signal A is supplied. A connection point between the series FET circuits 24 and 27 is connected to an input terminal 29 to which input signal B is supplied.
上記直列ＦＥＴ回路２４，２７を構成するＰ形ＦＥＴ２
２と２５はサブストレート（基板）が正電源ＶＤＤ側つ
まりソースと直結されており．またＮ形ＦＥＴ２３と２
６もサブストレートが接地側つまりソースと直結され．
直列ＦＥＴ回路２４，２７の出力端子すなわち各ＦＥＴ
２２，２３，２５，２６のドレインとサブストレートと
の間は結線せず寄生的にダイオードＤ１〜Ｄ４を介在さ
せることとし．いずれのダイオードＤ１〜Ｄ４も電源端
子２１と接地との間で逆極性をなすように構成している
。P-type FET 2 constituting the series FET circuits 24 and 27
The substrates of 2 and 25 are directly connected to the positive power supply VDD side, that is, the source. Also, N type FET23 and 2
In 6, the substrate is directly connected to the ground side, that is, the source.
Output terminals of series FET circuits 24 and 27, that is, each FET
The drains of 22, 23, 25, and 26 are not connected to the substrate, but diodes D1 to D4 are interposed parasitically. Each of the diodes D1 to D4 is configured to have opposite polarity between the power supply terminal 21 and the ground.
また，上記電源端子２１と上記直列ＦＥＴ回路２７の出
力端子との間には，Ｐ形ＦＥＴ３０とＮ形ＦＥＴ３１と
を直列接続した直列ＦＥＴ３２が設けられ，この直列Ｆ
ＥＴ３２の入力端子には上記直列ＦＥＴ回路２４の出力
端子が接続されることにより．上記ＦＥＴ３０と３１と
の接地点からは反一致出力Ｓ１が出力端子３３に出力さ
れるようになっている。Further, a series FET 32 is provided between the power supply terminal 21 and the output terminal of the series FET circuit 27, and the series FET 32 is formed by connecting a P-type FET 30 and an N-type FET 31 in series.
By connecting the output terminal of the series FET circuit 24 to the input terminal of the ET32. An anticoincidence output S1 is output from the ground point of the FETs 30 and 31 to an output terminal 33.
なお，端子３４，３５はそれぞれ直列ＦＥＴ回路２４，
２７の出力端子と接続される。Note that the terminals 34 and 35 are the series FET circuits 24 and 35, respectively.
27 output terminals.
そしてＦＥＴ３０，３１に於てもサブストレートとソー
スとの間は直結され．直結しないサブストレート−ドレ
イン間に寄生的に介在するダイオードＤ５、Ｄ６はＤ１
〜Ｄ４の場合と同様電源ＶＤＤに対して逆極性をなして
いる。Also in FETs 30 and 31, the substrate and source are directly connected. Diodes D5 and D6 parasitically interposed between the substrate and drain, which are not directly connected, are connected to D1.
~ As in the case of D4, the polarity is opposite to the power supply VDD.
第３図は上記実施例の論理回路を具体的にＳＯＳ（シリ
コンオンサファイヤ）のＭＯＳ型集積回路で構成した場
合の断面構造図である。FIG. 3 is a cross-sectional structural diagram of the logic circuit of the above embodiment specifically constituted by an SOS (silicon on sapphire) MOS type integrated circuit.
図中、３６はサファイヤ基板であり，この基板上に例え
ばヘテロエピタキシャル成長させた薄いシリコン層を設
けて，不要部分のシリコンをエッチング除去することに
より前記ＦＥＴ２２，２３，２５，２６，３０，３１を
形成している。In the figure, numeral 36 is a sapphire substrate, and the FETs 22, 23, 25, 26, 30, and 31 are formed by providing a thin silicon layer grown by, for example, heteroepitaxial growth on this substrate, and removing unnecessary silicon by etching. are doing.
基板３６は絶縁基板であればよくたとえばスピネルなど
も使用され．通常のＭＯＳＩＣ，ＣＭＯＳなどとは異な
り個々のトランジスタは容易に電気的に分離でき．回路
は小型化されかつ消費電力量も低減する。The substrate 36 may be any insulating substrate, such as spinel. Unlike ordinary MOSIC, CMOS, etc., individual transistors can be easily separated electrically. The circuit is smaller and consumes less power.
なお、３７はシリコン酸化膜であり，この上にゲート電
極．ソース．ドレイン電極がたとえばアルミニウムなど
の金属層によって形成される。Note that 37 is a silicon oxide film, on which a gate electrode is formed. sauce. A drain electrode is formed by a metal layer, such as aluminum.
上記各ＦＥＴのサブストレートとドレインとの間に破線
で示されたダイオードＤ１〜Ｄ６が介在するのは，サブ
ストレートとソースの領域をたとえば基板３６の面上で
，あるいはＦＥＴの側面部で導電体を用いて結線するこ
とにより寄生的に形成されてくるからである。The reason why the diodes D1 to D6 shown by broken lines are interposed between the substrate and the drain of each FET is that the substrate and source regions are connected to a conductor on the surface of the substrate 36 or on the side surface of the FET. This is because the wires are formed parasiticly by connecting the wires using the wire.
第８図では、ＦＥＴ，端子類をすべて第２図と対応させ
て同一符号で示しており，各端子とＦＥＴの電極との接
続関係も同時に模式的に示した。In FIG. 8, the FET and terminals are all indicated by the same reference numerals in correspondence with those in FIG. 2, and the connection relationship between each terminal and the electrode of the FET is also schematically shown.
次に第２図論理回路の動作について説明する。Next, the operation of the logic circuit shown in FIG. 2 will be explained.
たとえば今．入力端子２８，２９にそれぞれ入力信号Ａ
、ＢがＡ＝０，Ｂ＝０のレベルで供給された場合，出力
端子３３にあらわれる出力信号Ｓ１がどうなるかについ
て考える。For example, now. Input signal A to input terminals 28 and 29, respectively.
, B are supplied at the levels of A=0 and B=0, what happens to the output signal S1 appearing at the output terminal 33 will be considered.
直列ＦＥＴ回路２４のＰ形ＦＥＴ２２は導通状態，Ｎ形
ＦＥＴ２３は非導通状態となるから．直列ＦＥＴ回路２
４の出力端子すなわち端子３４にあらわれる出力信号Ｓ
２は「１」レベルとなる。The P-type FET 22 of the series FET circuit 24 is in a conductive state, and the N-type FET 23 is in a non-conductive state. Series FET circuit 2
4, that is, the output signal S appearing at the terminal 34.
2 becomes the "1" level.
また直列ＦＥＴ回路２７では，Ｐ形ＦＥＴ２５がソース
とサブストレートを直結しサブストレートの電位を「０
」としているからＮ形ＦＥＴ２６とともに非導通状態と
なっているが，ＦＥＴ２５のソース．ドレイン間に寄生
的に形成されたダイオードＤ３が順方向だから出力端子
すなわち端子３５の出力信号Ｓ３は「０」レベルとなっ
てあらわれる。In addition, in the series FET circuit 27, the P-type FET 25 directly connects the source and the substrate and sets the potential of the substrate to "0".
'', so it is in a non-conducting state along with N-type FET 26, but the source of FET 25. Since the diode D3 parasitically formed between the drains is in the forward direction, the output signal S3 at the output terminal, that is, the terminal 35, appears at the "0" level.
しかして．出力信号Ｓ２（＝１）がその入力端子に．出
力信号Ｓ３（＝０）が第２制御端子に供給される直列Ｆ
ＥＴ回路３２は，Ｐ形ＦＥＴ３０は非導通状態，Ｎ形Ｆ
ＥＴ３１は導通状態となるから出力端子３３にあらわれ
る出力信号Ｓ１は「０」レベルとなる。However. The output signal S2 (=1) is applied to its input terminal. A series F whose output signal S3 (=0) is supplied to the second control terminal
In the ET circuit 32, the P-type FET 30 is in a non-conducting state and the N-type FET 30 is in a non-conducting state.
Since ET31 becomes conductive, the output signal S1 appearing at output terminal 33 becomes "0" level.
すなわち，Ａ＝０，Ｂ＝０の入力信号状態のとき出力信
号はＳ＝０となっている。That is, when the input signal state is A=0 and B=0, the output signal is S=0.
同様に，入力信号の状態がＡ＝１，Ｂ＝０の場合．Ａ＝
０，Ｂ＝１の場合，Ａ＝１，Ｂ＝１の場合に出力信号Ｓ
１がどうなるかをまとめると，第２表に示す様になる。Similarly, if the input signal states are A=1 and B=0. A=
0, B=1, A=1, B=1, the output signal S
1 is summarized as shown in Table 2.
この第２表から入力信号Ａ，Ｂと出力信号Ｓ１、Ｓ２、
Ｓ３の関係を論理式で示すと，
Ｓ２＝Ａ・Ｂ＝Ａ＋Ｂ、Ｓ３＝Ａ・Ｂ、Ｓ１＝Ｓ２・Ｓ
３＝Ｓ２＋Ｓ３であるからＳ１＝Ａ・Ｂ＋Ａ・Ｂとなり
，前記第１表の真理値表に示される反一致回路としての
動作をしていることがわかる。From this second table, input signals A, B and output signals S1, S2,
Expressing the relationship of S3 with a logical formula, S2=A・B=A+B, S3=A・B, S1=S2・S
Since 3=S2+S3, S1=A.B+A.B, and it can be seen that the circuit operates as an anti-coincidence circuit shown in the truth table of Table 1 above.
次に第４図．第５図に示すこの発明の他の実施例につい
て説明する。Next, Figure 4. Another embodiment of the invention shown in FIG. 5 will be described.
第４図の論理回路の構成は第２図と同様に６個のＦＥＴ
で三組の直列ＦＥＴ回路２４，２７，３２を形成してな
るもので，第２図に示した実施例と同一部分には同一符
号を付している。The configuration of the logic circuit in Figure 4 is the same as in Figure 2, with 6 FETs.
In this embodiment, three series FET circuits 24, 27, and 32 are formed, and the same parts as in the embodiment shown in FIG. 2 are given the same reference numerals.
そして各ＦＥＴの配置接続関係は全く同じであるから，
入力端子２８，２９へそれぞれ入力信号Ａ，Ｂを供給し
たとき出力端子３３にあらわれる信号Ｓ１は反一致出力
となることは明らかである。And since the arrangement and connection relationship of each FET is exactly the same,
It is clear that when the input signals A and B are supplied to the input terminals 28 and 29, respectively, the signal S1 appearing at the output terminal 33 becomes an anti-coincidence output.
なお，第２図と異なる点は，直列ＦＥＴ回路２７のＰ形
ＦＥＴ２５に寄生するダイオードＤ３，Ｄ３′の他にＦ
ＥＴ２５のソース・ドレイン間にダイオードＤ７が配置
されている点であり．この実施例が第５図に示す様にＮ
型半導体基板４０上に選択拡散技術を用いて形成される
通常の相補型集積回路（Ｃ ＭＯＳ ＩＣ）としてて実
現されるものだからである。The difference from FIG. 2 is that in addition to the diodes D3 and D3' parasitic to the P-type FET 25 of the series FET circuit 27, the
The point is that a diode D7 is placed between the source and drain of ET25. In this embodiment, as shown in FIG.
This is because it is realized as a normal complementary integrated circuit (CMOS IC) formed on a type semiconductor substrate 40 using selective diffusion technology.
すなわち、第５図においてＰ形ＦＥＴ２５のサブストレ
ートは他のＰ形ＦＥＴ２２，３０とともに共通に上記Ｎ
型半導体基板４０を使用しているから．このＦＥＴ２５
のソース．ドレイン間に一方向でダイオードＤ３が寄生
的に形成されず，第２図に示す実施例のダイオードＤ３
に対応するものをＮ形ＦＥＴ３１を形成しているＰウエ
ル領域４１にあらためてＮ＋形拡散領域４２を設けるこ
とによって上記ダイオードＤ７として形成しなくてはな
らない。That is, in FIG. 5, the substrate of the P-type FET 25 and the other P-type FETs 22 and 30 are commonly
This is because a type semiconductor substrate 40 is used. This FET25
Source of. The diode D3 is not parasitically formed in one direction between the drains, and the diode D3 of the embodiment shown in FIG.
The diode D7 must be formed by newly providing an N+ type diffusion region 42 in the P well region 41 forming the N type FET 31.
つまり第２図の場合の様にＰ形ＦＥＴ２５のサブストレ
ート電位をそのソース電位と等しくできないためである
。In other words, this is because the substrate potential of the P-type FET 25 cannot be made equal to its source potential as in the case of FIG.
第６図に示すこの発明の実施例もまた上記２つの実施例
と同様に反一致動作をする論理回路である。The embodiment of the present invention shown in FIG. 6 is also a logic circuit that performs anticoincidence operation like the above two embodiments.
第２図の実施例と異なる点は，各直列ＦＥＴ回路２４、
２７、３２のＰ形ＦＥＴ２２，２５，３０とＮ形ＦＥＴ
２３，２６，３１とのサブストレートがそれぞれ共通に
電源端子２１と大地とに接続されていること．それ故に
ＦＥＴ２５，２３，３１にはそれぞれソース．ドレイン
間にダイオードＤ７，Ｄ８，Ｄ９が形成されていること
である。The difference from the embodiment shown in FIG. 2 is that each series FET circuit 24,
27, 32 P type FET22, 25, 30 and N type FET
The substrates 23, 26, and 31 are each commonly connected to the power supply terminal 21 and the ground. Therefore, FETs 25, 23, and 31 each have a source. Diodes D7, D8, and D9 are formed between the drains.
この様な論理回路の構成は，Ｎ形ＦＥＴ２３，２６、３
１がすべて共通のＰウエル領域内に形成される相補型集
積回路の場合に反一致動作を実現するため必要となるも
ので．回路断面図は省略しているが上記ダイオードＤ７
、Ｄ８、Ｄ９を形成するためには余分の半導体拡散領域
が設けられなくてはならない。The configuration of such a logic circuit consists of N-type FETs 23, 26, and 3.
This is necessary in order to realize anticoincidence operation in the case of a complementary integrated circuit where all 1s are formed in a common P-well region. Although the circuit cross-sectional diagram is omitted, the above diode D7
, D8, D9, an extra semiconductor diffusion region must be provided.
ところが第４図．第５図に示した実施例とくらべた場合
，Ｐウエル領域が１つに集約されるからダイオードＤ７
、Ｄ８、Ｄ９が２個余計に形成されるにもかかわらず．
回路面積の縮少がはかれるのである。However, Figure 4. When compared with the embodiment shown in FIG.
, D8, and D9 are formed.
The circuit area can be reduced.
以上述べた三通りの論理回路は，いずれも反一致動作を
するものであって第７図の論理記号図によって統一的に
表現されるものである。The three types of logic circuits described above all perform anticoincidence operations, and are uniformly expressed by the logic symbol diagram in FIG.
入力端子２８，２９に入力する入力信号Ａ，Ｂに対して
、三組の直列ＦＥＴ回路２４，２７，３２が設けられそ
れぞれの出力端子３４，３５，３３の出力信号Ｓ２，Ｓ
３，Ｓ１（＝Ａ・Ｂ＋Ａ・Ｂ）得られる。Three sets of series FET circuits 24, 27, 32 are provided for the input signals A, B input to the input terminals 28, 29, and the output signals S2, S of the respective output terminals 34, 35, 33 are provided.
3, S1 (=A・B+A・B) is obtained.
第８図ａ，ｂはこの発明の他の実施例を示す回路構成図
および論理記号図である。FIGS. 8a and 8b are a circuit configuration diagram and a logical symbol diagram showing another embodiment of the present invention.
同図ａにおいて，正電源ＶＤＤが印加される電源端子５
１と接地電位との間に直列に接続した二組の直列ＦＥＴ
回路５４，５７はＰ形ＦＥＴ５２，Ｎ形ＦＥＴ５３とＰ
形ＦＥＴ５５，Ｎ形ＦＥＴ５６をそれぞれ直列接続した
もので，これに対して第３の直列ＦＥＴ回路６２の第１
制御端子すなわちＮ形ＦＥＴ６１のソースは接地される
ことにより上記ＦＥＴ５６のソースと接続され，第２制
御端子すなわちＰ形ＦＥＴ６０のソースは上記直列ＦＥ
Ｔ回路５４の出力端子すなわちＦＥＴ５２，５３の接続
点と接続される。In the same figure a, the power supply terminal 5 to which the positive power supply VDD is applied
Two sets of series FETs connected in series between 1 and ground potential
The circuits 54 and 57 are P type FET52, N type FET53 and P
A type FET 55 and an N type FET 56 are connected in series, whereas a third series FET circuit 62 has a first
The control terminal, that is, the source of the N-type FET 61 is connected to the source of the FET 56 by being grounded, and the second control terminal, that is, the source of the P-type FET 60, is connected to the above-mentioned series FE.
It is connected to the output terminal of the T circuit 54, that is, the connection point between the FETs 52 and 53.
また、上記Ｎ形ＦＥＴ６１とＰ形ＦＥＴ６０とのゲート
は共通接続され上記直列ＦＥＴ回路５７の出力端子すな
わちＦＥＴ５５，５６の接続点と接続される。Further, the gates of the N-type FET 61 and the P-type FET 60 are commonly connected and connected to the output terminal of the series FET circuit 57, that is, the connection point between the FETs 55 and 56.
なお，入力端子５８，５９には入力信号Ａ，Ｂがそれぞ
れ供給され．入力端子５８は各ＦＥＴ５２，５３，５５
，５６のゲートと接続され．入力端力５９は直列ＦＥＴ
回路５４、５７の接続点と接続される。Note that input signals A and B are supplied to input terminals 58 and 59, respectively. The input terminal 58 is connected to each FET 52, 53, 55.
, 56 gates. Input terminal power 59 is series FET
It is connected to the connection point of circuits 54 and 57.
また出力端子６３，６４，６５はそれぞれ直列ＦＥＴ回
路６２，５４，５７の出力端子つまりそれぞれの共通ド
レイン電極と接続される。Further, the output terminals 63, 64, and 65 are respectively connected to the output terminals of the series FET circuits 62, 54, and 57, that is, the respective common drain electrodes.
そして６個のＦＥＴのサブストレート−ドレイン間に示
されるダイオードＤ１〜Ｄ６は．第２図．第３図に示し
た実施例におけるダイオードと同様，上記論理回路をＳ
ＯＳのＭＯＳ型集積回路で構成した場合に寄生的に形成
されるものである。The diodes D1 to D6 shown between the substrate and drain of the six FETs are... Figure 2. Similar to the diode in the embodiment shown in FIG.
It is formed parasitically when an OS is configured with a MOS type integrated circuit.
このように構成した論理回路は，入力信号Ａ，Ｂに対し
て次の論理式で表現される出力信号Ｓ１、Ｓ２、Ｓ３が
得られるものであって，回路動作は第２図．第３図に示
した実施例に関する第２表に準じて，次の第３表に示す
ところから容易に理解しうるものであるから，その詳細
な説明については省略する。The logic circuit configured in this manner provides output signals S1, S2, and S3 expressed by the following logical equations in response to input signals A and B, and the circuit operation is as shown in FIG. Since it can be easily understood from what is shown in the following Table 3 according to Table 2 regarding the embodiment shown in FIG. 3, detailed explanation thereof will be omitted.
なお，第８図ａに示す論理回路はＳＯＳ型のＭＯＳ型集
積回路として構成されるが．通常の相補型ＭＯＳ回路つ
まり選択拡散によっても形成できることはもちろんであ
る。Note that the logic circuit shown in FIG. 8a is constructed as an SOS type MOS type integrated circuit. Of course, it can also be formed by a normal complementary MOS circuit, that is, by selective diffusion.
第８図ｂは反一致動作をする上記論理回路の論理記号図
であり．同図ａと対応する部分に同一符号を付している
。FIG. 8b is a logical symbol diagram of the above logic circuit which performs anticoincidence operation. The same reference numerals are given to the parts corresponding to those in FIG.
このような構成であれば、上述したいずれの実施例も６
個のＦＥＴとそれに寄生するダイオードあるいは１個乃
至３個の意図的に構成したダイオードとを組合わせて反
一致回路あるいは一致回路を実現でき，従来の反一致回
路が１２個のＦＥＴを必要としていたのに較べると半数
のＦＥＴで論理回路を構成しているから一層の低消費電
力化，低価格化をはかれるものである。With such a configuration, any of the above embodiments can be used as 6
An anti-coincidence circuit or a coincidence circuit can be realized by combining two FETs and their parasitic diodes or one to three intentionally configured diodes, whereas the conventional anti-coincidence circuit required 12 FETs. Since the logic circuit is composed of half as many FETs as compared to the previous one, it is possible to further reduce power consumption and price.
また各実施例では単に反一致出力あるいは一致出力を得
ているだけではなく．入力信号Ａ，Ｂのオア出力，アン
ド出力が同時に出力信号として得られるから，最小の素
子数すなわち集積回路内での占有面積を縮小してかつ論
理回路機能の多様化をはかることができる。Moreover, in each embodiment, not only an anti-coincidence output or a coincidence output is obtained. Since the OR output and AND output of the input signals A and B can be obtained simultaneously as output signals, it is possible to reduce the minimum number of elements, that is, the area occupied within the integrated circuit, and to diversify the logic circuit functions.
したがって，この発明の論理回路は半加算器，半減算器
などに容易に応用することができ、演算回路の集積度の
向上に大きく寄与しうるものである。Therefore, the logic circuit of the present invention can be easily applied to half adders, half subtracters, etc., and can greatly contribute to improving the degree of integration of arithmetic circuits.
なお，この発明は上記した実施例のみに限定されるもの
ではなく．種々に変形して実施でき、しかも広く応用す
ることができる。Note that this invention is not limited to the above embodiments. It can be implemented with various modifications and can be widely applied.
以上詳述した通り，この発明によれば構成素子（ＦＥＴ
）数が最小で反一致，一致回路を実現でき，他の論理機
能を合せ持つことにより論理回路として広く応用できし
かも回路面積を縮小して集積回路の消費電力の低減をは
かりうるとともに製造コストの低減をも容易とする論理
回路を提供することができる。As detailed above, according to the present invention, the constituent elements (FET
), it is possible to realize anti-coincidence and coincidence circuits with a minimum number of circuits, and by having other logic functions, it can be widely applied as a logic circuit.In addition, it is possible to reduce the circuit area, reduce the power consumption of integrated circuits, and reduce manufacturing costs. It is possible to provide a logic circuit that can be easily reduced.
第１図は従来の反一致動作をなす論理回路を示す回路構
成図，第２図はこの発明の第１実施例を示す回路構成図
．第３図は同実施例を集積回路で構成する場合の回路断
面説明図．第４図はこの発明の第２実施例を示す回路構
成図．第５図は同実施例を集積回路で構成する場合の回
路断面説明図，第６図はこの発明の第３実施例を示す回
路構成図，第７図は第１〜第３実施例に対応する反一致
動作の論理記号図，第８図ａ，ｂはこの発明の他の実施
例を示す回路構成図および論理記号図である。
２４，５７・・・・・・第１の直列ＦＥＴ回路，２７，
５４・・・・・・第２の直列ＦＥＴ回路，３２，６２・
・・・・・第３の直列ＦＥＴ回路。FIG. 1 is a circuit configuration diagram showing a conventional logic circuit that performs anticoincidence operation, and FIG. 2 is a circuit configuration diagram showing a first embodiment of the present invention. Figure 3 is an explanatory diagram of a circuit cross section when the same embodiment is constructed using an integrated circuit. FIG. 4 is a circuit configuration diagram showing a second embodiment of the present invention. Fig. 5 is an explanatory diagram of a circuit cross section when the same embodiment is constructed with an integrated circuit, Fig. 6 is a circuit configuration diagram showing a third embodiment of the present invention, and Fig. 7 corresponds to the first to third embodiments. FIGS. 8a and 8b are circuit configuration diagrams and logical symbol diagrams showing another embodiment of the present invention. 24,57...First series FET circuit, 27,
54... Second series FET circuit, 32, 62.
...Third series FET circuit.
Claims (1)
，ＦＥＴと略記する）を反対導電型のＦＥＴと直列に接
続し．この直列回路両端子をそれぞれ第１，第２制御端
子とするとともに各ＦＥＴのゲート電極を共通接続して
入力端子とし。 各ＦＥＴの接続点を出力端子とする直列ＦＥＴ回路を三
組用いて構成する論理回路において，第１，第２の直列
ＦＥＴ回路を直列に接続し．第３の直列ＦＥＴ回路の第
１制御端子は上記第１の直列ＦＥＴ回路の第１制御端子
と接続するとともに第２制御端子は上記第２の直列ＦＥ
Ｔ回路の出力端子と接続し，かつ第３の直列ＦＥＴ回路
の入力端子を上記第１の直列ＦＥＴ回路の出力端子と接
続するとともに上記第１，第２の直列ＦＥＴ回路の各入
力端子には入力信号Ａを，第１の直列ＦＥＴ回路と第２
の直列ＦＥＴ回路の接続点には入力信号Ｂを供給するこ
とにより，上記第３の直列ＦＥＴ回路の出力端子から入
力信号Ａ，Ｂの反一致出力信号（Ａ・Ｂ＋Ａ・Ｂ）ある
いは一致出力信号（Ａ・Ｂ＋Ａ・Ｂ）を得るようにした
ことを特徴とする論理回路。[Claims] 1. An insulated gate field effect transistor (hereinafter abbreviated as FET) of one conductivity type is connected in series with a FET of the opposite conductivity type. Both terminals of this series circuit are used as first and second control terminals, respectively, and the gate electrodes of each FET are commonly connected to serve as an input terminal. In a logic circuit configured using three sets of series FET circuits with the connection point of each FET serving as an output terminal, the first and second series FET circuits are connected in series. The first control terminal of the third series FET circuit is connected to the first control terminal of the first series FET circuit, and the second control terminal is connected to the second series FET circuit.
The input terminal of the third series FET circuit is connected to the output terminal of the T circuit, and the input terminal of the third series FET circuit is connected to the output terminal of the first series FET circuit. The input signal A is connected to the first series FET circuit and the second series FET circuit.
By supplying the input signal B to the connection point of the series FET circuit, an anticoincidence output signal (A・B+A・B) or a coincidence output signal of the input signals A and B is output from the output terminal of the third series FET circuit. A logic circuit characterized in that it obtains (A・B+A・B).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6997575A JPS585611B2 (en) | 1975-06-10 | 1975-06-10 | Lonely Cairo |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6997575A JPS585611B2 (en) | 1975-06-10 | 1975-06-10 | Lonely Cairo |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS51149765A JPS51149765A (en) | 1976-12-22 |
| JPS585611B2 true JPS585611B2 (en) | 1983-02-01 |
Family
ID=13418154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6997575A Expired JPS585611B2 (en) | 1975-06-10 | 1975-06-10 | Lonely Cairo |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS585611B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0323124Y2 (en) * | 1985-11-28 | 1991-05-21 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4749886A (en) * | 1986-10-09 | 1988-06-07 | Intersil, Inc. | Reduced parallel EXCLUSIVE or and EXCLUSIVE NOR gate |
-
1975
- 1975-06-10 JP JP6997575A patent/JPS585611B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0323124Y2 (en) * | 1985-11-28 | 1991-05-21 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS51149765A (en) | 1976-12-22 |
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