JPS5850789A - Semiconductor laser device and manufacture thereof - Google Patents
Semiconductor laser device and manufacture thereofInfo
- Publication number
- JPS5850789A JPS5850789A JP14794981A JP14794981A JPS5850789A JP S5850789 A JPS5850789 A JP S5850789A JP 14794981 A JP14794981 A JP 14794981A JP 14794981 A JP14794981 A JP 14794981A JP S5850789 A JPS5850789 A JP S5850789A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- semiconductor laser
- mask
- active region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
- H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体レーザの電流狭窄構造及びその製造方
法、特に埋め込み゛構造半導体レーザの電流狭窄構造及
びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a current confinement structure for a semiconductor laser and a method for manufacturing the same, and more particularly to a current confinement structure for a buried structure semiconductor laser and a method for manufacturing the same.
半導体レーザにおいて、活性領域にいかに効率良く電流
を注入できるかは、半導体レーずの発振しきい値電流を
小さくする上で重要な要素である。In a semiconductor laser, how efficiently current can be injected into the active region is an important factor in reducing the oscillation threshold current of the semiconductor laser.
第１図に埋め込み構造半導体レーザの一例を示す。FIG. 1 shows an example of a buried structure semiconductor laser.
活性領域を含むメサ部分への電流狭窄は、このレーザは
ｎ型ＧａＡｓ基板１にｎ型”ｍａｌ Ｇａ０４１ Ａｓ
クラッドＪ−２、活性領域となるＩ） ｆｆｉ ＧａＡ
ｓ層３、ｐｍＡらａｓ Ｇａ、＠、 Ａｓクラッド層４
、オーミック電極形成用ｐ型ＧａＡ８Ｈａ ５を順次積
層してメサ状にし、そのメサ部分にＡｌ０ＪＩ ａａＯ
ＪＩ Ａｓ埋め込み層６を設けその埋め込み層６上に絶
縁膜７を設け、前記基板１及びオーミック電極形成用ｐ
！！！！ ＧａＡｓ層５に夫々電極８を設けたものであ
る。ｐ側表面上に形成された絶縁膜７によって行なわれ
る。このような構造は、ｐＨｌ１表面上に、Ｓｉへ９Ｍ
重０１ 等の絶縁膜７を一様に形成した後、フォトリゾ
グラフィー技術−こよって、メサ上部の絶′縁膜のみを
選択的に除去し、電流を流すための「窓」を開けるとと
ｋよって作製される。この電流狭窄方法は、従来量も広
く用いられてきた方法の一つであるが、絶縁膜７の窓を
メサ上に正確に配置するためのマスク合わせ操作を必要
とするため、素子の製造工程が複雑になるという欠点を
有していた。さらに、基本横モードで発振するための活
性領域３０幅は、通常２〜３７１ｍ以下となるため、上
述のマスク合わせ操作は容易ではない。また、絶縁膜７
の窓の幅はマスク合わせのための「合わせしろ」を含む
ため活性領域の幅の２倍程度とする必要があり、このた
め、第１図の矢印で示さ、、れる様に、メサの両側を通
って流れる無効電流の存在が避けられないという欠点も
あった。The current confinement to the mesa part including the active region is caused by this laser having an n-type "mal Ga041As" on an n-type GaAs substrate 1.
Cladding J-2, active region I) ffi GaA
S layer 3, pmA et al as Ga, @, As cladding layer 4
, p-type GaA8Ha 5 for forming ohmic electrodes are sequentially stacked to form a mesa, and Al0JI aaO is deposited on the mesa portion.
A JI As buried layer 6 is provided, an insulating film 7 is provided on the buried layer 6, and the substrate 1 and a p
! ! ! ! An electrode 8 is provided on each GaAs layer 5. This is done by an insulating film 7 formed on the p-side surface. Such a structure is formed on the pHl1 surface by 9M to Si.
After uniformly forming the insulating film 7 such as 01, only the insulating film on the upper part of the mesa is selectively removed using photolithography to open a "window" for current to flow. It is produced by k. This current confinement method is one of the methods that has been widely used in the past, but because it requires a mask alignment operation to accurately arrange the window of the insulating film 7 on the mesa, it is difficult to process the device manufacturing process. It has the disadvantage that it is complicated. Furthermore, since the width of the active region 30 for oscillation in the fundamental transverse mode is usually 2 to 371 m or less, the above-mentioned mask alignment operation is not easy. In addition, the insulating film 7
The width of the window needs to be approximately twice the width of the active region because it includes the "alignment margin" for mask alignment. Another disadvantage was that the presence of reactive currents flowing through them was unavoidable.
一方、マスク合わせが不要な方法ζこ、埋め込み層６を
高抵抗化する方法、あるいは第２図に示す様に、埋め込
み層中に逆バイアスされたｐｆｉ接合１３を設ける方法
があるが、前者においては実用上十分に高抵抗な（１０
″−１０’Ω備以上）層の結晶成長が現状では容易でな
いこと、後者においてはメサ側面での埋め込み層中のＰ
ｎ接合１３の位置−こ ゛よって、第２図の矢印
で示されるもれ電流の量が変化するばかりでなく、結晶
成長においてその位置の制御がきわめて困難であるとい
う問題点をそれぞれ有していた。On the other hand, there is a method that does not require mask alignment, a method of increasing the resistance of the buried layer 6, or a method of providing a reverse biased PFI junction 13 in the buried layer as shown in FIG. has a sufficiently high resistance for practical use (10
At present, it is not easy to grow crystals in the layer (more than -10'Ω), and in the latter case, P in the buried layer on the mesa side
The position of the n-junction 13 not only changes the amount of leakage current shown by the arrow in Figure 2, but also has the problem that it is extremely difficult to control its position during crystal growth. Ta.
このように、従来の電流狭窄方法には、工程の複雑さ、
工程の再現性の悪さという問題点がありこのことは素子
の歩留りを向上させる上できわめて不利であった。As described above, conventional current confinement methods have problems such as process complexity,
There was a problem of poor process reproducibility, which was extremely disadvantageous in improving the yield of devices.
本発明の目的は、マスク合わせ工程が不要で、かつ容易
で再現性の高い工程によって実現の可能な電流狭窄構造
及びその製造方法を提供することにある。以下本発明を
異体例によって説明する。An object of the present invention is to provide a current confinement structure that does not require a mask alignment process and can be realized by an easy and highly reproducible process, and a method for manufacturing the same. The present invention will be explained below using variant examples.
第３図は本発明による埋め込み構造半導体レーザの製造
方法の一例を示したものである。第３図３に示した様に
メサ最上部５はオーミック電極形成用ＧａＡｓ層、埋め
込み層６はＡｌｘ Ｇａｐ−、Ａｓ層例えばＡｌ６）ｇ
Ｇａ（財）、 Ａｓ層より成っている。オーミック電
極形成用ＧａＡｓ層５上にあらかじめ適当な選択結晶成
長マスク（Ｓｉｎｇ 、 ８４１Ｎ４等）を設けてあき
、エツチングによって活性領域を含むメサを形成した後
、埋め込み層成長のための２次結晶成長を行ない、その
後で選択結晶成長マスクを除去する工程は、通常の埋め
込み構造半導体レーザの製造方法と共通である。第３図
１の状態、すなわち、表面にオーミック電極形成用Ｇａ
Ａ＠層５及びＡｊＧａＡｓ埋め込み層６が露出した状態
で、全面を陽極酸化すると、ＧａＡｓ層５上にはＧａＡ
ｓ０陽極酸化膜９ａがＡｊｘ Ｇａ１−ｘＡｓＡｓ上に
は、ＡＪｘ Ｇａ１−ＨＡｓの陽極酸化膜９ｂが形成さ
れる（第３図ｂ）。次に、適当なエツチング液を用いて
、電極形成用ＧａＡｓ層５上の陽極酸化膜９麿のみを選
択除去する（第３図Ｃ）。FIG. 3 shows an example of a method for manufacturing a buried structure semiconductor laser according to the present invention. 3 As shown in FIG. 3, the mesa top 5 is a GaAs layer for forming an ohmic electrode, and the buried layer 6 is an Alx Gap-, As layer (for example, Al6)g.
It consists of Ga (goods) and As layers. A suitable selective crystal growth mask (Sing, 841N4, etc.) is prepared in advance on the GaAs layer 5 for forming the ohmic electrode, and after forming a mesa including the active region by etching, secondary crystal growth for buried layer growth is performed. The steps of performing this and then removing the selective crystal growth mask are common to the manufacturing method of a normal buried structure semiconductor laser. 3. In the state shown in FIG. 1, that is, Ga for forming an ohmic electrode on the surface.
When the entire surface is anodized with the A@ layer 5 and the AjGaAs buried layer 6 exposed, GaAs is formed on the GaAs layer 5.
On the s0 anodic oxide film 9a of Ajx Ga1-xAsAs, an anodic oxide film 9b of AJx Ga1-HAs is formed (FIG. 3b). Next, using an appropriate etching solution, only the 9 edges of the anodic oxide film on the electrode-forming GaAs layer 5 are selectively removed (FIG. 3C).
ＧａＡｓとＡｊＧａＡｓの陽極酸化膜９ｍ、９ｂのエツ
チング速度の違いを利用することｌこよって、選択エツ
チングのためのマスクを用いなくても、ＧａＡｓ層５上
の陽極酸化膜９ａのみを選択的に取り除くことが可能で
ある。エツチング液としては、ＧａＡｓの陽極酸化膜９
ａをエツチングできるもの、たとえば、Ｈｏｌ、 Ｈｌ
８０４ 、 ＮａＯＨ等を使用することができる。By utilizing the difference in etching speed between the anodic oxide films 9m and 9b of GaAs and AjGaAs, only the anodic oxide film 9a on the GaAs layer 5 can be selectively removed without using a mask for selective etching. Is possible. As an etching solution, an anodic oxide film 9 of GaAs is used.
Things that can be etched with a, such as Hol, Hl
804, NaOH, etc. can be used.
埋め込み層のＡＩ 濃度Ｘが０．３５である場合、Ｇａ
ＡｓとＡｊｘ Ｇａｐ−ｘＡｓの陽極酸化膜を完全に取
り除（のに要する時間の比は、たとえば１０倍希釈のＨ
Ｏｊ溶液を用いた場合、１：５であり、実用上十分番ζ
大きな選択比が得られる。第３図ｄはこのようにして得
られた半導体レーザである。When the AI concentration X of the buried layer is 0.35, Ga
The ratio of the time required to completely remove the anodic oxide film of As and Ajx Gap-x As is, for example, 10 times diluted with H
When Oj solution is used, the ratio is 1:5, which is practically tenth
A large selectivity ratio can be obtained. FIG. 3d shows the semiconductor laser thus obtained.
このように、マスク合わせ操作を必要とせずに電流狭窄
絶縁膜を容易に形成できることが、本発明の大きな特徴
である。陽極酸化工程及びそれに引き続くエツチング工
程は共にそれ自体きわめて単純かつ容易な工程であるた
め、本発明の製造方法の歩留りは高い。Ｉた本発明の方
法では絶縁属の形成において、いわば自動的なマスク合
わせが行なわれるため、絶縁膜９ｂはメサ上部に接して
形成される。したがって、第１図の方式に見られたよう
なマスクの合わせしるによるすき間を通ってメサ近傍を
流れる無効電流が全く無いということも、本発明の大き
な利点である。このようζこして形成された陽極酸化絶
縁膜による電流狭窄効果はきわめて良好であり、埋め込
み層として特に高抵抗化していないアンドープのＡｇ１
）４１ ｏａ６１１ Ａｓ（ｇ〜０．５Ω−程度）を用
いた場合でも、約３００μｍの共振器長に対して１５ｍ
Ａｌ１度の低しきい値電流が再現性良く得られる。Thus, a major feature of the present invention is that the current confinement insulating film can be easily formed without requiring a mask alignment operation. Since both the anodic oxidation step and the subsequent etching step are themselves extremely simple and easy steps, the manufacturing method of the present invention has a high yield. In addition, in the method of the present invention, automatic mask alignment is performed in the formation of the insulating layer, so that the insulating film 9b is formed in contact with the upper part of the mesa. Therefore, another great advantage of the present invention is that there is no reactive current flowing in the vicinity of the mesa through the gap caused by mask alignment, as seen in the method of FIG. The current confinement effect of the anodized insulating film formed in this way is extremely good, and the undoped Ag1 without particularly high resistance is used as a buried layer.
)41 Even when using oa611As (about g ~ 0.5 Ω), it is 15 m for a resonator length of about 300 μm.
A low threshold current of 1 degree Al can be obtained with good reproducibility.
以上の様に、本発明によれば、マスク合わせ操作を必要
とすることな（、容易かつ再現性の高い工程の組み合わ
せによって、効果の高い電流狭窄構造を形成することが
可能であり、埋め込み構造半導体レーザの歩留り向上の
有力な手段となるものである。As described above, according to the present invention, it is possible to form a highly effective current confinement structure by a combination of easy and highly reproducible processes without requiring a mask alignment operation ( This is an effective means of improving the yield of semiconductor lasers.
なお、本発明は埋め込み構造半導体レーザのみでなく、
活性領域上部に電極用ＧａＡｓ層を有し、それ以外の部
分ではＡＡ’ｘ Ｇａ、−ｘＡｓが露出している様な構
造の半導体レーザにも広く適用可能であることは言うま
でもない。Note that the present invention applies not only to buried structure semiconductor lasers but also to
Needless to say, the present invention is widely applicable to semiconductor lasers having a structure in which a GaAs layer for electrodes is provided above the active region, and AA'x Ga and -xAs are exposed in other parts.
第１図及び第２図は従来の電流狭窄構造を有する埋め込
み構造半導体レーザの構成図、第３図（ａ）〜（ｄ）は
本発明−実施例の埋め込み構造半導体レーザの製造方法
を示す工程図である。
１ ・−・ｎ−ＧａＡｓ基板ｅ ２ ・・・ｎ −Ａ
＆、＠ ｏａ（１６１Ａｓクラッド層３・・・Ｐ−Ｇａ
Ａａ活性層、４・・・Ｐ櫃４工Ｇ−６１んクラッド層５
・・・Ｐ−ＧａＡａオーミック電極層６・・・緘ＨＧａ
ジ、 Ａｓ埋め込み層。
７・・・絶 縁 膜、 ８・・・電極金属９＆・・Ｇａ
Ａｓの陽極酸化膜。
９１＞ −・Ａ／ＧａＡｓ （Ｄ 陽極ｄＲ化ＩＩ！１
１ ” ’ 、Ｐ−Ａ１６４＠ Ｇａ ＩＩＪ Ｉ Ａ
ｓ埋め込み層１２ ・・・ｎ −ＡＩＣｋＨＧａ ６４
＠ Ａｓ埋め込み層１３・・・電流狭窄Ｐｎ接合〇
代理人 弁理士 則 近 憲 佑 ほか１名第 １
図
□３
第 ２ 図
第３図1 and 2 are block diagrams of a conventional buried structure semiconductor laser having a current confinement structure, and FIGS. 3(a) to 3(d) are steps showing a method for manufacturing a buried structure semiconductor laser according to an embodiment of the present invention. It is a diagram. 1...n-GaAs substrate e 2...n -A
&, @ oa (161As cladding layer 3...P-Ga
Aa active layer, 4...P box 4G-61n cladding layer 5
... P-GaAa ohmic electrode layer 6 ... HGa
Di, As buried layer. 7... Insulating film, 8... Electrode metal 9 &... Ga
As anodic oxide film. 91> −・A/GaAs (D Anode dR conversion II!1
1 ” ', P-A164@Ga IIJ IA
s buried layer 12...n -AICkHGa 64
@As buried layer 13...Current confinement Pn junction〇Representative Patent attorney Kensuke Chika and 1 other person 1st
Figure □3 Figure 2 Figure 3
Claims (3)
Ａｓ層を有し、かつその他の部分ではＡｊｘ Ｇａ、−
ｘＡｓ層が表面に露出した構造を有し、該）Ｊｘ Ｇａ
１− ｘＭ層表面上に陽極酸化膜を形成することによっ
て該活性領域への電流狭窄を行なうことを特徴とする半
導体レーザ装置。(1) Ga for ohmic electrode formation on the top of the active region
It has an As layer, and the other parts have Ajx Ga, -
It has a structure in which the xAs layer is exposed on the surface, and the ) Jx Ga
A semiconductor laser device characterized in that current confinement to the active region is achieved by forming an anodic oxide film on the surface of the 1-xM layer.
ＡＪＸ Ｇａｔ−ＸＡｌ１層である埋め込み構造半導体
レーザ装置において、該ＩＪｘ Ｇａｐ−ｘＡｓＡｓ層
表面上階ζ陽極酸化膜成することによって、該活性領域
への電流狭窄を行なうことを特徴とする半導体レーザ装
置。(2) In a buried structure semiconductor laser device in which a GaAs layer is provided above the active region and one buried layer is an AJX Gat-XAl layer, the active region is A semiconductor laser device characterized by confining current to a region.
Ａｓ層を有し、かつその他の部分ではＡＪｘ Ｇａ□−
ｘＡｓ層が表面に露出した構造を有する半導体レーザ装
置を製造するに際し、該表面を一様に陽極酸化した後、
オーミック電極用ＧＪＩＡＩ上の陽極酸化膜を選択的に
除去することによって、該活性領域への電流狭窄構造を
形成することを特徴とする半導体レーザ装置の製造方法
。(3) Ga for ohmic electrode formation on the top of the active region
It has an As layer, and the other parts are AJx Ga□-
When manufacturing a semiconductor laser device having a structure in which the xAs layer is exposed on the surface, after uniformly anodizing the surface,
A method for manufacturing a semiconductor laser device, comprising selectively removing an anodic oxide film on a GJIAI for an ohmic electrode to form a current confinement structure in the active region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14794981A JPS5850789A (en) | 1981-09-21 | 1981-09-21 | Semiconductor laser device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14794981A JPS5850789A (en) | 1981-09-21 | 1981-09-21 | Semiconductor laser device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5850789A true JPS5850789A (en) | 1983-03-25 |
Family
ID=15441708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14794981A Pending JPS5850789A (en) | 1981-09-21 | 1981-09-21 | Semiconductor laser device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5850789A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5145807A (en) * | 1988-05-11 | 1992-09-08 | Mitsubishi Kasei Corporation | Method of making semiconductor laser devices |
| US5236864A (en) * | 1988-12-28 | 1993-08-17 | Research Development Corporation Of Japan | Method of manufacturing a surface-emitting type semiconductor laser device |
-
1981
- 1981-09-21 JP JP14794981A patent/JPS5850789A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5145807A (en) * | 1988-05-11 | 1992-09-08 | Mitsubishi Kasei Corporation | Method of making semiconductor laser devices |
| US5236864A (en) * | 1988-12-28 | 1993-08-17 | Research Development Corporation Of Japan | Method of manufacturing a surface-emitting type semiconductor laser device |
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