JPS584934A - Manufacture for semiconductor device - Google Patents
Manufacture for semiconductor deviceInfo
- Publication number
- JPS584934A JPS584934A JP10287781A JP10287781A JPS584934A JP S584934 A JPS584934 A JP S584934A JP 10287781 A JP10287781 A JP 10287781A JP 10287781 A JP10287781 A JP 10287781A JP S584934 A JPS584934 A JP S584934A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- solder
- semiconductor element
- semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の組立て方法１例えば電力用半導体
素子まｇはかかる半導体素子と基板との組立体である半
導体素子部材を、基板まπはステム上に半田付けするに
おいＣ，かかる半導体素子または半導体素子部材と基板
まｇはステ五〇間に存在する半田に、空１ＩＩ４シ＜は
気泡が発生することを抑制する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for assembling a semiconductor device (1). For example, a power semiconductor element or a semiconductor element member, which is an assembly of such a semiconductor element and a substrate, is soldered onto a substrate or a stem. This invention relates to a method for suppressing the formation of air bubbles in the solder present between the semiconductor element or the semiconductor element member and the substrate.
従来技ｌｉにおいては、半導体素子を基体に半田付けす
る場合、次のような方法な用いて行われて（、・る、第
１図を参照して説明すると、銅製のステムｌ上に銀ろう
２ｖ用い【モリブデン基板３にろう付けし１次に半田４
によって半導体素子５ｖ基板３に半田付けする。かかる
ろう付けおよび半田付けは、ステムｌの下に配置された
（図示しない）加熱体からの熱によって行う、ここで、
半導体素子５ｖ基板３に半田付けする場合、従来技術で
は次の３つの方法が行われている。In the conventional technique, when a semiconductor element is soldered to a substrate, the following method is used. 2V use [braze to molybdenum board 3, first solder 4
The semiconductor element 5v is soldered to the substrate 3 by the following steps. Such brazing and soldering is carried out by heat from a heating element (not shown) located below the stem l, where:
When soldering the semiconductor element to the 5V substrate 3, the following three methods are used in the prior art.
その１つは、半田４および半導体素子５ｖ基板３上に乗
せ、高温の加熱炉で半田材を溶融させて象付ける方法で
、その１つは加熱体の熱で半田４を溶融した段階で半導
体素子５を数回基板にこすり合わせて（スクラブして）
取り付ける方法、他の１つは、半導体素子５をスクラブ
しに後、基板３ＫＦｉつて水平にその一辺が１板３の一
辺に平行かつわずかに重なり合う位置（同図破線で示さ
れる位置）まで動かし、しかる後に半導体素子５ｖ基板
３に水平かつ平行に当該素子の取付は位置まで動かして
取付ける方法である。上述し′ｒ、３つの方法のうち前
者２つの方法は、電力用半導体素子Ｖように大きなチッ
プに対しては有効でない、その理由は、半導体素子５の
取付は時に半田４内に空隙（ボイド）が多数発生し、半
導体装置としては信頼性に欠けるという問題を有してい
る。One method is to place the solder 4 and the semiconductor element 5V on the substrate 3 and melt the solder material in a high-temperature heating furnace. Rub element 5 against the board several times (scrub)
Another mounting method is to scrub the semiconductor element 5 and then move the substrate 3KFi horizontally to a position where one side of the substrate 3KFi is parallel to and slightly overlaps one side of the board 3 (the position indicated by the broken line in the figure). Thereafter, the semiconductor element 5v is mounted horizontally and parallel to the substrate 3 by moving it to a position. Of the three methods mentioned above, the former two methods are not effective for large chips such as the power semiconductor device V. The reason is that mounting the semiconductor device 5 sometimes creates voids in the solder 4. ) occurs in large numbers, resulting in a problem of lack of reliability as a semiconductor device.
第３の方法は、前者２つの方法がもっていた間ｌｌｖ解
決すべく開発され文方法で、この方法によって半導体素
子な半田材けして取付は文場合は半田内に空ｌＩｖはと
んと生じないため、高い信頼性をもつπ電力用半導体装
置を作９５ることが確かめられた。ところが、かかる方
法では半導体素子Ｓ【基板３に半田付けする時、一度素
子５を基板３１１Ｃ対し水平な方向に移動させるが、こ
の素子５の移動が基板３に平行に行われないと、取付は
後に半田内に空−が残り易いことが経験された。まｇ、
この半導体素子５の平行移動には技術上熟練Ｖ畳し、半
導体装置製作工程の効率すなわち歩留９１’低下させる
ことは否み得な〜・。The third method is a method developed to solve the problems that the former two methods had.With this method, if the solder material of the semiconductor device is used, no voids will be created in the solder. It has been confirmed that a highly reliable π power semiconductor device can be produced. However, in this method, when soldering the semiconductor element S to the substrate 3, the element 5 is once moved in a direction horizontal to the substrate 311C, but if this movement of the element 5 is not performed parallel to the substrate 3, the mounting will not be possible. It was later experienced that voids tend to remain in the solder. Mag,
This parallel movement of the semiconductor element 5 requires technical skill and inevitably reduces the efficiency of the semiconductor device manufacturing process, that is, the yield rate.
本発明の目的は上述し究第３番目の半導体素子部材は方
法に不可避の問題を解決するにあり、このため本発明に
よれば半導体素子またはかかる半導体素子と基板との組
立体である半導体素子部材な基体上に半田材けする方法
にお〜２て、溶融されに半田上の半導体素子または半導
体素子部材を。An object of the present invention is to solve the above-mentioned problems unavoidable in the third semiconductor device member method, and for this reason, the present invention provides a semiconductor device or a semiconductor device that is an assembly of such a semiconductor device and a substrate. In method 2 for applying solder material onto a substrate, the semiconductor element or semiconductor element member on the solder is melted.
牛導体収納容器上に前記基体と近接して設けら九に凸状
ガイドを案内として基体に対し平行に、前記半導体素子
または半導体素子部材の一部と前記基体の一部とが重な
り合う位置まで移動し、しかる後に前記半導体素子また
は半導体素子部材を凸状ガイドを用いて基体上の素子取
付は位置へ移動する工程を有することｖ４Ｉ黴とする半
導体装置の組立て方法が提供される。Using a convex guide provided on the conductor storage container in close proximity to the base body as a guide, move parallel to the base body to a position where the semiconductor element or a part of the semiconductor element member and a part of the base body overlap. However, there is provided a method for assembling a semiconductor device, which includes the step of subsequently moving the semiconductor element or semiconductor element member to a position for mounting the element on the substrate using a convex guide.
以下、添付図面を参照して本発明にかかる半導体装置の
組立て方法の実施例Ｖ説明する。Embodiment V of the method for assembling a semiconductor device according to the present invention will be described below with reference to the accompanying drawings.
第２図は本発ｑ１４１）方法を行５工権における半導体
装置の要部を示す図である１間図において（ａ）と（ｂ
）はそれぞれ当該半導体装置の平面図と−）のムーム＃
［＆５断面図である０本発ＥＪ１によれば１例えば銅製
ステムからなる半導体収納容器基体１上にモリブデン基
板３が例えば銀ろ５（１１１点７８０ （’Ｃ））２に
よって固着されており、轟骸基板３１ｆ：ＩＩ＊して、
半導体索子５を水平移動させるための案内としての凸状
ガイド６が設けられる。前記凸状ガイド６は、基体ｌと
ｄば等しい高さを有するよう（ステム１と一体に機械加
工により形成されてもよく、まＲ該ステムｌとは別に形
成されて基板３と同様に適当なろう材によリステムｌＫ
固着されてもよい。Figure 2 is a diagram illustrating the main parts of a semiconductor device in the 5th stage of construction using the present invention q141) method.
) is the plan view of the semiconductor device, and −) is the muum#, respectively.
[&5 According to EJ1, which is a cross-sectional view, a molybdenum substrate 3 is fixed on a semiconductor storage container base 1 made of, for example, a copper stem, with, for example, a silver plate 5 (111 points, 780 ('C)) 2, Todoroki board 31f:II*,
A convex guide 6 is provided as a guide for horizontally moving the semiconductor cord 5. The convex guide 6 has a height equal to that of the base 1 (it may be formed integrally with the stem 1 by machining, or it may be formed separately from the stem 1 in a suitable manner similar to the base 3). List stem lK by narou wood
It may be fixed.
かかる半導体装置において半導体素子ｓｖ基板３上に半
田付けするには、先ず、基板３上に半田材４Ｃ融点３０
０（’Ｃ））を載せ、さらに半田材４上に半導体素子５
ｔｌ−置き、半導体装置下方から加熱体（図示せず）で
熱を加え、半田を溶融させる。In order to solder the semiconductor element onto the sv substrate 3 in such a semiconductor device, first, solder material 4C melting point 30 is applied onto the substrate 3.
0 ('C)), and then the semiconductor element 5 is placed on the solder material 4.
The semiconductor device is placed at tl-, and heat is applied from below with a heating element (not shown) to melt the solder.
次に、半導体索子５ｔ−半導体取付は位置７付近で数回
こすり合せ（スタツグ）、シかる後半導体素子５を凸状
カイドロ上にかつそれＫｆＢって同図に示す如く左方向
にスライドさせる。このとき。Next, the semiconductor cable 5t-semiconductor attachment is rubbed together several times near position 7, and after that, the semiconductor element 5 is placed on the convex guide and it is slid to the left as shown in the figure. . At this time.
半導体素子５の右の上下方向、すなわち素子の勧業の横
方向の辺ｔＣ沿う狭い領域は基板３の左の上下方向の辺
に沿うきわめて狭い領域に重なり合っている６次いで前
記半導体素子５を凸状ガイド６上を基板３に平行にかつ
、半田材を前方へ押し流すように取付は位置７までスラ
イｔさせる。A narrow area along the right vertical side tC of the semiconductor element 5, that is, along the horizontal side tC of the element overlaps with an extremely narrow area along the left vertical side of the substrate 3. Attachment is done by sliding the guide 6 parallel to the board 3 to position 7 so as to push the solder material forward.
このような本発明による固着方法によれば、簡単な操作
で半導体素子５を、当該半導体素子５と基板３との間に
空隙な発生させることなく基板３に半田付けすることが
できる。According to the fixing method according to the present invention, the semiconductor element 5 can be soldered to the substrate 3 with a simple operation without creating a gap between the semiconductor element 5 and the substrate 3.
また１本発明は半導体素子を基板に半田付けする場合の
みでな（、半導体素子が取付けられに基板などの如き半
導体素子部材を半導体収納容器への取付けにも応用しう
る。第３図を参照すると。Furthermore, the present invention is applicable not only to the case of soldering a semiconductor element to a substrate (but also to the attachment of a semiconductor element member such as a substrate on which a semiconductor element is attached to a semiconductor storage container. See FIG. 3). Then.
半導体収納容器基体１上に銅岬かもなる基板１２がろう
付けされており、当該基板１２上にタングステン、モリ
ブデン、セラミック等からなる基板１７が半田付けされ
る０図には基板１）のみが示されるが、この基板は前述
しで如くその上に半導体素子が取付けられに半導体素子
部材であってもよ−・、基板１７を半田材けする方法は
、前述しに半導体素子の場合と同じで、基板ｔｚｅｃｌ
ｉｌｌして設けられ交１個の凸状ガイド１６上を基板１
７ｖスライドさせることＫよって、空ｌ！Ｉｖ発生する
ことなく半田材けすることができる。πだし、基板１７
に：半導体素子を半田付けする場合は、半田材１３より
融点の低い半田材を使用する必要がある。A substrate 12, which also serves as a copper cape, is soldered onto the semiconductor storage container base 1, and a substrate 17 made of tungsten, molybdenum, ceramic, etc. is soldered onto the substrate 12. Only the substrate 1) is shown in FIG. However, as described above, this substrate may be a semiconductor element member on which a semiconductor element is mounted.The method for soldering the substrate 17 is the same as that for the semiconductor element described above. , substrate tzecl
The substrate 1 is placed over the intersecting convex guides 16 arranged in parallel with each other.
7v sliding K, empty l! Soldering material can be soldered without generating IV. Since it is π, the board is 17
B: When soldering semiconductor elements, it is necessary to use a solder material that has a lower melting point than the solder material 13.
以上説明しに如き１本発明の方法によれば簡単な操作で
電力用大型半導体素子まπは半導体基板勢の半導体素子
部材な、空隙を発生させることなく、基板に半田付けす
ることができ、装置の信頼性を高めることができる。As explained above, according to the method of the present invention, a large power semiconductor element or a semiconductor element member of a semiconductor substrate can be soldered to a substrate without creating a gap with a simple operation. The reliability of the device can be improved.
なお、第２図には凸状ガイド６は２個示されろが、それ
は２個に限定されるものでなく、算３図に示される如く
１個でお一つてもよい、凸状ガイド６の上表面は凸状に
形成してもまたは平担に形成してもよい、更に、凸状ガ
イドは基板から離して廖成してもまたは隣接して形成し
てもよい、要は。Although two convex guides 6 are shown in FIG. 2, the number is not limited to two, and there may be one convex guide 6 as shown in FIG. The upper surface of the guide may be convex or flat; furthermore, the convex guide may be formed apart from or adjacent to the substrate.
凸部ガイドが、半導体素子または半導体素子部材の平行
な移動な助けることである。The convex guide assists in parallel movement of the semiconductor element or semiconductor element member.
＠１図は従来方法における半導体素子の基板への半田付
けの工ｌｉＫおける半導体素子と基板とｔ示す断面図、
第２図の（−と伽）はそれぞれ本発明の方法な実施する
工程における半導体収納容器基体と半導体素子との千賀
図および麟面図、第３図の（ｍｌと（ｂｌは本発明の方
法の他の実施例の工程における半導体収納容器と半導体
素子部材の平面図と断面図である。Figure 1 is a cross-sectional view showing the semiconductor element and the substrate in the conventional method of soldering the semiconductor element to the substrate.
In FIG. 2, (- and 伽) are respectively the Chiga diagram and the front view of the semiconductor storage container base and the semiconductor element in the process of carrying out the method of the present invention, and (ml and (bl) in FIG. 3 are the method of the present invention. FIG. 6 is a plan view and a cross-sectional view of a semiconductor storage container and a semiconductor element member in the process of another example.
１・・・半導体収納容器基体％３ 、１２ 、１７−・
一基板。1...Semiconductor storage container base%3, 12, 17-...
One board.
４．１３−−・半田材、５・−半導体素子、６．１６−
凸状ガイド
第１図
（ｂ）
第２図
第３図4.13--Solder material, 5--Semiconductor element, 6.16-
Convex guide Fig. 1 (b) Fig. 2 Fig. 3
Claims (1)
ある半導体素子部材を基体上に半田付けする方法におい
【、溶融されπ半田上の半導体素子または半導体素子部
材を、半導体収納容器上に前記基体と近接して設けられ
た凸部状ガイドを案内として基体に対し平行に、前記半
導体素子まπは半導体素子部材の一部と前記基体の一部
とが重なり合う位置まで移動し、しかる後に前記半導体
素子または半導体素子部材を凸状ガイドを用いて基体上
の素子取付は位置へ移動する工程を有することを特徴と
する半導体装置の組立て方法。[Claims] In a method of soldering a semiconductor element or a semiconductor element member, which is an assembly of such a semiconductor element and a substrate, onto a substrate, The semiconductor element or π is moved parallel to the base using a convex guide provided on the container in close proximity to the base to a position where a part of the semiconductor element member and a part of the base overlap. . A method for assembling a semiconductor device, comprising the step of subsequently moving the semiconductor element or semiconductor element member to a position for mounting the element on the substrate using a convex guide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10287781A JPS584934A (en) | 1981-06-30 | 1981-06-30 | Manufacture for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10287781A JPS584934A (en) | 1981-06-30 | 1981-06-30 | Manufacture for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS584934A true JPS584934A (en) | 1983-01-12 |
Family
ID=14339115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10287781A Pending JPS584934A (en) | 1981-06-30 | 1981-06-30 | Manufacture for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS584934A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59182814A (en) * | 1983-04-01 | 1984-10-17 | Idemitsu Petrochem Co Ltd | Monovinyl aromatic resin composition |
| US4639494A (en) * | 1984-02-28 | 1987-01-27 | Sumitomo Chemical Company, Limited | Process for producing polystyrene |
| JPS63248809A (en) * | 1987-01-28 | 1988-10-17 | ザ ダウ ケミカル カンパニー | Rubber reinforcing monovinylidene aromatic polymer resin and its production |
| JPH0368612A (en) * | 1989-08-08 | 1991-03-25 | Japan Synthetic Rubber Co Ltd | High-gloss, high-impact aromatic vinyl resin composition |
| US5191023A (en) * | 1988-08-26 | 1993-03-02 | Mitsui Toatsu Chemicals, Inc. | Block-copolymerized-rubber-modified styrene copolymers |
-
1981
- 1981-06-30 JP JP10287781A patent/JPS584934A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59182814A (en) * | 1983-04-01 | 1984-10-17 | Idemitsu Petrochem Co Ltd | Monovinyl aromatic resin composition |
| JPH0318646B2 (en) * | 1983-04-01 | 1991-03-13 | Idemitsu Petrochemical Co | |
| US4639494A (en) * | 1984-02-28 | 1987-01-27 | Sumitomo Chemical Company, Limited | Process for producing polystyrene |
| JPS63248809A (en) * | 1987-01-28 | 1988-10-17 | ザ ダウ ケミカル カンパニー | Rubber reinforcing monovinylidene aromatic polymer resin and its production |
| US5191023A (en) * | 1988-08-26 | 1993-03-02 | Mitsui Toatsu Chemicals, Inc. | Block-copolymerized-rubber-modified styrene copolymers |
| JPH0368612A (en) * | 1989-08-08 | 1991-03-25 | Japan Synthetic Rubber Co Ltd | High-gloss, high-impact aromatic vinyl resin composition |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0055378A2 (en) | A method of brazing adjoining surfaces of elements | |
| JPS59119844A (en) | Method of brazing by laser flexible wire | |
| DE2937050C2 (en) | ||
| US3665590A (en) | Semiconductor flip-chip soldering method | |
| US3470611A (en) | Semiconductor device assembly method | |
| JPS59110128A (en) | Method of connecting lead to semiconductor device | |
| JPS584934A (en) | Manufacture for semiconductor device | |
| JP2002076043A (en) | Bump forming method, semiconductor device, and bump forming device | |
| US4654102A (en) | Method for correcting printed circuit boards | |
| US4778556A (en) | Apparatus for correcting printed circuit boards | |
| JPH0778932A (en) | Manufacture of semiconductor device | |
| JPH07118498B2 (en) | Electrical junction | |
| JP2828069B2 (en) | Soldering method of work with bump | |
| JPH026055A (en) | Method of soldering printed circuit board and silicon chip | |
| JP2975207B2 (en) | Wire bonding equipment with solder wire | |
| JP2544947B2 (en) | Method for manufacturing semiconductor device | |
| JPH0529364A (en) | Method and apparatus for bonding semiconductor element | |
| JPS6153737A (en) | Electronic device assembling method and apparatus thereof | |
| JP2682006B2 (en) | Bump forming method | |
| JPS62134173A (en) | Laser die bonding tool | |
| JP4499899B2 (en) | Lead frame brazing method for electronic component package | |
| JPS58197897A (en) | Solder bonding method | |
| JP2874771B2 (en) | Method of forming bump | |
| DE19818436A1 (en) | Fluxless soldering especially of a chip to a ball grid array substrate | |
| DE2355501C3 (en) | Process for the production of soldering points with a soft solder on a gold layer |