JPS5849064B2 - Tobikoshisouchi - Google Patents
TobikoshisouchiInfo
- Publication number
- JPS5849064B2 JPS5849064B2 JP13427375A JP13427375A JPS5849064B2 JP S5849064 B2 JPS5849064 B2 JP S5849064B2 JP 13427375 A JP13427375 A JP 13427375A JP 13427375 A JP13427375 A JP 13427375A JP S5849064 B2 JPS5849064 B2 JP S5849064B2
- Authority
- JP
- Japan
- Prior art keywords
- vertical
- circuit
- current
- pincushion distortion
- correction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Details Of Television Scanning (AREA)
Description
【発明の詳細な説明】
本発明はテレビジョン受像機などにおいて上下糸巻歪補
正電流による垂直飛越走査の乱れを除去する装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for removing disturbances in vertical interlaced scanning caused by vertical pincushion distortion correction currents in television receivers and the like.
第１図は従来の垂直偏向出力回路と上下糸巻歪補正回路
を示すものである。FIG. 1 shows a conventional vertical deflection output circuit and a vertical pincushion distortion correction circuit.
同図において、１は極性反転機能を含んだ増幅器、２は
平衡変調器、３は増幅器、４は入力抵抗、５は帰還コン
デンサ、６は水平信号バイパス用のコンデンサ、７は結
合コンデンサ、８は垂直偏向コイル、９は上下糸巻歪補
正用出力トランス、１０は帰還抵抗、１１は結合コンデ
ンサである。In the figure, 1 is an amplifier including a polarity inversion function, 2 is a balanced modulator, 3 is an amplifier, 4 is an input resistor, 5 is a feedback capacitor, 6 is a capacitor for horizontal signal bypass, 7 is a coupling capacitor, and 8 is a A vertical deflection coil, 9 an output transformer for correcting vertical pincushion distortion, 10 a feedback resistor, and 11 a coupling capacitor.
次に、この回路の動作について第２図とともに説明する
。Next, the operation of this circuit will be explained with reference to FIG.
入力端子Ａには第２図Ａに示す負極性垂直周期パルス信
号が、前段発振器（図示せず）より加えられる。A negative polarity vertical periodic pulse signal shown in FIG. 2A is applied to input terminal A from a pre-stage oscillator (not shown).
この垂直周期パルス信号は増幅器１、入力抵抗４、帰還
コンデンサ５よりなるミラー積分回路により積分され、
Ｂ点には垂直周期の鋸歯状波電圧が得られる。This vertical periodic pulse signal is integrated by a Miller integration circuit consisting of an amplifier 1, an input resistor 4, and a feedback capacitor 5.
A sawtooth wave voltage with a vertical period is obtained at point B.
従って垂直偏向コイル８には鋸歯状波の偏向電流を流す
ことができる。Therefore, a sawtooth wave deflection current can be passed through the vertical deflection coil 8.
一方、平衡変調器２の入力端子Ｄには第２図Ｄに示す水
平周期の鋸歯状波電圧を加え、また変調入力端子Ｃには
第２図Ｃに示すように垂直周期鋸歯状波電圧を加える。On the other hand, a sawtooth wave voltage with a horizontal period shown in FIG. 2D is applied to the input terminal D of the balanced modulator 2, and a sawtooth wave voltage with a vertical period as shown in FIG. 2C is applied to the modulation input terminal C. Add.
従って平衡変調器２の出力には第２図Ｅに示すような垂
直走査の前半と後半とで水平周期鋸歯状波の位相が反転
し、かつ振巾変調された電圧波形が得られる。Therefore, as shown in FIG. 2E, the balanced modulator 2 outputs a voltage waveform in which the phase of the horizontal periodic sawtooth wave is reversed between the first half and the second half of the vertical scan, and the amplitude is modulated.
この電圧は増幅器３により増幅され、結合コンデンサ１
１を介して、上下糸巻歪補正用出力トランス９の一次巻
線に加えられる。This voltage is amplified by amplifier 3 and coupling capacitor 1
1 to the primary winding of the output transformer 9 for correcting vertical pincushion distortion.
これに伴ない二次巻線に発生する起動力により帰還抵抗
１０、上下糸巻歪補正用出力トランス９の二次巻線、垂
直偏向コイル８、結合コンデンサ７、水平信号バイパス
用コンデンサ６のループを通って電流が流れる。Due to the starting force generated in the secondary winding, the feedback resistor 10, the secondary winding of the output transformer 9 for correcting vertical pincushion distortion, the vertical deflection coil 8, the coupling capacitor 7, and the loop of the horizontal signal bypass capacitor 6 are activated. Current flows through it.
このループは垂直偏向コイル８によりインダクタンス負
荷として作用するため、流れる電流波形は第２図Ｅの電
圧が積分された第２図Ｆの波形となる。Since this loop acts as an inductance load by the vertical deflection coil 8, the flowing current waveform becomes the waveform shown in FIG. 2F, which is obtained by integrating the voltage shown in FIG. 2E.
従って、垂直偏向コイル８には垂直周期鋸歯状波電流と
、振幅変調された水平周期パラボラ電流とが重畳された
電流が流れることになり、上下糸巻歪補正電流を含んだ
第２図Ｂに示す垂直偏向電流が得られることになる。Therefore, a current in which a vertical periodic sawtooth wave current and an amplitude-modulated horizontal periodic parabolic current are superimposed flows through the vertical deflection coil 8, as shown in FIG. 2B including the vertical pincushion distortion correction current. A vertical deflection current will be obtained.
所で、この回路においては帰還抵抗１０の一端Ｂ点にも
第２図Ｂに示す波形の電圧が生じることになり、この電
圧の水平周期パラボラ電圧も帰還コンデンサ５を介して
増幅器１の入力へ帰還される。Incidentally, in this circuit, a voltage having the waveform shown in FIG. will be returned.
この入力電圧はＡ点からの垂直周期パルスと重なり、増
幅器１に加えられる。This input voltage overlaps with the vertical periodic pulse from point A and is applied to amplifier 1.
しかし一般のテレビジョン信号は、飛越走査処理を施し
ており、奇数フィールドと偶数フィールドとで、垂直同
期信号と水平同期信号との時間関係が異なっている。However, general television signals undergo interlaced scanning processing, and the time relationship between vertical synchronization signals and horizontal synchronization signals differs between odd and even fields.
このために前記の様に上下巻線歪補正信号が垂直偏向回
路の入力に戻ることは、飛越走査が乱れる原因となる。For this reason, returning the upper and lower winding distortion correction signals to the input of the vertical deflection circuit as described above causes disturbances in interlaced scanning.
本発明はこのような上下糸巻歪補正電流による飛越走査
の乱れを除去することを目的とするもので、以下にその
実施例について説明する。The present invention aims to eliminate such disturbances in interlaced scanning caused by the vertical pincushion distortion correction current, and embodiments thereof will be described below.
第３図において、第１図と同一の部品については、同一
番号を付している。In FIG. 3, parts that are the same as those in FIG. 1 are given the same numbers.
第１図の回路との相違点は、上下糸巻歪補正回路の増幅
器３の出力点より、結合コンデンサ１３および可変イン
ダクタンス１２の直列回路を介して、帰還抵抗１０の一
端Ｂ点に補正電流を流している。The difference from the circuit in FIG. 1 is that a correction current is passed from the output point of the amplifier 3 of the upper and lower pincushion distortion correction circuit to point B at one end of the feedback resistor 10 via a series circuit of a coupling capacitor 13 and a variable inductance 12. ing.
なおその直列回路においてはその共振周波数が水平走査
周波数とはと一致するように構成している。The series circuit is constructed so that its resonant frequency coincides with the horizontal scanning frequency.
この場合、上下糸巻歪補正用トランス９の巻線方向を第
３図の様にすると（図において黒星印は巻始めを示す）
。In this case, if the winding direction of the vertical pincushion distortion correction transformer 9 is set as shown in Figure 3 (in the figure, the black star indicates the beginning of winding).
.
可変インダクタ１２に流れる第２図Ｆに示す波形の電流
は上下糸巻歪補正用偏向電流により帰還抵抗１０に生じ
る電圧を打ち消す方向に流れる。The current having the waveform shown in FIG. 2F flowing through the variable inductor 12 flows in a direction that cancels out the voltage generated in the feedback resistor 10 due to the deflection current for correcting the vertical pincushion distortion.
従って可変インダクタンス１２を調整することにより、
Ｂ点に生じる上下糸巻歪補正電圧を除去し、垂直周期の
鋸歯状波電圧のみにすることができる。Therefore, by adjusting the variable inductance 12,
The vertical pincushion distortion correction voltage generated at point B can be removed to provide only the vertical period sawtooth wave voltage.
このように構成することにより、垂直偏向回路入力への
上下糸巻歪補正電圧の戻りをなくすることができ、飛越
走査の乱れを除去することができる。With this configuration, it is possible to eliminate the return of the vertical pincushion distortion correction voltage to the input of the vertical deflection circuit, and it is possible to eliminate disturbances in interlaced scanning.
第４図は本発明を用いた具体的な回路を示すもので、１
４は垂直周期パルス増幅用スイッチングトランジスタ、
１５．１６はその負荷抵抗、１６′は垂直振幅調整用可
変抵抗、１７は温度補償用のダイオード、１８はバイア
ス調整用可変抵抗、２１はバイアス電圧平滑用コンデン
サ、１９，２０．２２はドライブトランジスタ２４のバ
イアス抵抗、２３は結合用コンデンサ、２５はドライブ
トランジスタ２４のエミツタ抵抗である。Figure 4 shows a specific circuit using the present invention.
4 is a switching transistor for vertical periodic pulse amplification;
15.16 is the load resistance, 16' is a variable resistor for vertical amplitude adjustment, 17 is a diode for temperature compensation, 18 is a variable resistor for bias adjustment, 21 is a bias voltage smoothing capacitor, 19, 20.22 is a drive transistor 24 is a bias resistor, 23 is a coupling capacitor, and 25 is an emitter resistor of the drive transistor 24.
２６は帰還コンデンサ、２７，２８はバイアス抵抗、３
０は温度補償用ダイオード、３１は保護抵抗、３２．３
６は垂直出力用相補対称性トランジスタ、３３，３５は
出力トランジスタ３２．３６のバイアス抵抗、３４は出
力結合コンデンサ、３７は垂直偏向コイル、３８は帰還
用抵抗、３９．４０は直線性補正用帰還コンデンサ、４
１，４２，４３は直線性調整用抵抗である。26 is a feedback capacitor, 27 and 28 are bias resistors, 3
0 is a temperature compensation diode, 31 is a protection resistor, 32.3
6 is a complementary symmetrical transistor for vertical output, 33 and 35 are bias resistors of output transistors 32 and 36, 34 is an output coupling capacitor, 37 is a vertical deflection coil, 38 is a feedback resistor, and 39.40 is a feedback for linearity correction. capacitor, 4
1, 42, and 43 are linearity adjustment resistors.
４４は上下糸巻歪補正用出力トランス、４５は結合コン
デンサ、４７は結合コンデンサ、４６は可変インダクタ
ンス、５０，５１はバイアス抵抗、４８は保護抵抗、４
９，５２は上下糸巻歪補正用相補対称性出力トランジス
タ、５３，５５は出力トランジスタ、４９，５２のバイ
アス抵抗、５４は温度補償用ダイオード、５９はドライ
ブトランジスタ、５６，５８．６０はドライブトランジ
スタ５９のバイアス抵抗、５７はバイアス回路平滑用コ
ンデンサである。44 is an output transformer for correcting upper and lower pincushion distortion, 45 is a coupling capacitor, 47 is a coupling capacitor, 46 is a variable inductance, 50 and 51 are bias resistors, 48 is a protection resistor, 4
9 and 52 are complementary symmetric output transistors for correcting upper and lower pincushion distortion, 53 and 55 are output transistors, 49 and 52 are bias resistors, 54 is a temperature compensation diode, 59 is a drive transistor, 56, 58, and 60 are drive transistors 59 57 is a bias circuit smoothing capacitor.
以下、この回路の動作について簡単に述べる。The operation of this circuit will be briefly described below.
スイッチングトランジスタ１４のベースには、正極性の
垂直パルスが印加され、コレクター負荷抵抗１６に生じ
る電圧はコンデンサ２３によりドライブトランジスタ２
４のベースへ加えられる。A positive vertical pulse is applied to the base of the switching transistor 14, and the voltage generated across the collector load resistor 16 is connected to the drive transistor 2 by a capacitor 23.
Added to the base of 4.
ドライブトランジスタ２４のコレクタから得られる増幅
された垂直偏向出力電圧は、それぞれで相補対称性出力
トランジスタ３２．３６のペースニ加えられ、それぞれ
のエミツターに接続された抵抗３３ ．３５の接続点よ
り出力結合コンデンサ３４を通じて、垂直偏向コイル３
７に垂直偏向電流を通している。The amplified vertical deflection output voltage obtained from the collector of drive transistor 24 is applied to the base of complementary symmetrical output transistors 32, 36, respectively, and resistors 33, . The vertical deflection coil 3 is connected to the vertical deflection coil 3 through the output coupling capacitor 34 from the connection point 35.
A vertical deflection current is passed through 7.
この電流は帰還用抵抗３８を介してアースへ流れる。This current flows to ground via the feedback resistor 38.
ここで、スイッチングトランジスタ１４のペースヘ印加
される垂直パルス電圧より、鋸歯状波電流を偏向コイル
３１に流すために、帰還抵抗３８に生じる電圧を帰還コ
ンデンサ３９．４０と直線性調整用抵抗４Ｌ４２，４３
より成る直線性補正用帰還回路を通じて、ドライブトラ
ンジスタ２４のベースに一端を接続された結合コンデン
サ２３に帰還している。Here, in order to cause a sawtooth wave current to flow through the deflection coil 31 from the vertical pulse voltage applied to the pace of the switching transistor 14, a voltage generated in the feedback resistor 38 is applied to the feedback capacitor 39, 40 and the linearity adjustment resistor 4L42, 43.
The signal is fed back to the coupling capacitor 23 whose one end is connected to the base of the drive transistor 24 through a linearity correction feedback circuit consisting of the following.
即ち、ミラー積分回路を形成し、パルス入力電圧より鋸
歯状波電流を偏向コイル３γに流している。That is, a mirror integration circuit is formed, and a sawtooth wave current is caused to flow through the deflection coil 3γ based on the pulse input voltage.
またドライブトランジスタ５９のペースには垂直鋸歯状
波電圧で平衡変調された水平周期の鋸歯状波電圧が加え
られ、このドライブトランジスタ５９のコレクタ出力電
圧を、相補対称性出力トランジスタ４９．５２のベース
に加え、出力トランジスタのエミツターに接続されたバ
イアス抵抗５０，５１の接続点を、結合コンデンサ４５
を介して上下糸巻歪補正用出力トランスの一次巻線に接
続し、二次巻線は偏向コイル３７に直列に接続されてい
る。Further, a horizontally periodic sawtooth voltage balanced with a vertical sawtooth voltage is applied to the pace of the drive transistor 59, and the collector output voltage of the drive transistor 59 is applied to the base of the complementary symmetrical output transistor 49.52. In addition, the connection point between bias resistors 50 and 51 connected to the emitters of the output transistors is connected to a coupling capacitor 45.
It is connected to the primary winding of the output transformer for correcting the upper and lower pincushion distortion via the upper and lower pincushion distortion correction output transformers, and the secondary winding is connected in series to the deflection coil 37.
従って、水平周期の鋸歯状波電圧が増幅されて、二次巻
線に加わり、垂直偏向コイル３１には、この積分された
パラボラ波形の糸巻歪補正電流を流している。Therefore, the horizontally periodic sawtooth wave voltage is amplified and applied to the secondary winding, and the integrated parabolic waveform pincushion distortion correction current flows through the vertical deflection coil 31.
以上のようにして、垂直偏向回路と、上下糸巻歪補正回
路とが構成されているが、結合コンデンサ４７と可変イ
ンダクタンス４６との直列回路より構成された飛越走査
補正回路が、前述した第３図の回路と同様に、上下糸巻
歪補正回路出力端子と帰還抵抗３８との間に挿入され、
帰還抵抗３８に生じる上下糸巻歪補正電圧を相殺してい
る。As described above, the vertical deflection circuit and the vertical pincushion distortion correction circuit are constructed, but the interlaced scanning correction circuit constructed from the series circuit of the coupling capacitor 47 and the variable inductance 46 is shown in FIG. Similar to the circuit shown in FIG.
The vertical pincushion distortion correction voltage generated in the feedback resistor 38 is canceled out.
以上の実施例から明らかなように本発明は小型の可変イ
ンダクタンスとコンデンサとの直列回路を付加すること
により、飛越走査の乱れを完全に除去することができる
。As is clear from the above embodiments, the present invention can completely eliminate disturbances in interlaced scanning by adding a series circuit of a small variable inductance and a capacitor.
また本発明は上下糸巻歪補正量の大きい、偏向コイル、
陰極線管を用いる場合に特に有用である。The present invention also provides a deflection coil with a large amount of vertical pincushion distortion correction;
This is particularly useful when using cathode ray tubes.
第１図は従来の飛越走査補正装置の構成図、第２図はそ
の信号波形図、第３図は本発明の一実施例による飛越走
査補正装置の構成図、第４図はその具体的な構成を示す
結線図である。
１，３・・・・・・増幅器、２・・・・・・平衡変調器
、８・・・・・・垂直偏向コイル、９・・・・・・上下
糸巻歪補正用出力トランス、１２・・・・・・可変イン
ダクタンス、１３・・・・・・結合コンデンサ。FIG. 1 is a block diagram of a conventional interlaced scan correction device, FIG. 2 is a signal waveform diagram thereof, FIG. 3 is a block diagram of an interlaced scan correction device according to an embodiment of the present invention, and FIG. 4 is a detailed diagram of the interlaced scan correction device. FIG. 3 is a wiring diagram showing the configuration. 1, 3...Amplifier, 2...Balanced modulator, 8...Vertical deflection coil, 9...Output transformer for correcting vertical pincushion distortion, 12... ...Variable inductance, 13...Coupling capacitor.
Claims (1)
路と、前記垂直偏向コイルに流す偏向電流の直線性補正
用帰還回路と、共振周波数を水平走査周波数とほぼ一致
させたインダクタンスとコンデンサの直列回路とを備え
、前記直列回路から得られる信号を薊記上下糸巻歪補正
電流と逆方向の電流として前記直線性補正用帰還回路に
加えることを特徴とする飛越走査補正装置。1. A correction circuit that sends a vertical pincushion distortion correction current to the vertical deflection coil, a feedback circuit for linearity correction of the deflection current that flows to the vertical deflection coil, and a series circuit of an inductance and a capacitor that makes the resonance frequency almost match the horizontal scanning frequency. An interlaced scan correction device, characterized in that the signal obtained from the series circuit is applied to the linearity correction feedback circuit as a current in the opposite direction to the vertical pincushion distortion correction current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13427375A JPS5849064B2 (en) | 1975-11-08 | 1975-11-08 | Tobikoshisouchi |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13427375A JPS5849064B2 (en) | 1975-11-08 | 1975-11-08 | Tobikoshisouchi |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5258312A JPS5258312A (en) | 1977-05-13 |
| JPS5849064B2 true JPS5849064B2 (en) | 1983-11-01 |
Family
ID=15124419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13427375A Expired JPS5849064B2 (en) | 1975-11-08 | 1975-11-08 | Tobikoshisouchi |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5849064B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60131767U (en) * | 1984-01-30 | 1985-09-03 | 株式会社ノーリツ | water control valve |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4748384A (en) * | 1987-01-06 | 1988-05-31 | Zenith Electronics Corporation | Error signal cancellation for top/bottom pincushion correction circuit |
| JP2008030602A (en) * | 2006-07-28 | 2008-02-14 | Hitachi Constr Mach Co Ltd | Fuel tank cap for working machine |
-
1975
- 1975-11-08 JP JP13427375A patent/JPS5849064B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60131767U (en) * | 1984-01-30 | 1985-09-03 | 株式会社ノーリツ | water control valve |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5258312A (en) | 1977-05-13 |
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