JPS5842316A - Flag transmission system for plural analog-to-digital converters - Google Patents
Flag transmission system for plural analog-to-digital convertersInfo
- Publication number
- JPS5842316A JPS5842316A JP56139761A JP13976181A JPS5842316A JP S5842316 A JPS5842316 A JP S5842316A JP 56139761 A JP56139761 A JP 56139761A JP 13976181 A JP13976181 A JP 13976181A JP S5842316 A JPS5842316 A JP S5842316A
- Authority
- JP
- Japan
- Prior art keywords
- converter
- flag
- output
- converters
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
- H03M1/1076—Detection or location of converter hardware failure, e.g. power supply failure, open or short circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は複数ＡＤ変換器のフラグ送出方式に関し、さら
に詳しくは複数ＡＤ変換器が全て実装されているか否か
を検出する方式ＥＩＩ１するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flag sending method for multiple AD converters, and more specifically to a method EII1 for detecting whether all multiple AD converters are installed.
ＡＤ変換器を複数個用いて１組のデータを構成する場合
がある．例えば音声の分解合成等圧おいては音声を複数
の周波数帯域にＦａｉｌを用いて分解し各周波数帯域の
アナ■グ信号をＡＤ変換器によりディジタル信号に変換
しζれを合成して熟理する場合等がある。従来このよう
な複数個のＡＤ変換回路では全実装状態の検出が行なわ
れていないためその出力データが実際にＡＤ変換された
データか否かを判断できないという欠点がある．またレ
ディピットを使用して全実装検出を行う方式もあるがこ
の方式は全実装でない場合にレディが送出されないため
受信側で情報更新不要，すなわちデータがレディ状態で
ないため受信側でデータを読めない状態となる欠点があ
る。A set of data may be constructed using multiple AD converters. For example, in isobaric voice decomposition and synthesis, the voice is decomposed into multiple frequency bands using Fail, the analog signals of each frequency band are converted to digital signals by an AD converter, and the ζ errors are synthesized. There are cases etc. Conventionally, in such a plurality of AD conversion circuits, all the mounting states are not detected, so it is difficult to determine whether the output data is actually AD converted data or not. There is also a method that uses ready pits to detect all implementations, but this method does not send out a ready signal if not all implementations occur, so there is no need to update the information on the receiving side.In other words, the data cannot be read on the receiving side because the data is not in a ready state. There are drawbacks to the condition.
本発明の目的は１組のデータが複数のＡＤ変換器によシ
構成する場合．ＡＤ変換器の夷俟状態を検出してそのデ
ータが有効か無効かを指示するビットフラグを付加する
方式を提供することにある。The purpose of the present invention is to solve the problem when one set of data is configured by multiple AD converters. It is an object of the present invention to provide a method for detecting the abnormal state of an AD converter and adding a bit flag indicating whether the data is valid or invalid.
本発明によれば複数のＡＤ変換器を用いて１組のデータ
を構成する場合に、第１のＡＤ変換器の実装出力を第２
のＡＤ変換器の外部フラグとして入力し、・・・、第ｎ
−１のＡＤ変換器の実装出力を第ｎのＡＤ変換器の外部
フラグとして入力し、該第ｎのＡＤ変換器の実装出力を
前記第１ＯＡＤ変換器の外部フラグとして入力し、誼各
ＡＤ変換器には該外部フラグを入力し電位変化を検出す
るフラグ回路を有し前記第１ないし第ｎ ＯＡ Ｄ変換
器の７ラグ出力をオア回路を介してフラグビットとして
出力し、前記第１ないし第ｎのＡＤ変換器が全て実装さ
れているか否かを検出することを特徴とする複数ＡＤ変
換器のフラグ送出方式が提案される。According to the present invention, when configuring one set of data using a plurality of AD converters, the mounted output of the first AD converter is transferred to the second AD converter.
input as an external flag of the AD converter, ..., the nth
- input the mounted output of the first AD converter as an external flag of the n-th AD converter; input the mounted output of the n-th AD converter as the external flag of the first OAD converter; The converter has a flag circuit that inputs the external flag and detects potential changes, and outputs the 7-lag outputs of the first to n-th OA/D converters as flag bits via an OR circuit, and A flag sending method for multiple AD converters is proposed, which is characterized by detecting whether all n AD converters are installed.
以下本発明Ｋか＼る方式の実施例について図面により詳
細に説明する。Embodiments of the method according to the present invention will be described in detail below with reference to the drawings.
第１図は本発明にか＼る方式のｉ実施例を示すブロック
図であり同図において１ｍ、・・・、１（ｎ−１）、Ｉ
ｎはそれぞれＡＤ変換器、また２ｍ。FIG. 1 is a block diagram showing an i embodiment of the system according to the present invention.
n is an AD converter, and 2m.
−、２（ｎ−１） 、 ２ｎはそれぞれＡＤ変換器出カ
データである。フラグ構成ｔｉＡＤ変換＠１１の実装出
力３ａは図示されないＡＤ変換５１ｂの外部フラグとし
て入力し、・・・；ＡＤ変換５１（ｎ−１）はその前の
図示されないＡＤ変換器１（ｎ−２）よ〕外部フラグを
入力し、ＡＤ変換器１（ｎ−１）の実装出力３ （ｎ−
１）ａＡＤＡＤ変換５１ｒｌｎ部フラグとして入力し、
ＡＤ変換器Ｉｎの実装出力３ｎはＡＤ変換器１ｍの外部
フラグとして入力する。各ＡＤ変換器１ｇ、、＝・、
１ （ｎ−１） 。-, 2(n-1), and 2n are AD converter output data, respectively. The implementation output 3a of the flag configuration tiAD conversion @11 is input as an external flag of the AD conversion 51b (not shown), and...; The AD conversion 51 (n-1) is connected to the previous AD converter 1 (n-2) not shown. ] Input the external flag and output the mounted output 3 (n-1) of AD converter 1 (n-1).
1) Input as the aADAD conversion 51rln section flag,
The mounting output 3n of the AD converter In is inputted as an external flag of the AD converter 1m. Each AD converter 1g, =...
1 (n-1).
１ｎのフラグ出力４ ａ ｔ ”・ｅ ４ （ｎ−１）
ｌ ４ ｎ唸それぞれオア回路５ｍ、・・・、５（ｎ
−１）を介して異常表示フラグピット６として出力され
る。1n flag output 4 a t ”・e 4 (n-1)
l 4 n each OR circuit 5m,..., 5(n
-1) is output as an abnormality display flag pit 6.
第１図における各ＡＤ変換器の７′ｙグ回路構成はそれ
ぞれ同様となっておりこれを第２図に示す。The 7'y circuit configuration of each AD converter in FIG. 1 is the same, and this is shown in FIG. 2.
第２図はＡＤ変換器Ｉｎのフラグ回路構成を示す。FIG. 2 shows the flag circuit configuration of the AD converter In.
第２図に示すごと＜ＡＤ変換器の７２ダ入カおよび実装
出力の相互接続はＡＤ変換器Ｉｎの実装出力３ｎをＡＤ
変換５１ｍの外部フラグ入力として印加させＡＤ変換器
１（ｎ−１）の実装出力３（ｎ−１）を外部フラグ入力
としてそれぞれのＡＤ変換器は他の実装の有無を検出し
あっている。また各ＡＤ変換器の外部フラグ入力線には
任意の電源電圧（Ｖｃｃ）を抵抗器線用で与えられてお
シ他の実装の有無を検出するアースｔが断となった時外
部フラグ入力の電位が変化してフラグ出力を与、する、
そしてこれらの外部フラグ入力は他のイニシャルリセッ
ト、オーバーフロー、精度チェックエラー等のフラグと
ともにオア回路６ｎを介してフラグ出力４ｎとして出力
される。As shown in Figure 2, the interconnection of the 72-da input and mounting output of the AD converter is to
It is applied as an external flag input to the conversion 51m, and the mounting output 3 (n-1) of the AD converter 1 (n-1) is used as an external flag input, and each AD converter detects the presence or absence of other mounting. In addition, an arbitrary power supply voltage (Vcc) is applied to the external flag input line of each AD converter for the resistor line. The potential changes to give a flag output,
These external flag inputs are output as a flag output 4n through an OR circuit 6n together with other flags such as initial reset, overflow, accuracy check error, etc.
第２図のごとくフラグ回路を構成することによりいずれ
のＡＤ変換器が実装されていなくてもそれを外部フラグ
入力としているＡＤ変換器よシフラグ出力されこれによ
り実装状態を検出することができる。これによ、？ＡＤ
変換器の実装状態が検出でき出力ｒ−夕の有効性の判断
ができる効果がある。By configuring the flag circuit as shown in FIG. 2, even if any AD converter is not mounted, the flag is output from the AD converter which uses it as an external flag input, thereby making it possible to detect the mounting state. What about this? A.D.
This has the effect that the mounting state of the converter can be detected and the validity of the output r-value can be determined.
以上詳細に説明したごとく本発明によれば複数ＡＤ変換
器構成の場合の実装状態を７２グψツトを用いて表わす
ことができその出力データが有効なものであるか否かを
判断し無効データの送出金防ぐととができる。As explained in detail above, according to the present invention, the mounting state in the case of a plurality of AD converter configuration can be expressed using 72 points, and it is possible to judge whether the output data is valid or not. It is possible to prevent the withdrawal of funds.
さらに本発明にか＼る方式において単数のＡＤ変換器回
路構成として使用する場合でも検知入力信号線を接地す
るだけでよく回路変更することなく単数、複数のＡＤ変
換器回路構成として使用できる。Furthermore, even when the method according to the present invention is used as a single AD converter circuit configuration, it is sufficient to simply ground the detection input signal line, and the circuit can be used as a single or multiple AD converter circuit configuration without changing the circuit.
第１図は本発明にが＼る複数ＡＤ変換器のフラグ送出方
式の１実施例のブロック図、第２図は第１図の各変換器
のフラグ回路構成の１例を示す。
図において、ｌ ｍ 、−＝、 １ （ｎ−１） 、
ＩｎがＡＤ変換器、３ａ ＠・＝、３（ｎ−１）、３ｎ
が実装出力ｓ ４ ａ ｓ ＝・９４ （ｎ −ｌ）
ｅ ４ ｎがフラグ出力、５＊、・ 、５（ｎ−１）が
オア回路、６が】フラグビットである。FIG. 1 is a block diagram of an embodiment of a flag sending system for multiple AD converters according to the present invention, and FIG. 2 shows an example of the flag circuit configuration of each converter in FIG. 1. In the figure, l m , -=, 1 (n-1),
In is an AD converter, 3a @・=, 3(n-1), 3n
is the implementation output s 4 a s =・94 (n − l)
e4n is a flag output, 5*, . . . , 5(n-1) is an OR circuit, and 6 is a flag bit.
Claims (1)
に、第１のＡＤ変換器の実装出力を第２のＡＤ変換器の
外部フラグとして入力し、・・・、第ｎ−１のＡＤ変換
器の実装出力を第ｎ０ＡＤ変換器の外部フラグとして入
力し、該第ｎのＡＤ変換器の実装出力を前記第１のＡＤ
変換器の外部ブラダとして入力し、骸各ＡＤ変換器には
鋏外部ブッダを入力し電位変化を検出するフラグ回路を
有し、前記第１ないし第ｎ０ＡＤ変換器のフラグ出力を
オア回路を介して７ラダビツトとして出力し、前記第１
ないし第ｎのＡＤ変換器が全て実装されているか否かを
検出することを特徴とする複数ＡＤ変換器の７ラグ送出
方式。When configuring one set of data using a plurality of AD converters, input the implementation output of the first AD converter as an external flag of the second AD converter, ..., the (n-1)th The mounted output of the AD converter is input as an external flag of the n0th AD converter, and the mounted output of the nth AD converter is inputted to the first AD converter.
Each AD converter has a flag circuit that inputs the external bladder of the converter and detects a potential change, and the flag output of the first to n0th AD converters is inputted to the external bladder of the converter through an OR circuit. output as 7 radabits, and
A 7-lag transmission method for a plurality of AD converters, characterized by detecting whether or not all of the n-th AD converters are installed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56139761A JPS5842316A (en) | 1981-09-07 | 1981-09-07 | Flag transmission system for plural analog-to-digital converters |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56139761A JPS5842316A (en) | 1981-09-07 | 1981-09-07 | Flag transmission system for plural analog-to-digital converters |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5842316A true JPS5842316A (en) | 1983-03-11 |
Family
ID=15252767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56139761A Pending JPS5842316A (en) | 1981-09-07 | 1981-09-07 | Flag transmission system for plural analog-to-digital converters |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5842316A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008501505A (en) * | 2004-06-03 | 2008-01-24 | アルファ ラヴァル コーポレイト アクチボラゲット | Apparatus and method for purifying gas |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS423601Y1 (en) * | 1964-10-31 | 1967-03-02 | ||
| JPS5423440A (en) * | 1977-07-25 | 1979-02-22 | Hitachi Ltd | Information processor |
-
1981
- 1981-09-07 JP JP56139761A patent/JPS5842316A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS423601Y1 (en) * | 1964-10-31 | 1967-03-02 | ||
| JPS5423440A (en) * | 1977-07-25 | 1979-02-22 | Hitachi Ltd | Information processor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008501505A (en) * | 2004-06-03 | 2008-01-24 | アルファ ラヴァル コーポレイト アクチボラゲット | Apparatus and method for purifying gas |
| JP4885127B2 (en) * | 2004-06-03 | 2012-02-29 | アルファ ラヴァル コーポレイト アクチボラゲット | Apparatus and method for purifying gas |
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