JPS5840962U - line monitor device - Google Patents
line monitor deviceInfo
- Publication number
- JPS5840962U JPS5840962U JP1981135405U JP13540581U JPS5840962U JP S5840962 U JPS5840962 U JP S5840962U JP 1981135405 U JP1981135405 U JP 1981135405U JP 13540581 U JP13540581 U JP 13540581U JP S5840962 U JPS5840962 U JP S5840962U
- Authority
- JP
- Japan
- Prior art keywords
- information
- memory
- stores
- monitor device
- line monitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Digital Computer Display Output (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示す構成図ならびに第２図
ａおよびｂはそれぞれ本実施例および従来のナイスプレ
イ上の表示状態を示す図である。
図において、１１・・・・・・マイクロプロセッサ、１
２・・・・・・プログラムメモリ、１３・・・・・・プ
ロトコルメモリ、１４・・・・・・ポインタメモーリ、
１５・・・・・・ディスプレイフォーマットメモリ、１
６・・・・・・ラインレシーバ、１７°°°°°°バツ
フアメモリ、１９・・・・・・ディスプレイ、２０・・
曲ディスプレイメモリ。FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2a and 2b are diagrams showing display states on the present embodiment and the conventional Nice Play, respectively. In the figure, 11...microprocessor, 1
2...Program memory, 13...Protocol memory, 14...Pointer memory,
15...Display format memory, 1
6... line receiver, 17°°°°° buffer memory, 19... display, 20...
Song display memory.
Claims (1)
数の第１の情報を一時記憶するバッファメモリと、前記
複数の第１の情報に対応する複数の第２の情報が予め記
憶された第１のメモリと、前記複数の第１の情報に対応
する複数の第３の情報が予め記憶された第２のメモリと
、前記複数の第２の情報を予め定めた形式にもとづいて
表示しポインタを所望の第２の情報の位置に移動させた
ときに対応する第３の情報を表示するディスプレイと、
該ディスプレイ上の前記複数の第２の情報の位置と前記
バッファメモリ内の対応する前記第１の情報の位置との
対応関係が記憶されるポインタメモリとを備えたことを
特徴とする回線モニタ装置。a line receiver that receives a plurality of first information; a buffer memory that temporarily stores the plurality of first information; and a line receiver that stores a plurality of second information corresponding to the plurality of first information in advance. 1 memory, a second memory in which a plurality of third information corresponding to the plurality of first information is stored in advance, and a pointer for displaying the plurality of second information based on a predetermined format. a display that displays corresponding third information when the is moved to a desired second information position;
A line monitoring device comprising: a pointer memory that stores a correspondence relationship between the positions of the plurality of second pieces of information on the display and the corresponding positions of the first pieces of information in the buffer memory. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981135405U JPS5840962U (en) | 1981-09-11 | 1981-09-11 | line monitor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981135405U JPS5840962U (en) | 1981-09-11 | 1981-09-11 | line monitor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5840962U true JPS5840962U (en) | 1983-03-17 |
| JPS635305Y2 JPS635305Y2 (en) | 1988-02-13 |
Family
ID=29928774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1981135405U Granted JPS5840962U (en) | 1981-09-11 | 1981-09-11 | line monitor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5840962U (en) |
-
1981
- 1981-09-11 JP JP1981135405U patent/JPS5840962U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS635305Y2 (en) | 1988-02-13 |
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