JPS5840881A - Manufacture of buried hetero-structure semiconductor laser-photodiode beam integrating element - Google Patents
Manufacture of buried hetero-structure semiconductor laser-photodiode beam integrating elementInfo
- Publication number
- JPS5840881A JPS5840881A JP56138953A JP13895381A JPS5840881A JP S5840881 A JPS5840881 A JP S5840881A JP 56138953 A JP56138953 A JP 56138953A JP 13895381 A JP13895381 A JP 13895381A JP S5840881 A JPS5840881 A JP S5840881A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- photodiode
- laser
- inp
- semiconductor laser
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
- H01S5/0262—Photo-diodes, e.g. transceiver devices, bidirectional devices
- H01S5/0264—Photo-diodes, e.g. transceiver devices, bidirectional devices for monitoring the laser-output
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
- H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は埋め込みへテロ構造半導体レーザとＰＮ接合型
フォトダイオードとが同一半導体基板上に集積化された
埋め込みへテロ構造半導体レーザ・フォトダイオード光
集積化素子の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a buried heterostructure semiconductor laser/photodiode optical integrated device in which a buried heterostructure semiconductor laser and a PN junction photodiode are integrated on the same semiconductor substrate. .
近年光半導体素子や光ファイバの高品質化が進み、光フ
アイバ通信の実用化が進みつつある。それにつれ各種光
素子を一体化してシステムの安定化をはかろうという気
運が高まってきており、半導体レーザ、半導体受光素子
、光変調素子、光増幅素子等各釉光半導体素子の７１イ
ブリツド的な、あるいはモノリシックな集積回路化がは
かられ、２−
光集積回路という新しい研究分野が発展しつつある。中
でも半導体レーザ、発光ダイオード等の発光素子と受光
素子とが集積化は光源の光出力をモニタする必要性から
システム構成上重要であると考えられ、それらを同一半
導体基板上に形成するモノリシックな集積化が関心を集
めている。半導体レーザと受光素子とのモノリシックな
集積化をめざしたものとして、例えば１９８０年発行の
エレクトロニクス、レターズ（Ｅｌｅｃｔｒｏｎｉｃｓ
Ｌｅｔｔｅｒｓ ）誌、第１６巻、第９号、第３４２
頁から第３４３頁に報告された伊賀氏らによる化学エツ
チングミラー面を用いたＧａＩｎＡｓＰ ／ ＩｎＰレ
ーザ・受光素子の集積化素子がある。これは通常の絶縁
膜ストライプレーザの一方の共振器面を化学エツチング
によって形成し、このエツチング共振器面に相対した面
をフォトダイオードの受光面としておシ、化学エツチン
グによって形成されたレーザ共振器面からの光出力をモ
ニタすべくフォトダイオードが配置された半導体レーザ
・フォトダイオード集積化素子である。この集積化素子
の絶縁膜ストライプレーザに正のバイアスをかけて電流
を流してレーザ発振を生じさせ、フォトダイオードに外
部抵抗を介して負のバイアスをかけることにより、その
レーザ出力光をモニタすることができる。In recent years, the quality of optical semiconductor elements and optical fibers has improved, and optical fiber communications are being put into practical use. As a result, there is a growing trend to stabilize systems by integrating various optical devices, and 71-bridled optical semiconductor devices such as semiconductor lasers, semiconductor photodetectors, optical modulation devices, and optical amplification devices are being developed. , or monolithic integrated circuits, and a new research field called 2-photonic integrated circuits is developing. In particular, integration of light-emitting elements such as semiconductor lasers and light-emitting diodes with light-receiving elements is considered to be important in system configuration due to the need to monitor the optical output of the light source, and monolithic integration in which they are formed on the same semiconductor substrate is considered important. is attracting attention. For example, Electronics Letters published in 1980 aimed at monolithic integration of semiconductor lasers and photodetectors.
Letters) Magazine, Volume 16, No. 9, No. 342
There is an integrated GaInAsP/InP laser/photodetector device using a chemically etched mirror surface by Mr. Iga et al. reported on pages 343 to 343. In this method, one cavity surface of an ordinary insulating film stripe laser is formed by chemical etching, and the surface opposite to this etched cavity surface is used as the light receiving surface of the photodiode. This is a semiconductor laser/photodiode integrated element in which a photodiode is arranged to monitor the optical output from the semiconductor laser. A positive bias is applied to the insulating film stripe laser of this integrated element, and a current is applied to cause laser oscillation, and the laser output light is monitored by applying a negative bias to the photodiode via an external resistor. Can be done.
しかしながら、この例ではレーザ共振器軸上に受光素子
を配置しているため、レーザ共振器形成のために通常の
へき闘技術を使うことができず、化学エツチング法を用
いておシ、それによってレーザ自身の発振しきい値が上
がってしまう他に、製作が容易でなく歩留シが悪い等の
欠点があった。However, in this example, since the photodetector is placed on the laser cavity axis, it is not possible to use normal cleavage techniques to form the laser cavity, and a chemical etching method is used. In addition to raising the oscillation threshold of the laser itself, it also has drawbacks such as difficulty in manufacturing and poor yield.
本発明の目的は、これらの欠点を克服すべく、高性能な
埋め込みへテロ構造半導体レーザとＰＮ接合型フォトダ
イオードとを同一半導体基板上に集積化した埋め込みへ
テロ構造半導体レーザ・フォトダイオード光集積化素子
を再現性よく製造する製造方法を提供することにある。In order to overcome these drawbacks, the object of the present invention is to provide a buried heterostructure semiconductor laser/photodiode optical integration in which a high-performance buried heterostructure semiconductor laser and a PN junction photodiode are integrated on the same semiconductor substrate. An object of the present invention is to provide a manufacturing method for manufacturing a chemical element with good reproducibility.
本発明によれば、活性層の周囲がよシエネルギーギャッ
プが大きく屈折率が小さい半導体材料でおおわれている
埋め込みへテロ構造半導体レーザとフォトダイオードと
が同−半導体基板上に集積化された埋め込みへテロ構造
半導体レーザ・７オトダイオード光集積化素子の製造方
法において、第１導電型（１００）ＩｎＰ基板上に第２
導電型Ｉｎ１−３ｆＧａｘＡｓＩ Ｆ”Ｆ （ｏ≦ｘ
（１、Ｏ（ｙ≦１）層を形成した後、＜０１１＞方向に
平行な２本のストライプ状の溝を前記第２導電型Ｉｎ１
−ｘＧａ、Ａｓ１−７２７層をつきぬけるまでエツチン
グして形成する工程と、それらの溝中に第１導電型Ｉｎ
Ｐ層、Ｉ ｎ １−２ Ｇａ ｊＡｓ １−１Ｐｙ（ｘ
＜ｘ′（１、ｙ′＜１≦１）層を溝のふちでとぎれるよ
うに、さらにそれに続いて第２導電型ＩｎＰ層を順次成
長させるエピタキシャル成長工程と、上記２つの溝の中
間の一部をエピタキシャル成長層側からＩ ｎ １−
ｘＧａ ｘＡｓ １−１Ｐｙ層までをエツチングして除
去する工程とを含むことを特徴とする埋め込みへテロ構
造半導体レーザ・フォトダイオード光集積化素子の製造
方法が得られる。According to the present invention, a buried heterostructure semiconductor laser and a photodiode, in which the periphery of the active layer is covered with a semiconductor material having a large energy gap and a low refractive index, are integrated on the same semiconductor substrate. In the method for manufacturing a terror structure semiconductor laser/7-otodiode optical integrated device, a second conductivity type (100) InP substrate is
Conductivity type In1-3fGaxAsI F”F (o≦x
(1. After forming the O(y≦1) layer, two stripe-shaped grooves parallel to the <011> direction are formed in the second conductivity type In1.
-xGa, As1-727 layer is etched until it penetrates, and the first conductivity type In is formed in those grooves.
P layer, In 1-2 Ga jAs 1-1Py(x
An epitaxial growth step in which a second conductivity type InP layer is successively grown so that the <x' (1, y'<1≦1) layer is stopped at the edge of the groove, and a part of the middle between the two grooves. I n 1− from the epitaxial growth layer side
A method for manufacturing a buried heterostructure semiconductor laser/photodiode optical integrated device is obtained, which includes a step of etching and removing up to the xGa xAs 1-1Py layer.
実施例を述べる前に本素子の動作原理を説明する。通常
埋め込みへテロ構造半導体レーザ（以下ＢＨ−ＬＤと略
す）ではレーザ共振軸にそった側面の平坦度がいくらか
悪いため、この面で光が散乱５−
を受けて放射される。このことは通常のＢＨ−ＬＤにお
いては発光遠視野像に悪影響をおよぼしているが、これ
を利用すれば、このＢＨ−ＬＤの横にＰＮ接合型フォト
ダイオード（以下ＰＤと略す）を配置することによって
、レーザ光をモニターすることができる。Before describing embodiments, the operating principle of this device will be explained. Typically, in a buried heterostructure semiconductor laser (hereinafter abbreviated as BH-LD), the flatness of the side surface along the laser resonance axis is somewhat poor, so light is scattered and emitted from this surface. This has a negative effect on the emission far-field image in a normal BH-LD, but if you take advantage of this, you can place a PN junction photodiode (hereinafter abbreviated as PD) next to this BH-LD. Laser light can be monitored by
本発明によれは、とのＢＨ−ＬＤに特有な性質を利用し
て散乱された光を検出すべく、同一半導体基板上にレー
ザ光の光放射方向に対してその横側にＦＤが自動的に形
成されたＢＨ−ＬＤ 、ＰＤ光集積化素子を製造するだ
めの製造方法が得られ、その際本発明の構成によれば、
レーザ共振器の形成に従来と同じへき開法が使えるので
ＢＨ−ＬＤの性能を損なうことなく、製作歩留りもよい
。According to the present invention, an FD is automatically installed on the same semiconductor substrate on the side of the laser beam in the light emission direction in order to detect the scattered light by utilizing the characteristics unique to the BH-LD. A manufacturing method for manufacturing a BH-LD, PD optical integrated device formed in a semiconductor device is obtained, in which according to the configuration of the present invention,
Since the same cleavage method as conventional methods can be used to form the laser resonator, the performance of the BH-LD is not impaired and the manufacturing yield is good.
以下図面を用いて本発明の詳細な説明する。The present invention will be described in detail below using the drawings.
第１図は本発明の第１の実施例の製造方法を示すだめの
断面図である。まず第１図において、（１００）ｎ−Ｉ
ｎＰ基板１０１上にｎ−ＩｎＰバフ７７層１０２（Ｔｅ
ドープ、厚さ約５μｍ）、１．１μｍ発光波長組成のｐ
−ＩｎＧａＡｓＰ 電流ブロック層１０３０ＪＩＩ
Ｏ，１２０，２１１０，７７−６＝
（Ｚｎドープ、厚さ約１μｍ）を順次成長させ、はじめ
の液相エピタキシャル（以下ＬＰＥと略す）成長を終え
る。次に第１図（２）において通常のフォトレジストの
手法を用いてＨ１！８０４ ： Ｈ２Ｏ２： ＨｚＯ＝
３：１：１の選拓エツチング液を用いて＜ ０１１ ＞
方向に平行に幅２μｍ１間隔１００μ飢の２本の平行な
ストライプ、すなわちＢ）（−ＬＤ用ストライプ１０４
とＰＤ用ストライプ１０５とをぬく。この際エツチング
条件を適当に選んでやることによシ、図に示したように
エツチング側面とエピタキシャル成長層表面とが垂直よ
りも、少し深くえぐれた、いわゆる逆メサ形状にエツチ
ングすることができる。FIG. 1 is a cross-sectional view showing a manufacturing method of a first embodiment of the present invention. First, in Figure 1, (100)n-I
An n-InP buff 77 layer 102 (Te
doped, about 5 μm thick), 1.1 μm emission wavelength composition p
-InGaAsP current blocking layer 1030JII
O, 120, 2110, 77-6= (Zn-doped, about 1 μm thick) are sequentially grown to complete the initial liquid phase epitaxial (hereinafter abbreviated as LPE) growth. Next, in FIG. 1 (2), H1!804: H2O2: HzO=
Using a selective etching solution of 3:1:1 <011>
Two parallel stripes parallel to the direction with a width of 2 μm and an interval of 100 μm, that is, B) (−LD stripe 104
and PD stripe 105. At this time, by appropriately selecting the etching conditions, it is possible to form a so-called inverted mesa shape in which the etched side surface and the surface of the epitaxial growth layer are hollowed out a little deeper than perpendicular to each other, as shown in the figure.
このようにするとこの後につづく埋め込み成長の再現性
がよい。またエツチングされたストライプの深さは・は
じめのｐ−Ｉ ” ｏ 、ａａ Ｇａ ０．□２Ａｓ
ｏ、２． Ｐ ｏ、ｒ□電電流ブロク２層１０３厚さで
自動的に決まってしまうため、その再現性、制御性はは
じめのＬＰＥ成長で決まり、きわめて制御性にすぐれて
いる。In this way, the reproducibility of the subsequent buried growth is good. Also, the depth of the etched stripe is: - Initial p-I ” o , aa Ga 0.□2As
o, 2. Since P o, r □ is automatically determined by the thickness of the two current block layers 103, its reproducibility and controllability are determined by the initial LPE growth, and the controllability is extremely excellent.
次に第１図（３）において埋め込み成長を行なう。ｎ−
ＩｎＰｎソバ２フフ
ノンドープＩｎ０．７０”０．３０Ａ８０．６５ＰＯＪ
Ｓ層１０７（λ＝１、３μｍ１発光波長組成、ストライ
プ部厚さ約０．２μｍ＞、ｐ−ＩｎＰ埋め込み層１０８
（Ｚｎドープ、平坦部厚さ２、 ５μｍ ） 、ｎ−Ｉ
ｎＧａＡｓＰ電極層１０９ （Ｔｅドープ、厚さ０．
５μ風、発光波長組成は任意）を順次ＬＰＥ成長させる
。なお、この際結晶成長条件を選んでやることによりＢ
）１−ＬＤの活性層、およびＰＤのキャリア発生領域と
なるノンドープＩｎ Ｇａ Ａｓ Ｐ 層は図
に示すようにスト０、７０ ０ＪＯ Ｏ．
６５ ０．３５ライブのふちでとぎれるように成長さ
せ、ストライプ内このＩｎ Ｇａ Ａｓ Ｐ
層が埋め込ま０、、７０ ０．３０ ０．
６５ ０．３６れるようにすることができる。最後に
第１図（４）において結晶成長を終えたウェファのプロ
セスを行なう。まずＢＨ−ＬＤ１１２とＰＤ１１７部分
の２つのエツチングストライプの上部に幅４〜５μｍ１
深さ２μｍ程度、Ｐ形不純物であるＺｎを拡散してＢＨ
−ＬＤ部Ｚｎ拡散層１１０、ＰＤ部Ｚｎ拡散層１１１を
形成した後、２つのエツチングストライプの中間部分に
幅４０μｍ程度のストライプ状にフォトレジストマスク
をぬいて、その部分のｎ−ＩｎＧａＡｓＰ電極層１０９
、ｐ−ＩｎＰ埋め込み層１０ ８ ｓ Ｉ ” ｏ．ｔ
ｏＧＭ ｏ．３ｏＡ’ ｏ 、、、Ｐ ０．３。Next, in FIG. 1(3), buried growth is performed. n-
InPn buckwheat 2 fufunone doped In0.70”0.30A80.65POJ
S layer 107 (λ=1, 3 μm1 emission wavelength composition, stripe portion thickness approximately 0.2 μm>, p-InP buried layer 108
(Zn doped, flat part thickness 2.5 μm), n-I
nGaAsP electrode layer 109 (Te doped, thickness 0.
5μ wind, emission wavelength composition is arbitrary) are sequentially grown by LPE. In addition, by selecting the crystal growth conditions at this time, B
)1-The active layer of the LD and the non-doped InGaAsP layer which becomes the carrier generation region of the PD are made of 0, 70, 0, 0, 0, 0, 70, 0, 0, 70, 0, 70, 0, 0, 70, 0, 70, 0, 70, 0, 70, 0, 0, 70, 0, 70, 0, 70, 0, 70, 0, 70, 0, 70, 0.
65 0.35 Grow so that it breaks at the edge of the live, and grow this In Ga As P within the stripe.
Layer embedded 0,,70 0.30 0.
65 0.36 Finally, in FIG. 1(4), the wafer after crystal growth is processed. First, a width of 4 to 5 μm1 is etched on the top of the two etching stripes on the BH-LD112 and PD117 parts.
BH by diffusing Zn, which is a P-type impurity, to a depth of approximately 2 μm.
- After forming the LD part Zn diffusion layer 110 and the PD part Zn diffusion layer 111, a photoresist mask is cut out in a stripe shape with a width of about 40 μm in the middle part between the two etching stripes, and the n-InGaAsP electrode layer 109 is formed in that part.
, p-InP buried layer 10 8 s I” o.t.
oGM o. 3oA'o,,,P 0.3.
層１０７を順次選拓エツチングする。次にＳ ｊｏｇ絶
縁膜１１３を選拓エツチングした部分付近のみ残して形
成し、ＡｕＺｎを蒸着して、こんどはエツチングした部
分のみをとシ去ってＢＨ−ＬＤ用Ｐ形オーミック性電極
１１４、ＰＤ用Ｐ形オーミック性電極１１５を形成する
。つぎに裏面ケンマした後基板側にＡｕＳｎオーミック
性電極を形成してウェファからチップに切り出すことに
よシ埋め込みへテロ構造半導体レーザ・フォトダイオー
ド光集積化素子が得られた。この素子のＢＨ−ＬＤ １
１２に正のバイアスをかけて電流を流し、レーザ発振さ
せると，ＢＨ−ＬＤの活性層のふちでレーザ光の一部が
散乱される。The layers 107 are sequentially selectively etched. Next, the S jog insulating film 113 is formed leaving only the selectively etched portions, and AuZn is deposited, and only the etched portions are removed to form the P-type ohmic electrode 114 for BH-LD and the P-type ohmic electrode 114 for PD. A P-type ohmic electrode 115 is formed. Next, after the back surface was hardened, an AuSn ohmic electrode was formed on the substrate side, and the wafer was cut into chips to obtain a buried heterostructure semiconductor laser/photodiode optical integrated device. BH-LD 1 of this element
When a positive bias is applied to 12 and a current is applied to cause laser oscillation, a portion of the laser light is scattered at the edge of the active layer of the BH-LD.
この散乱光はｐ−ＩｎＧａＡｓＰ 電流プロ０、８８
０．１２ ０．２Ｂ ０．７７ツク層
によシ光ガイドされ、横に配置されたＰＤ１１７に逆バ
イアスをかけておくことにより、レーザ出力光をモニタ
することができた。This scattered light is p-InGaAsP current pro 0,88
0.12 0.2B 0.77 Laser output light could be monitored by applying a reverse bias to the PD 117 placed laterally and guided by the light layer.
第２図は本発明による第２の実施例の埋め込みへテロ構
造半導体レーザ・フォトダイオード光集積化素子の斜視
図である。この場合には第１の実９−
施例における１回めのＬＰＥ成長によるｐ−Ｉｎ−０、
８８
” ０．１２ＡＳ０．２Ｂ ＰＯ．７７電流ブロック層
１０３のかわりに、あらかじめ（１００） ｎ−ＩｎＰ
基板２０１上にＰ形不純物であるＺｎを１μｍ程度拡散
しておく。このＺｎ拡散電流ブロック層２０２をつきぬ
けてエツチングすることによシ、ＢＨ−ＬＤ ２１３、
およびＰＤ２１４用のエツチングストライプを形成する
。あとは第１の実施例と全く同様に埋め込み成長および
それにつづくプロセスを行なえびよい。この第２の実施
例の場合には第１の実施例の場合のようにＺｎ拡散電流
ブロック層２０２は光ガイドとはならないが、ただ一度
のＬＰＥ成長だけで製造できるという特徴がある。FIG. 2 is a perspective view of a buried heterostructure semiconductor laser/photodiode optical integrated device according to a second embodiment of the present invention. In this case, p-In-0 by the first LPE growth in the first example 9-
88'' 0.12AS0.2B PO.77 Instead of the current blocking layer 103, (100) n-InP
Zn, which is a P-type impurity, is diffused onto the substrate 201 to a thickness of about 1 μm. By etching through this Zn diffusion current blocking layer 202, the BH-LD 213,
And etching stripes for PD214 are formed. After that, the buried growth and subsequent processes are carried out in exactly the same manner as in the first embodiment. In the case of this second embodiment, the Zn diffused current blocking layer 202 does not serve as a light guide as in the case of the first embodiment, but it is characterized in that it can be manufactured by only one LPE growth.
上記２つの実施例においてはいずれも化学エツチング法
によらない、通常のへき開技術が使えるため，ＢＨ−Ｌ
Ｄの発振しきい値電流が上昇したり、歩留りが悪くなる
ということはなく、シかもＢＨ−ＬＤに対してレーザ共
振軸の横側に自動的にＰＤが形成され、高性能ＢＨ−Ｌ
Ｄの性能を何ら損なうことなく、モニタ用ＰＤを同一半
導体基板上に歩留り １ ０−
良く集積化できた。In both of the above two examples, ordinary cleavage techniques can be used without using chemical etching methods, so BH-L
There is no increase in the oscillation threshold current of the D, there is no decrease in the yield, and the PD is automatically formed on the side of the laser resonance axis compared to the BH-LD, resulting in a high-performance BH-L.
Monitoring PDs could be integrated on the same semiconductor substrate at a high yield of 10- without impairing the performance of the D.
なお前記第１の実施例においてはｐ形電流ブロック層と
して１．１４ｍ発光波長組成の””０．８８Ｇａ Ａ
ｓ Ｐ 層を用いたが、これは活性層よ０．１２
０．２ａ ０．７７
ｐもエネルギーギャップの大きなｎ−ＩｎＧａＡｓＰ層
であればよく、また活性層も実施例においては１．３μ
ｍ発光波長組成の”０．７０”０．８Ｇ”０．６５ＰＯ
，８１層を用いたが、ＩｎＰと格子整合のとれた任意の
発光波長組成のＩｎＧａＡｓＰ層でもさしつかえない。In the first embodiment, the p-type current blocking layer is made of "0.88 Ga A" having an emission wavelength composition of 1.14 m.
s P layer was used, which is 0.12 times smaller than the active layer.
0.2a 0.77 P may also be an n-InGaAsP layer with a large energy gap, and the active layer is also 1.3μ in the example.
m emission wavelength composition "0.70"0.8G" 0.65PO
.
さらに上記２つの実施例においては、ＢＨ−ＬＤ用の溝
およびＰＤ用の溝の幅をいずれも２〜３μｍにとったが
、ＰＤ用の溝幅は２〜３μｍと限定することなく、よシ
広くともかまわない。Furthermore, in the above two examples, the widths of the BH-LD groove and the PD groove were both set to 2 to 3 μm, but the width of the PD groove is not limited to 2 to 3 μm; It doesn't matter if it's wide.
本発明においては、レーザ共振器形成に際しては常のへ
き闘技術を用いることができ、レーザ特性になんら影響
を与えずに、レーザ光出力のモニタ用ＰＤと高性能ＢＨ
−ＬＤとが自動的に同一半導体基板上に集積化される製
造方法を提供している。In the present invention, when forming a laser resonator, it is possible to use a conventional cracking technique, and a PD for monitoring laser light output and a high-performance BH can be used without affecting the laser characteristics.
-LD is automatically integrated on the same semiconductor substrate.
第１図（１）〜（４）は、本発明による第１の実施例の
製造方法を示すため９断面図、第２図は本発明による第
２の実施例の斜視図である。
図中１０１．２０１は（１００） ｎ−ＩｎＰ基板、１
０２．１０６．２０３はｎ−１ｎＰバツフアｆｆｉ、１
０３Ｕｐ−Ｉｎ −０，８８
”０．１２人Ｓ０．２３”０．７７電流ブ０７り層、２
０２はＺｎ拡散電流ブロック層、１ｏ４はＢＨ−ＬＤ用
エツチングストライプ、１ｏ５はＰＤ用エツチングスト
ライプ、１０７．２０４はＩｎ Ｇａ Ａｓ Ｐ
層、１０８．０．７０ ０．８０ ０．６１１
０４ｇ２０５はｐ−ＩｎＰ埋め込み層、 ｌ ０９
．２０６ Ｊｄ ｎ−ＩｎＧａＡｓＰ電極層、１１０．
２０７はＢＨ−ＬＤ部Ｚｎ拡散層、１１１．２０８はＰ
Ｄ部Ｚｎ拡散層、１１４．１１５．２１０，２１１はｐ
形オーミック性電極、１１６．２１２はｎ形オーミック
性電極、１１３．２０９は５ｉｎ２絶縁膜、１１２．２
１３はＢＨ−ＬＤ、 １１７．２１４はＰＤである。FIGS. 1 (1) to (4) are 9 cross-sectional views showing the manufacturing method of the first embodiment according to the present invention, and FIG. 2 is a perspective view of the second embodiment according to the present invention. 101.201 in the figure is (100) n-InP substrate, 1
02.106.203 is n-1nP buffer ffi, 1
03Up-In -0,88 ``0.12 people S0.23'' 0.77 Current flow 07 layer, 2
02 is a Zn diffusion current blocking layer, 1o4 is an etching stripe for BH-LD, 1o5 is an etching stripe for PD, 107.204 is InGaAsP
layer, 108.0.70 0.80 0.611
04g205 is p-InP buried layer, l 09
．． 206 Jd n-InGaAsP electrode layer, 110.
207 is the BH-LD part Zn diffusion layer, 111.208 is P
D part Zn diffusion layer, 114, 115, 210, 211 are p
type ohmic electrode, 116.212 is n-type ohmic electrode, 113.209 is 5in2 insulating film, 112.2
13 is BH-LD, 117.214 is PD.
Claims (1)
が小さい牛導体材料ヤおおわれている埋め込みへテロ構
造半導体レーザとフォトダイオードとが同一半導体基板
上に集積化された埋め込みへテロ構造半導体レーザ・フ
ォトダイオード光集積化素子の製造方法において、第１
導電型（Ｚｏｏ）ＩｎＰ基板上に第２導電型Ｉｎ１−ｘ
ＧａｘＡｓｔ−ｙＰｙ （０（ｘ（１，０＜ｙ≦１）層
を形成した後、＜０１１＞方向に平行な２本のストライ
ブ状の溝を前記第２導電型Ｉｎ１−ｘＧａｘＡｓｔ−ｙ
Ｐｙ層をつきぬけるまでエツチングして形成する工程と
、それらの溝中に第１導電型ＩｎＰ層、Ｉｎ １−ｘ′
Ｇａ； Ａａｔ−ｙ’Ｐｙ’ （ｘ（ｊ（ｔ、］＜ｙ≦
１）層を溝のふちでとぎれるように、さらにそれに続い
て第２導電型ＩｎＰ層を順次成長させるエピタキシャル
成長工程と、前記２つの溝の中間の一部をエピタキシャ
ル成長層側から前記Ｉｎ１−ｘ’ＧａｊＡｓ１−ｙ’
Ｐｙ’層までをエツチングして除去する工程とを含むこ
とを特徴とする埋め込みへテロ構造半導体レーザ・フォ
トダイオード光集積化素子の製造方法。The active layer is surrounded by a conductive material with a large energy gap and a low refractive index.A buried heterostructure semiconductor laser and a photodiode are integrated on the same semiconductor substrate. In the method for manufacturing a diode optical integrated device, the first
Second conductivity type In1-x on conductivity type (Zoo) InP substrate
After forming the GaxAst-yPy (0(x(1,0<y≦1) layer, two stripe-shaped grooves parallel to the <011> direction are
A process of etching the Py layer until it penetrates, and forming a first conductivity type InP layer, In 1-x', in the grooves.
Ga; Aat-y'Py'(x(j(t,]<y≦
1) An epitaxial growth step in which a second conductivity type InP layer is sequentially grown so that the layer can be stopped at the edge of the groove, and a part of the middle of the two grooves is grown from the epitaxial growth layer side. -y'
1. A method for manufacturing a buried heterostructure semiconductor laser/photodiode optical integrated device, comprising the step of etching and removing up to the Py' layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56138953A JPS5840881A (en) | 1981-09-03 | 1981-09-03 | Manufacture of buried hetero-structure semiconductor laser-photodiode beam integrating element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56138953A JPS5840881A (en) | 1981-09-03 | 1981-09-03 | Manufacture of buried hetero-structure semiconductor laser-photodiode beam integrating element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5840881A true JPS5840881A (en) | 1983-03-09 |
Family
ID=15234014
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56138953A Pending JPS5840881A (en) | 1981-09-03 | 1981-09-03 | Manufacture of buried hetero-structure semiconductor laser-photodiode beam integrating element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5840881A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0405801A2 (en) * | 1989-06-26 | 1991-01-02 | AT&T Corp. | Optical amplifier-photodetector assemblage |
| EP0405800A2 (en) * | 1989-06-26 | 1991-01-02 | AT&T Corp. | Laser-photodetector assemblage |
| EP0449636A2 (en) * | 1990-03-28 | 1991-10-02 | Xerox Corporation | Laser apparatus with means for detecting the laser power level |
| US5252513A (en) * | 1990-03-28 | 1993-10-12 | Xerox Corporation | Method for forming a laser and light detector on a semiconductor substrate |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS521439A (en) * | 1975-06-23 | 1977-01-07 | Joji Koyanagi | Type coaxial lighting conductor |
-
1981
- 1981-09-03 JP JP56138953A patent/JPS5840881A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS521439A (en) * | 1975-06-23 | 1977-01-07 | Joji Koyanagi | Type coaxial lighting conductor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0405801A2 (en) * | 1989-06-26 | 1991-01-02 | AT&T Corp. | Optical amplifier-photodetector assemblage |
| EP0405800A2 (en) * | 1989-06-26 | 1991-01-02 | AT&T Corp. | Laser-photodetector assemblage |
| EP0449636A2 (en) * | 1990-03-28 | 1991-10-02 | Xerox Corporation | Laser apparatus with means for detecting the laser power level |
| US5252513A (en) * | 1990-03-28 | 1993-10-12 | Xerox Corporation | Method for forming a laser and light detector on a semiconductor substrate |
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