JPS5840427B2 - Thyristor phase control circuit - Google Patents
Thyristor phase control circuitInfo
- Publication number
- JPS5840427B2 JPS5840427B2 JP11109277A JP11109277A JPS5840427B2 JP S5840427 B2 JPS5840427 B2 JP S5840427B2 JP 11109277 A JP11109277 A JP 11109277A JP 11109277 A JP11109277 A JP 11109277A JP S5840427 B2 JPS5840427 B2 JP S5840427B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- power supply
- thyrisk
- rectified power
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Power Conversion In General (AREA)
Description
【発明の詳細な説明】
この発明はサイリスクの位相制御回路に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Cyrisk phase control circuit.
従来のサイリスクの位相制御回路たとえば調光またはヒ
ータの温度制御等に用いられているものは、負荷が比較
的高い定格電圧を持っているため、電源の最大電圧を印
加しても負荷には異常が生じなかった。In conventional Cyrisk phase control circuits, such as those used for dimming or temperature control of heaters, the load has a relatively high rated voltage, so even if the maximum voltage of the power supply is applied, there is no abnormality in the load. did not occur.
しかし、テレビジョン受像機のブランン管のヒータ等の
負荷の定格電圧が１０ｖ以下のものに、トランスを用い
ずに直接ＡＣ１００Ｖ５０／６０Ｈｚの商用電源を位相
制御して電力を供給する場合、すなわち、電源の電圧に
比べて負荷の定格電圧が非常に低い場合、負荷に加えら
れる最大印加電圧と実効電圧との間には大きな差があり
、負荷の寿命を縮めるという欠点があった。However, when supplying power directly to a load with a rated voltage of 10V or less, such as a Blank tube heater in a television receiver, by controlling the phase of an AC 100V 50/60Hz commercial power source without using a transformer, When the rated voltage of the load is very low compared to the voltage of the load, there is a large difference between the maximum applied voltage applied to the load and the effective voltage, which has the disadvantage of shortening the life of the load.
したがって、この発明の目的は、負荷に印加する実効電
圧を下げることなく最大印加電圧を低く押えることがで
きるサイリスクの位相制御回路を提供することである。Therefore, an object of the present invention is to provide a phase control circuit that can keep the maximum applied voltage low without lowering the effective voltage applied to the load.
この発明の一実施例を第１図に示す。An embodiment of this invention is shown in FIG.
すなわち、このサイリスクの位相制御回路は、抵抗１、
コンデンサ２、コイル３，４、トランジスタ５、コンデ
ンサ６、抵抗７、サイリスタ８および負性抵抗素子９で
構成されている。That is, this Cyrisk phase control circuit has a resistor of 1,
It is composed of a capacitor 2, coils 3 and 4, a transistor 5, a capacitor 6, a resistor 7, a thyristor 8, and a negative resistance element 9.
この場合、抵抗１、コンデンサ２、コイル３，４、トラ
ンジスタ５およびコンデンサ６は転流回路ＴＤを構成し
ている。In this case, the resistor 1, capacitor 2, coils 3 and 4, transistor 5, and capacitor 6 constitute a commutation circuit TD.
すなわち、コイル３，４は、同じコアに巻装してあり、
トランジスタ５とでブロッキング発振回路を構成し、こ
のブロッキング発振回路の発振開始電圧■１を設定する
。That is, the coils 3 and 4 are wound around the same core,
A blocking oscillation circuit is formed with the transistor 5, and an oscillation start voltage (1) of this blocking oscillation circuit is set.
発振開始電圧■１ において発振を開始すると、トラン
ジスタ５のターンオフ時においてコイル４には高電圧の
逆起電圧が発生し、この逆起電圧によりコンデンサ６を
通してサイリスタ８のカソードに正のパルスを印加する
ことでサイリスタ８をターンオフさせる。When oscillation starts at the oscillation start voltage 1, a high voltage back electromotive force is generated in the coil 4 when the transistor 5 is turned off, and this back electromotive voltage applies a positive pulse to the cathode of the thyristor 8 through the capacitor 6. This turns off the thyristor 8.
また、トリガ用抵抗７は、転流回路ＴＤが動作する電圧
と同電圧になると負性抵抗素子９がオン状態になるよう
に、その値が設定されている。Further, the value of the trigger resistor 7 is set so that the negative resistance element 9 is turned on when the voltage becomes the same as the voltage at which the commutation circuit TD operates.
なお、１０は負荷、１１は整流器、１２および１３は端
子である。Note that 10 is a load, 11 is a rectifier, and 12 and 13 are terminals.
つぎに、この実施例の動作について説明する。Next, the operation of this embodiment will be explained.
まず、端子１２．１３間に商用電源（図示せず）が接続
されると、整流器１１から第２図ａに示すような両波整
流された電圧が出力される。First, when a commercial power source (not shown) is connected between terminals 12 and 13, a double-wave rectified voltage as shown in FIG. 2a is output from the rectifier 11.
この整流器１１の出力電圧をサイリスクの位相制御回路
に入力すると、第２図すに示すような電流が負荷１０に
流れる。When the output voltage of the rectifier 11 is input to the Cyrisk phase control circuit, a current as shown in FIG. 2 flows through the load 10.
すなわち、時刻Ｔ。から時刻Ｔ１までの整流器１１の出
力電圧が発振開始電圧■１ より低い間はブロッキング
発振回路は発振せず、サイリスタ８のカソード電圧は第
３図に示すように正弦波状であり、かつ負性抵抗素子９
がオフ状態でありサイリスタ８が抵抗７を通してトリガ
されてオン状態になり、負荷１０に電力が供給される。That is, time T. The blocking oscillation circuit does not oscillate while the output voltage of the rectifier 11 from to time T1 is lower than the oscillation start voltage ■1, and the cathode voltage of the thyristor 8 is sinusoidal as shown in FIG. Element 9
is in the off state, and the thyristor 8 is triggered through the resistor 7 to be in the on state, and power is supplied to the load 10.
時刻Ｔ１で整流器１１の出力電圧が所定の発振開始電圧
ｖ１を越えると、負性抵抗素子９がオン状態になってサ
イリスク８へのゲート電流がなくなりサイリスタ８への
トリガが停止する。When the output voltage of the rectifier 11 exceeds a predetermined oscillation start voltage v1 at time T1, the negative resistance element 9 is turned on, the gate current to the thyristor 8 disappears, and the triggering to the thyristor 8 is stopped.
この状態において、転流回路ＴＤのコイル４の出力がコ
ンデンサ６を介して第３図に示すようにサイリスタ８の
カソードに印加されるので、サイリスタ８のアノード・
カソード間には逆バイアスが印加され、サイリスク８を
非導通状態にして負荷１０への電力の供給を停止し、時
刻Ｔ１から時刻Ｔ２の期間はこの状態が保持される。In this state, the output of the coil 4 of the commutation circuit TD is applied to the cathode of the thyristor 8 via the capacitor 6 as shown in FIG.
A reverse bias is applied between the cathodes, turning the cyrisk 8 into a non-conductive state and stopping the supply of power to the load 10, and this state is maintained during the period from time T1 to time T2.
時刻Ｔ２で整流器１１の出力電圧が所定の発振開始電圧
ｖ１ よりも低くなり、負性抵抗素子９がオフ状態にな
るとともに転流回路ＴＤが動作を停止し、サイリスタ８
が再びトリガされてオン状態になり、負荷１０に電力が
供給され、時刻Ｔ２から時刻Ｔ３の期間この状態が保持
される。At time T2, the output voltage of the rectifier 11 becomes lower than the predetermined oscillation start voltage v1, the negative resistance element 9 turns off, the commutation circuit TD stops operating, and the thyristor 8
is triggered again to turn on, power is supplied to the load 10, and this state is maintained for a period from time T2 to time T3.
これ以後は上述の動作と同じ動作を繰返す。After this, the same operations as those described above are repeated.
このように構成することにより、負荷に印加する実効電
圧を下げることなく最大印加電圧を低く押えることがで
き、電源の電圧に比較してかなり小さい定格電圧の負荷
に対してもその寿命を縮めることなく電力を供給できる
。With this configuration, the maximum applied voltage can be kept low without lowering the effective voltage applied to the load, and the life of the load can be shortened even for loads whose rated voltage is considerably lower than the voltage of the power supply. power can be supplied without any need for electricity.
以上のように、この発明のサイリスクの位相制御回路は
、整流電源の正極にアノードを接続したサイリスクと、
このサイリスクのアノード・ゲート間に接続したトリガ
用抵抗と、前記サイリスクのカソードと前記整流電源の
負極との間に接続した負荷と、前記サイリスクのゲート
と前記整流電源の負極との間に接続して前記整流電源の
電圧が所定の値以上の期間中オンとなることにより前記
サイリスタのゲート電流をバイパスする負性抵抗素子と
、前記整流電源の正極に一端を接続した第１のコイルと
、この第１のコイルの他端と前記整流電源の負極との間
に接続したトランジスタと、前記整流電源の正極に一端
を接続した抵抗と、この抵抗の他端と前記整流電源の負
極との間に接続した第１のコンデンサと、前記第１のコ
イルと電磁結合して前記トランジスタのベースと前記抵
抗および第１のコンデンサの接続点との間に接続した第
２のコイルとからなり、前記整流電源の電圧が前記負性
抵抗素子をオンにさせる電圧を越えたときに発振開始す
るように発振開始電圧を設定し、前記第１のコイルおよ
び前記トランジスタの接続点を第２のコンデンサを介し
て前記サイリスクのカソードに接続したブロッキング発
振回路とを備え、前記整流電源の電圧が前記負性抵抗素
子をオンにさせる電圧を越えたときに前記サイリスクの
カソードに正のパルスを与えて前記サイリスクをターン
オフさせるようにしたので、整流電源の各半波の中間部
を除いて前縁と後縁の両方でサイリスクが導通すること
になり、その結果、負荷に印加する実効電圧を下げるこ
となく最大印加電圧を低く押えることができるという効
果がある。As described above, the Cyrisk phase control circuit of the present invention includes a Cyrisk whose anode is connected to the positive electrode of a rectified power supply,
A trigger resistor connected between the anode and gate of this Cyrisk, a load connected between the cathode of the Cyrisk and the negative pole of the rectified power supply, and a load connected between the gate of the Cyrisk and the negative pole of the rectified power supply. a negative resistance element that bypasses the gate current of the thyristor by being on during a period when the voltage of the rectifying power source is equal to or higher than a predetermined value; a first coil having one end connected to the positive electrode of the rectifying power source; A transistor connected between the other end of the first coil and the negative pole of the rectified power supply, a resistor whose one end is connected to the positive pole of the rectified power supply, and a transistor connected between the other end of the resistor and the negative pole of the rectified power supply. a first capacitor connected to the rectifying power source, and a second coil electromagnetically coupled to the first coil and connected between the base of the transistor and the connection point of the resistor and the first capacitor; The oscillation start voltage is set so that oscillation starts when the voltage exceeds the voltage that turns on the negative resistance element, and the connection point between the first coil and the transistor is connected to the and a blocking oscillation circuit connected to the cathode of the Cyrisk, and when the voltage of the rectified power supply exceeds the voltage that turns on the negative resistance element, a positive pulse is applied to the cathode of the Cyrisk to turn off the Cyrisk. As a result, the sirisk conducts at both the leading and trailing edges except in the middle of each half-wave of the rectified power supply, and as a result, the maximum applied voltage can be increased without reducing the effective voltage applied to the load. It has the effect of being able to press down low.
第１図はこの発明の一実施例の回路図、第２図ａ、ｂお
よび第３図は第１図の回路の動作を説明するための波形
図である。
１・・・・・・抵抗、２・・・・・・コンデンサ、３，
４・・・・・・コイル、５・・・・・・トランジスタ、
６・・・・・・コンデンサ、７・・・・・・抵抗、８・
・・・・・サイリスク、９・・・・・・負性抵抗素子、
１０・・・・・・負荷、ＴＤ・・・・・・転流回路。FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIGS. 2a, 2b, and 3 are waveform diagrams for explaining the operation of the circuit of FIG. 1. 1...Resistor, 2...Capacitor, 3,
4... Coil, 5... Transistor,
6... Capacitor, 7... Resistor, 8...
...Sirisk, 9...Negative resistance element,
10... Load, TD... Commutation circuit.
Claims (1)
、このサイリスクのアノード・ゲート間に接続したトリ
ガ用抵抗と、前記サイリスクのカソードと前記整流電源
の負極との間に接続した負荷と、前記サイリスクのゲー
トと前記整流電源の負極との間に接続して前記整流電源
の電圧が所定の値以上の期間中オンとなることにより前
記サイリスクのゲート電流をバイパスする負性抵抗素子
と、前記整流電源の正極に一端を接続した第１のコイル
と、この第１のコイルの他端と前記整流電源の負極との
間に接続したトランジスタと、前記整流電源の正極に一
端を接続した抵抗と、この抵抗の他端と前記整流電源の
負極との間に接続した第１のコンデンサと、前記第１の
コイルと電磁結合して前記トランジスタのベースと前記
抵抗および第１のコンデンサの接続点との間に接続した
第２のコイルとからなり、前記整流電源の電圧が前記負
性抵抗素子をオンにさせる電圧を越えたときに発振開始
するように発振開始電圧を設定し、前記第１コイルおよ
び前記トランジスタの接続点を第２のコンデンサを介し
て前記サイリスクのカソードに接続したブロッキング発
振回路とを備え、前記整流電源の電圧が前記負性抵抗素
子をオンにさせる電圧を越えたときに前記サイリスクの
カソードに正のパルスを与えて前記サイリスクをターン
オフさせるようにしたサイリスクの位相制御回路。1. A thyrisk whose anode is connected to the positive electrode of a rectified power supply, a trigger resistor connected between the anode and gate of this thyrisk, a load connected between the cathode of said thyrisk and the negative electrode of said rectified power supply, and a thyrisk's a negative resistance element that is connected between the gate and the negative electrode of the rectified power source and is turned on during a period when the voltage of the rectified power source is equal to or higher than a predetermined value, thereby bypassing the gate current of the thyrisk; a first coil having one end connected to the positive pole; a transistor connected between the other end of the first coil and the negative pole of the rectifying power supply; a resistor having one end connected to the positive pole of the rectifying power supply; and the resistor. a first capacitor connected between the other end and the negative electrode of the rectified power supply; and a first capacitor that is electromagnetically coupled to the first coil and connected between the base of the transistor and the connection point of the resistor and the first capacitor. The oscillation start voltage is set so that oscillation starts when the voltage of the rectified power supply exceeds the voltage that turns on the negative resistance element, and the first coil and the transistor are connected to each other. and a blocking oscillation circuit in which the connection point of the oscillator is connected to the cathode of the thyrisk via a second capacitor, and when the voltage of the rectified power supply exceeds the voltage that turns on the negative resistance element, the cathode of the thyrisk is A phase control circuit for the Cyrisk, which turns off the Cyrisk by applying a positive pulse to the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11109277A JPS5840427B2 (en) | 1977-09-14 | 1977-09-14 | Thyristor phase control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11109277A JPS5840427B2 (en) | 1977-09-14 | 1977-09-14 | Thyristor phase control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5444462A JPS5444462A (en) | 1979-04-07 |
| JPS5840427B2 true JPS5840427B2 (en) | 1983-09-06 |
Family
ID=14552167
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11109277A Expired JPS5840427B2 (en) | 1977-09-14 | 1977-09-14 | Thyristor phase control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5840427B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6212428A (en) * | 1985-07-11 | 1987-01-21 | Kubota Ltd | Hydraulic pump setting structure in farm tractor |
| JPH0511063Y2 (en) * | 1985-07-10 | 1993-03-18 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE8106447L (en) * | 1981-11-02 | 1983-05-03 | Bror Allan Eriksson | CONSTANT POWER CONTROL DEVICE |
| US4675798A (en) * | 1985-07-15 | 1987-06-23 | Harris Corporation | Direct coupled switching power supply with GTO SCR switching element |
| WO2005114823A1 (en) * | 2004-05-24 | 2005-12-01 | Young-Chang Cho | Method for controlling lo w- voltage using waves ac and system for performing the same |
-
1977
- 1977-09-14 JP JP11109277A patent/JPS5840427B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0511063Y2 (en) * | 1985-07-10 | 1993-03-18 | ||
| JPS6212428A (en) * | 1985-07-11 | 1987-01-21 | Kubota Ltd | Hydraulic pump setting structure in farm tractor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5444462A (en) | 1979-04-07 |
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